From fb5d60dafb52c76773b4d1942b1843a04fd14eb0 Mon Sep 17 00:00:00 2001 From: Premysl Houdek Date: Thu, 12 Nov 2015 23:11:27 +0100 Subject: bsp/tms570: EMAC control header file corrected and EMAC interrupt vector added Signed-off-by: Premysl Houdek Signed-off-by: Pavel Pisa --- c/src/lib/libbsp/arm/tms570/Makefile.am | 2 +- c/src/lib/libbsp/arm/tms570/include/irq.h | 4 + .../libbsp/arm/tms570/include/ti_herc/reg_emac.h | 230 ----------------- .../libbsp/arm/tms570/include/ti_herc/reg_emacc.h | 285 +++++++++++++++++++++ c/src/lib/libbsp/arm/tms570/include/tms570.h | 4 +- c/src/lib/libbsp/arm/tms570/preinstall.am | 6 +- 6 files changed, 295 insertions(+), 236 deletions(-) delete mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emac.h create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emacc.h (limited to 'c/src/lib/libbsp') diff --git a/c/src/lib/libbsp/arm/tms570/Makefile.am b/c/src/lib/libbsp/arm/tms570/Makefile.am index b9c7fd4f14..a278aa2d0e 100644 --- a/c/src/lib/libbsp/arm/tms570/Makefile.am +++ b/c/src/lib/libbsp/arm/tms570/Makefile.am @@ -50,7 +50,7 @@ include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_dcc.h include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_dma.h include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_dmm.h include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_efuse.h -include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_emac.h +include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_emacc.h include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_emacm.h include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_emif.h include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_esm.h diff --git a/c/src/lib/libbsp/arm/tms570/include/irq.h b/c/src/lib/libbsp/arm/tms570/include/irq.h index f35e7fe5ca..2952582453 100644 --- a/c/src/lib/libbsp/arm/tms570/include/irq.h +++ b/c/src/lib/libbsp/arm/tms570/include/irq.h @@ -103,6 +103,10 @@ #define TMS570_IRQ_HET2_LEVEL_1 73 #define TMS570_IRQ_SCI2_LEVEL_1 74 #define TMS570_IRQ_HET_TU2_LEVEL_1 75 +#define TMS570_IRQ_EMAC_MISC 76 +#define TMS570_IRQ_EMAC_TX 77 +#define TMS570_IRQ_EMAC_THRESH 78 +#define TMS570_IRQ_EMAC_RX 79 #define TMS570_IRQ_HWA_INT_REQ_H 80 #define TMS570_IRQ_HWA_INT_REQ_H 81 #define TMS570_IRQ_DCC_DONE_INTERRUPT 82 diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emac.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emac.h deleted file mode 100644 index 31fe7ef2fd..0000000000 --- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emac.h +++ /dev/null @@ -1,230 +0,0 @@ -/* The header file is generated by make_header.py from EMAC.json */ -/* Current script's version can be found at: */ -/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ - -/* - * Copyright (c) 2014-2015, Premysl Houdek - * - * Czech Technical University in Prague - * Zikova 1903/4 - * 166 36 Praha 6 - * Czech Republic - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * The views and conclusions contained in the software and documentation are those - * of the authors and should not be interpreted as representing official policies, - * either expressed or implied, of the FreeBSD Project. -*/ -#ifndef LIBBSP_ARM_TMS570_EMAC -#define LIBBSP_ARM_TMS570_EMAC - -#include - -typedef struct{ - uint32_t REVID; /*MDIO Revision ID Register*/ - uint32_t CONTROL; /*MDIO Control Register*/ - uint32_t ALIVE; /*PHY Alive Status register*/ - uint32_t LINK; /*PHY Link Status Register*/ - uint32_t LINKINTRAW; /*MDIO Link Status Change Interrupt (Unmasked) Register*/ - uint32_t LINKINTMASKED; /*MDIO Link Status Change Interrupt (Masked) Register*/ - uint8_t reserved1 [8]; - uint32_t USERINTRAW; /*MDIO User Command Complete Interrupt (Unmasked) Register*/ - uint32_t USERINTMASKED; /*MDIO User Command Complete Interrupt (Masked) Register*/ - uint32_t USERINTMASKSET; /*MDIO User Command Complete Interrupt Mask Set Register*/ - uint32_t USERINTMASKCLEAR; /*MDIO User Command Complete Interrupt Mask Clear Register*/ - uint8_t reserved2 [80]; - uint32_t USERACCESS0; /*MDIO User Access Register 0*/ - uint32_t USERPHYSEL0; /*MDIO User PHY Select Register 0*/ - uint32_t USERACCESS1; /*MDIO User Access Register 1*/ - uint32_t USERPHYSEL1; /*MDIO User PHY Select Register 1*/ -} tms570_emac_t; - - -/*---------------------TMS570_EMAC_REVID---------------------*/ -/* field: REV - Identifies the MDIO Module revision. */ -/* Whole 32 bits */ - -/*--------------------TMS570_EMAC_CONTROL--------------------*/ -/* field: IDLE - State machine IDLE status bit. */ -#define TMS570_EMAC_CONTROL_IDLE BSP_BIT32(31) - -/* field: ENABLE - State machine enable control bit. */ -#define TMS570_EMAC_CONTROL_ENABLE BSP_BIT32(30) - -/* field: HIGHEST_USER_CHANNEL - Highest user channel that is available in the module. It is currently set to 1. */ -#define TMS570_EMAC_CONTROL_HIGHEST_USER_CHANNEL(val) BSP_FLD32(val,24, 28) -#define TMS570_EMAC_CONTROL_HIGHEST_USER_CHANNEL_GET(reg) BSP_FLD32GET(reg,24, 28) -#define TMS570_EMAC_CONTROL_HIGHEST_USER_CHANNEL_SET(reg,val) BSP_FLD32SET(reg, val,24, 28) - -/* field: PREAMBLE - Preamble disable */ -#define TMS570_EMAC_CONTROL_PREAMBLE BSP_BIT32(20) - -/* field: FAULT - Fault indicator. */ -#define TMS570_EMAC_CONTROL_FAULT BSP_BIT32(19) - -/* field: FAULTENB - Fault detect enable. */ -#define TMS570_EMAC_CONTROL_FAULTENB BSP_BIT32(18) - -/* field: CLKDIV - Clock Divider bits. */ -#define TMS570_EMAC_CONTROL_CLKDIV(val) BSP_FLD32(val,0, 15) -#define TMS570_EMAC_CONTROL_CLKDIV_GET(reg) BSP_FLD32GET(reg,0, 15) -#define TMS570_EMAC_CONTROL_CLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) - - -/*---------------------TMS570_EMAC_ALIVE---------------------*/ -/* field: ALIVE - MDIO Alive bits. */ -/* Whole 32 bits */ - -/*----------------------TMS570_EMAC_LINK----------------------*/ -/* field: LINK - MDIO Link state bits. This register is updated after a read of the generic status register of a PHY. */ -/* Whole 32 bits */ - -/*-------------------TMS570_EMAC_LINKINTRAW-------------------*/ -/* field: USERPHY1 - MDIO Link change event, raw value. */ -#define TMS570_EMAC_LINKINTRAW_USERPHY1 BSP_BIT32(1) - -/* field: USERPHY0 - MDIO Link change event, raw value. */ -#define TMS570_EMAC_LINKINTRAW_USERPHY0 BSP_BIT32(0) - - -/*-----------------TMS570_EMAC_LINKINTMASKED-----------------*/ -/* field: USERPHY1 - MDIO Link change interrupt, masked value. */ -#define TMS570_EMAC_LINKINTMASKED_USERPHY1 BSP_BIT32(1) - -/* field: USERPHY0 - MDIO Link change interrupt, masked value. */ -#define TMS570_EMAC_LINKINTMASKED_USERPHY0 BSP_BIT32(0) - - -/*-------------------TMS570_EMAC_USERINTRAW-------------------*/ -/* field: USERACCESS1 - MDIO User command complete event bit. */ -#define TMS570_EMAC_USERINTRAW_USERACCESS1 BSP_BIT32(1) - -/* field: USERACCESS0 - MDIO User command complete event bit. */ -#define TMS570_EMAC_USERINTRAW_USERACCESS0 BSP_BIT32(0) - - -/*-----------------TMS570_EMAC_USERINTMASKED-----------------*/ -/* field: USERACCESS1 - Masked value of MDIO User command complete interrupt. */ -#define TMS570_EMAC_USERINTMASKED_USERACCESS1 BSP_BIT32(1) - -/* field: USERACCESS0 - Masked value of MDIO User command complete interrupt. */ -#define TMS570_EMAC_USERINTMASKED_USERACCESS0 BSP_BIT32(0) - - -/*-----------------TMS570_EMAC_USERINTMASKSET-----------------*/ -/* field: USERACCESS1 - MDIO user interrupt mask set for USERINTMASKED[1]. */ -#define TMS570_EMAC_USERINTMASKSET_USERACCESS1 BSP_BIT32(1) - -/* field: USERACCESS0 - MDIO user interrupt mask set for USERINTMASKED[0]. */ -#define TMS570_EMAC_USERINTMASKSET_USERACCESS0 BSP_BIT32(0) - - -/*----------------TMS570_EMAC_USERINTMASKCLEAR----------------*/ -/* field: USERACCESS1 - MDIO user command complete interrupt mask clear for USERINTMASKED[1]. */ -#define TMS570_EMAC_USERINTMASKCLEAR_USERACCESS1 BSP_BIT32(1) - -/* field: USERACCESS0 - MDIO user command complete interrupt mask clear for USERINTMASKED[0]. */ -#define TMS570_EMAC_USERINTMASKCLEAR_USERACCESS0 BSP_BIT32(0) - - -/*------------------TMS570_EMAC_USERACCESS0------------------*/ -/* field: GO - Go bit. */ -#define TMS570_EMAC_USERACCESS0_GO BSP_BIT32(31) - -/* field: WRITE - Write enable bit. */ -#define TMS570_EMAC_USERACCESS0_WRITE BSP_BIT32(30) - -/* field: ACK - Acknowledge bit. This bit is set if the PHY acknowledged the read transaction. */ -#define TMS570_EMAC_USERACCESS0_ACK BSP_BIT32(29) - -/* field: REGADR - Register address bits. */ -#define TMS570_EMAC_USERACCESS0_REGADR(val) BSP_FLD32(val,21, 25) -#define TMS570_EMAC_USERACCESS0_REGADR_GET(reg) BSP_FLD32GET(reg,21, 25) -#define TMS570_EMAC_USERACCESS0_REGADR_SET(reg,val) BSP_FLD32SET(reg, val,21, 25) - -/* field: PHYADR - PHY address bits. This field specifies the PHY to be accessed for this transaction. */ -#define TMS570_EMAC_USERACCESS0_PHYADR(val) BSP_FLD32(val,16, 20) -#define TMS570_EMAC_USERACCESS0_PHYADR_GET(reg) BSP_FLD32GET(reg,16, 20) -#define TMS570_EMAC_USERACCESS0_PHYADR_SET(reg,val) BSP_FLD32SET(reg, val,16, 20) - -/* field: DATA - User data bits. */ -#define TMS570_EMAC_USERACCESS0_DATA(val) BSP_FLD32(val,0, 15) -#define TMS570_EMAC_USERACCESS0_DATA_GET(reg) BSP_FLD32GET(reg,0, 15) -#define TMS570_EMAC_USERACCESS0_DATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) - - -/*------------------TMS570_EMAC_USERPHYSEL0------------------*/ -/* field: LINKSEL - Link status determination select bit. */ -#define TMS570_EMAC_USERPHYSEL0_LINKSEL BSP_BIT32(7) - -/* field: LINKINTENB - Link change interrupt enable. */ -#define TMS570_EMAC_USERPHYSEL0_LINKINTENB BSP_BIT32(6) - -/* field: PHYADRMON - PHY address whose link status is to be monitored. */ -#define TMS570_EMAC_USERPHYSEL0_PHYADRMON(val) BSP_FLD32(val,0, 4) -#define TMS570_EMAC_USERPHYSEL0_PHYADRMON_GET(reg) BSP_FLD32GET(reg,0, 4) -#define TMS570_EMAC_USERPHYSEL0_PHYADRMON_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) - - -/*------------------TMS570_EMAC_USERACCESS1------------------*/ -/* field: GO - Go bit. */ -#define TMS570_EMAC_USERACCESS1_GO BSP_BIT32(31) - -/* field: WRITE - Write enable bit. */ -#define TMS570_EMAC_USERACCESS1_WRITE BSP_BIT32(30) - -/* field: ACK - Acknowledge bit. This bit is set if the PHY acknowledged the read transaction. */ -#define TMS570_EMAC_USERACCESS1_ACK BSP_BIT32(29) - -/* field: REGADR - Register address bits. */ -#define TMS570_EMAC_USERACCESS1_REGADR(val) BSP_FLD32(val,21, 25) -#define TMS570_EMAC_USERACCESS1_REGADR_GET(reg) BSP_FLD32GET(reg,21, 25) -#define TMS570_EMAC_USERACCESS1_REGADR_SET(reg,val) BSP_FLD32SET(reg, val,21, 25) - -/* field: PHYADR - PHY address bits. This field specifies the PHY to be accessed for this transaction. */ -#define TMS570_EMAC_USERACCESS1_PHYADR(val) BSP_FLD32(val,16, 20) -#define TMS570_EMAC_USERACCESS1_PHYADR_GET(reg) BSP_FLD32GET(reg,16, 20) -#define TMS570_EMAC_USERACCESS1_PHYADR_SET(reg,val) BSP_FLD32SET(reg, val,16, 20) - -/* field: DATA - User data bits. */ -#define TMS570_EMAC_USERACCESS1_DATA(val) BSP_FLD32(val,0, 15) -#define TMS570_EMAC_USERACCESS1_DATA_GET(reg) BSP_FLD32GET(reg,0, 15) -#define TMS570_EMAC_USERACCESS1_DATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) - - -/*------------------TMS570_EMAC_USERPHYSEL1------------------*/ -/* field: LINKSEL - Link status determination select bit. */ -#define TMS570_EMAC_USERPHYSEL1_LINKSEL BSP_BIT32(7) - -/* field: LINKINTENB - Link change interrupt enable. */ -#define TMS570_EMAC_USERPHYSEL1_LINKINTENB BSP_BIT32(6) - -/* field: PHYADRMON - PHY address whose link status is to be monitored. */ -#define TMS570_EMAC_USERPHYSEL1_PHYADRMON(val) BSP_FLD32(val,0, 4) -#define TMS570_EMAC_USERPHYSEL1_PHYADRMON_GET(reg) BSP_FLD32GET(reg,0, 4) -#define TMS570_EMAC_USERPHYSEL1_PHYADRMON_SET(reg,val) BSP_FLD32SET(reg, val,0, 4) - - - -#endif /* LIBBSP_ARM_TMS570_EMAC */ diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emacc.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emacc.h new file mode 100644 index 0000000000..c7c564cf49 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emacc.h @@ -0,0 +1,285 @@ +/* The header file is generated by make_header.py from EMACC.json */ +/* Current script's version can be found at: */ +/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ + +/* + * Copyright (c) 2014-2015, Premysl Houdek + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are those + * of the authors and should not be interpreted as representing official policies, + * either expressed or implied, of the FreeBSD Project. +*/ +#ifndef LIBBSP_ARM_TMS570_EMACC +#define LIBBSP_ARM_TMS570_EMACC + +#include + +typedef struct{ + uint32_t REVID; /*EMAC Control Module Revision ID Register*/ + uint32_t SOFTRESET; /*EMAC Control Module Software Reset Register*/ + uint8_t reserved1 [4]; + uint32_t INTCONTROL; /*EMAC Control Module Interrupt Control Register*/ + uint32_t C0RXTHRESHEN; /*EMAC Control Module Receive Threshold Interrupt Enable Register*/ + uint32_t C0RXEN; /*EMAC Control Module Receive Interrupt Enable Register*/ + uint32_t C0TXEN; /*EMAC Control Module Transmit Interrupt Enable Register*/ + uint32_t C0MISCEN; /*EMAC Control Module Miscellaneous Interrupt Enable Register*/ + uint8_t reserved2 [32]; + uint32_t C0RXTHRESHSTAT; /*EMAC Control Module Receive Threshold Interrupt Status Register*/ + uint32_t C0RXSTAT; /*EMAC Control Module Receive Interrupt Status Register*/ + uint32_t C0TXSTAT; /*EMAC Control Module Transmit Interrupt Status Register*/ + uint32_t C0MISCSTAT; /*EMAC Control Module Miscellaneous Interrupt Status Register*/ + uint8_t reserved3 [32]; + uint32_t C0RXIMAX; /*EMAC Control Module Receive Interrupts Per Millisecond Register*/ + uint32_t C0TXIMAX; /*EMAC Control Module Transmit Interrupts Per Millisecond Register*/ +} tms570_emacc_t; + + +/*---------------------TMS570_EMACC_REVID---------------------*/ +/* field: REV - Identifies the EMAC Control Module revision. */ +/* Whole 32 bits */ + +/*-------------------TMS570_EMACC_SOFTRESET-------------------*/ +/* field: RESET - Software reset bit for the EMAC Control Module. */ +#define TMS570_EMACC_SOFTRESET_RESET BSP_BIT32(0) + + +/*------------------TMS570_EMACC_INTCONTROL------------------*/ +/* field: C0TXPACEEN - Enable pacing for TX interrupt pulse generation */ +#define TMS570_EMACC_INTCONTROL_C0TXPACEEN BSP_BIT32(17) + +/* field: C0RXPACEEN - Enable pacing for RX interrupt pulse generation */ +#define TMS570_EMACC_INTCONTROL_C0RXPACEEN BSP_BIT32(16) + +/* field: INTPRESCALE - Number of internal EMAC module reference clock periods within a 4 us time window (see */ +#define TMS570_EMACC_INTCONTROL_INTPRESCALE(val) BSP_FLD32(val,0, 11) +#define TMS570_EMACC_INTCONTROL_INTPRESCALE_GET(reg) BSP_FLD32GET(reg,0, 11) +#define TMS570_EMACC_INTCONTROL_INTPRESCALE_SET(reg,val) BSP_FLD32SET(reg, val,0, 11) + + +/*-----------------TMS570_EMACC_C0RXTHRESHEN-----------------*/ +/* field: RXCH7THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 7 */ +#define TMS570_EMACC_C0RXTHRESHEN_RXCH7THRESHEN BSP_BIT32(7) + +/* field: RXCH6THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 6 */ +#define TMS570_EMACC_C0RXTHRESHEN_RXCH6THRESHEN BSP_BIT32(6) + +/* field: RXCH5THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 5 */ +#define TMS570_EMACC_C0RXTHRESHEN_RXCH5THRESHEN BSP_BIT32(5) + +/* field: RXCH4THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 4 */ +#define TMS570_EMACC_C0RXTHRESHEN_RXCH4THRESHEN BSP_BIT32(4) + +/* field: RXCH3THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 3 */ +#define TMS570_EMACC_C0RXTHRESHEN_RXCH3THRESHEN BSP_BIT32(3) + +/* field: RXCH2THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 2 */ +#define TMS570_EMACC_C0RXTHRESHEN_RXCH2THRESHEN BSP_BIT32(2) + +/* field: RXCH1THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 1 */ +#define TMS570_EMACC_C0RXTHRESHEN_RXCH1THRESHEN BSP_BIT32(1) + +/* field: RXCH0THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 0 */ +#define TMS570_EMACC_C0RXTHRESHEN_RXCH0THRESHEN BSP_BIT32(0) + + +/*--------------------TMS570_EMACC_C0RXEN--------------------*/ +/* field: RXCH7EN - Enable C0RXPULSE interrupt generation for RX Channel 7 */ +#define TMS570_EMACC_C0RXEN_RXCH7EN BSP_BIT32(7) + +/* field: RXCH6EN - Enable C0RXPULSE interrupt generation for RX Channel 6 */ +#define TMS570_EMACC_C0RXEN_RXCH6EN BSP_BIT32(6) + +/* field: RXCH5EN - Enable C0RXPULSE interrupt generation for RX Channel 5 */ +#define TMS570_EMACC_C0RXEN_RXCH5EN BSP_BIT32(5) + +/* field: RXCH4EN - Enable C0RXPULSE interrupt generation for RX Channel 4 */ +#define TMS570_EMACC_C0RXEN_RXCH4EN BSP_BIT32(4) + +/* field: RXCH3EN - Enable C0RXPULSE interrupt generation for RX Channel 3 */ +#define TMS570_EMACC_C0RXEN_RXCH3EN BSP_BIT32(3) + +/* field: RXCH2EN - Enable C0RXPULSE interrupt generation for RX Channel 2 */ +#define TMS570_EMACC_C0RXEN_RXCH2EN BSP_BIT32(2) + +/* field: RXCH1EN - Enable C0RXPULSE interrupt generation for RX Channel 1 */ +#define TMS570_EMACC_C0RXEN_RXCH1EN BSP_BIT32(1) + +/* field: RXCH0EN - Enable C0RXPULSE interrupt generation for RX Channel 0 */ +#define TMS570_EMACC_C0RXEN_RXCH0EN BSP_BIT32(0) + + +/*--------------------TMS570_EMACC_C0TXEN--------------------*/ +/* field: TXCH7EN - Enable C0TXPULSE interrupt generation for TX Channel 7 */ +#define TMS570_EMACC_C0TXEN_TXCH7EN BSP_BIT32(7) + +/* field: TXCH6EN - TXCH6EN */ +#define TMS570_EMACC_C0TXEN_TXCH6EN BSP_BIT32(6) + +/* field: TXCH5EN - Enable C0TXPULSE interrupt generation for TX Channel 5 */ +#define TMS570_EMACC_C0TXEN_TXCH5EN BSP_BIT32(5) + +/* field: TXCH4EN - Enable C0TXPULSE interrupt generation for TX Channel 4 */ +#define TMS570_EMACC_C0TXEN_TXCH4EN BSP_BIT32(4) + +/* field: TXCH3EN - Enable C0TXPULSE interrupt generation for TX Channel 3 */ +#define TMS570_EMACC_C0TXEN_TXCH3EN BSP_BIT32(3) + +/* field: TXCH2EN - Enable C0TXPULSE interrupt generation for TX Channel 2 */ +#define TMS570_EMACC_C0TXEN_TXCH2EN BSP_BIT32(2) + +/* field: TXCH1EN - Enable C0TXPULSE interrupt generation for TX Channel 1 */ +#define TMS570_EMACC_C0TXEN_TXCH1EN BSP_BIT32(1) + +/* field: TXCH0EN - Enable C0TXPULSE interrupt generation for TX Channel 0 */ +#define TMS570_EMACC_C0TXEN_TXCH0EN BSP_BIT32(0) + + +/*-------------------TMS570_EMACC_C0MISCEN-------------------*/ +/* field: STATPENDEN - Enable C0MISCPULSE interrupt generation when EMAC statistics interrupts are generated */ +#define TMS570_EMACC_C0MISCEN_STATPENDEN BSP_BIT32(3) + +/* field: HOSTPENDEN - HOSTPENDEN */ +#define TMS570_EMACC_C0MISCEN_HOSTPENDEN BSP_BIT32(2) + +/* field: LINKINT0EN - Enable C0MISCPULSE interrupt generation when MDIO LINKINT0 interrupts (corresponding to */ +#define TMS570_EMACC_C0MISCEN_LINKINT0EN BSP_BIT32(1) + +/* field: USERINT0EN - Enable C0MISCPULSE interrupt generation when MDIO USERINT0 interrupts (corresponding */ +#define TMS570_EMACC_C0MISCEN_USERINT0EN BSP_BIT32(0) + + +/*----------------TMS570_EMACC_C0RXTHRESHSTAT----------------*/ +/* field: RXCH7THRESHSTAT - Interrupt status for RX Channel 7 masked by the C0RXTHRESHEN register */ +#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH7THRESHSTAT BSP_BIT32(7) + +/* field: RXCH6THRESHSTAT - Interrupt status for RX Channel 6 masked by the C0RXTHRESHEN register */ +#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH6THRESHSTAT BSP_BIT32(6) + +/* field: RXCH5THRESHSTAT - Interrupt status for RX Channel 5 masked by the C0RXTHRESHEN register */ +#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH5THRESHSTAT BSP_BIT32(5) + +/* field: RXCH4THRESHSTAT - Interrupt status for RX Channel 4 masked by the C0RXTHRESHEN register */ +#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH4THRESHSTAT BSP_BIT32(4) + +/* field: RXCH3THRESHSTAT - Interrupt status for RX Channel 3 masked by the C0RXTHRESHEN register */ +#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH3THRESHSTAT BSP_BIT32(3) + +/* field: RXCH2THRESHSTAT - Interrupt status for RX Channel 2 masked by the C0RXTHRESHEN register */ +#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH2THRESHSTAT BSP_BIT32(2) + +/* field: RXCH1THRESHSTAT - Interrupt status for RX Channel 1 masked by the C0RXTHRESHEN register */ +#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH1THRESHSTAT BSP_BIT32(1) + +/* field: RXCH0THRESHSTAT - Interrupt status for RX Channel 0 masked by the C0RXTHRESHEN register */ +#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH0THRESHSTAT BSP_BIT32(0) + + +/*-------------------TMS570_EMACC_C0RXSTAT-------------------*/ +/* field: RXCH7STAT - RXCH7STAT */ +#define TMS570_EMACC_C0RXSTAT_RXCH7STAT BSP_BIT32(7) + +/* field: RXCH6STAT - Interrupt status for RX Channel 6 masked by the C0RXEN register */ +#define TMS570_EMACC_C0RXSTAT_RXCH6STAT BSP_BIT32(6) + +/* field: RXCH5STAT - Interrupt status for RX Channel 5 masked by the C0RXEN register */ +#define TMS570_EMACC_C0RXSTAT_RXCH5STAT BSP_BIT32(5) + +/* field: RXCH4STAT - Interrupt status for RX Channel 4 masked by the C0RXEN register */ +#define TMS570_EMACC_C0RXSTAT_RXCH4STAT BSP_BIT32(4) + +/* field: RXCH3STAT - Interrupt status for RX Channel 3 masked by the C0RXEN register */ +#define TMS570_EMACC_C0RXSTAT_RXCH3STAT BSP_BIT32(3) + +/* field: RXCH2STAT - H2STAT Interrupt status for RX Channel 2 masked by the C0RXEN register */ +#define TMS570_EMACC_C0RXSTAT_RXCH2STAT BSP_BIT32(2) + +/* field: RXCH1STAT - Interrupt status for RX Channel 1 masked by the C0RXEN register */ +#define TMS570_EMACC_C0RXSTAT_RXCH1STAT BSP_BIT32(1) + +/* field: RXCH0STAT - Interrupt status for RX Channel 0 masked by the C0RXEN register */ +#define TMS570_EMACC_C0RXSTAT_RXCH0STAT BSP_BIT32(0) + + +/*-------------------TMS570_EMACC_C0TXSTAT-------------------*/ +/* field: TXCH7STAT - Interrupt status for TX Channel 7 masked by the C0TXEN register */ +#define TMS570_EMACC_C0TXSTAT_TXCH7STAT BSP_BIT32(7) + +/* field: TXCH6STAT - TXCH6STAT */ +#define TMS570_EMACC_C0TXSTAT_TXCH6STAT BSP_BIT32(6) + +/* field: TXCH5STAT - Interrupt status for TX Channel 5 masked by the C0TXEN register */ +#define TMS570_EMACC_C0TXSTAT_TXCH5STAT BSP_BIT32(5) + +/* field: TXCH4STAT - Interrupt status for TX Channel 4 masked by the C0TXEN register */ +#define TMS570_EMACC_C0TXSTAT_TXCH4STAT BSP_BIT32(4) + +/* field: TXCH3STAT - Interrupt status for TX Channel 3 masked by the C0TXEN register */ +#define TMS570_EMACC_C0TXSTAT_TXCH3STAT BSP_BIT32(3) + +/* field: TXCH2STAT - Interrupt status for TX Channel 2 masked by the C0TXEN register */ +#define TMS570_EMACC_C0TXSTAT_TXCH2STAT BSP_BIT32(2) + +/* field: TXCH1STAT - Interrupt status for TX Channel 1 masked by the C0TXEN register */ +#define TMS570_EMACC_C0TXSTAT_TXCH1STAT BSP_BIT32(1) + +/* field: TXCH0STAT - Interrupt status for TX Channel 0 masked by the C0TXEN register */ +#define TMS570_EMACC_C0TXSTAT_TXCH0STAT BSP_BIT32(0) + + +/*------------------TMS570_EMACC_C0MISCSTAT------------------*/ +/* field: STATPENDSTAT - Interrupt status for EMAC STATPEND masked by the C0MISCEN register */ +#define TMS570_EMACC_C0MISCSTAT_STATPENDSTAT BSP_BIT32(3) + +/* field: HOSTPENDSTAT - Interrupt status for EMAC HOSTPEND masked by the C0MISCEN register */ +#define TMS570_EMACC_C0MISCSTAT_HOSTPENDSTAT BSP_BIT32(2) + +/* field: LINKINT0STAT - Interrupt status for MDIO LINKINT0 masked by the C0MISCEN register */ +#define TMS570_EMACC_C0MISCSTAT_LINKINT0STAT BSP_BIT32(1) + +/* field: USERINT0STAT - Interrupt status for MDIO USERINT0 masked by the C0MISCEN register */ +#define TMS570_EMACC_C0MISCSTAT_USERINT0STAT BSP_BIT32(0) + + +/*-------------------TMS570_EMACC_C0RXIMAX-------------------*/ +/* field: RXIMAX - RXIMAX is the desired number of C0RXPULSE interrupts generated per millisecond when */ +#define TMS570_EMACC_C0RXIMAX_RXIMAX(val) BSP_FLD32(val,0, 5) +#define TMS570_EMACC_C0RXIMAX_RXIMAX_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_EMACC_C0RXIMAX_RXIMAX_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + +/*-------------------TMS570_EMACC_C0TXIMAX-------------------*/ +/* field: TXIMAX - TXIMAX is the desired number of C0TXPULSE interrupts generated per millisecond when */ +#define TMS570_EMACC_C0TXIMAX_TXIMAX(val) BSP_FLD32(val,0, 5) +#define TMS570_EMACC_C0TXIMAX_TXIMAX_GET(reg) BSP_FLD32GET(reg,0, 5) +#define TMS570_EMACC_C0TXIMAX_TXIMAX_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) + + + +#endif /* LIBBSP_ARM_TMS570_EMACC */ diff --git a/c/src/lib/libbsp/arm/tms570/include/tms570.h b/c/src/lib/libbsp/arm/tms570/include/tms570.h index 3280950bc3..439387e401 100644 --- a/c/src/lib/libbsp/arm/tms570/include/tms570.h +++ b/c/src/lib/libbsp/arm/tms570/include/tms570.h @@ -46,7 +46,7 @@ #include #include #include -#include +#include #include #include #include @@ -87,7 +87,7 @@ #define TMS570_DMA (*(volatile tms570_dma_t*)0xFFFFF000) #define TMS570_DMM (*(volatile tms570_dmm_t*)0xFFFFF700) #define TMS570_EFUSE (*(volatile tms570_efuse_t*)0XFFF8C01C) -#define TMS570_EMAC (*(volatile tms570_emac_t*)0xFCF78900) +#define TMS570_EMACC (*(volatile tms570_emacc_t*)0xFCF78800) #define TMS570_EMACM (*(volatile tms570_emacm_t*)0xFCF78000) #define TMS570_EMIF (*(volatile tms570_emif_t*)0xFCFFE800) #define TMS570_ESM (*(volatile tms570_esm_t*)0XFFFFF500) diff --git a/c/src/lib/libbsp/arm/tms570/preinstall.am b/c/src/lib/libbsp/arm/tms570/preinstall.am index 54d90a03ef..c6408cbf6c 100644 --- a/c/src/lib/libbsp/arm/tms570/preinstall.am +++ b/c/src/lib/libbsp/arm/tms570/preinstall.am @@ -146,9 +146,9 @@ $(PROJECT_INCLUDE)/bsp/ti_herc/reg_efuse.h: include/ti_herc/reg_efuse.h $(PROJEC $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/ti_herc/reg_efuse.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/ti_herc/reg_efuse.h -$(PROJECT_INCLUDE)/bsp/ti_herc/reg_emac.h: include/ti_herc/reg_emac.h $(PROJECT_INCLUDE)/bsp/ti_herc/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/ti_herc/reg_emac.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/ti_herc/reg_emac.h +$(PROJECT_INCLUDE)/bsp/ti_herc/reg_emacc.h: include/ti_herc/reg_emacc.h $(PROJECT_INCLUDE)/bsp/ti_herc/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/ti_herc/reg_emacc.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/ti_herc/reg_emacc.h $(PROJECT_INCLUDE)/bsp/ti_herc/reg_emacm.h: include/ti_herc/reg_emacm.h $(PROJECT_INCLUDE)/bsp/ti_herc/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/ti_herc/reg_emacm.h -- cgit v1.2.3