From 8cfdb56662b61ac41afd154041b18516d63986be Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Wed, 7 Aug 2002 15:40:31 +0000 Subject: 2002-08-07 Ivan Guzvinec * include/bsp.h, start/start.S, startup/linkcmds: Patches which were required to make the BSP run. --- c/src/lib/libbsp/or32/orp/ChangeLog | 5 +++ c/src/lib/libbsp/or32/orp/include/bsp.h | 4 +-- c/src/lib/libbsp/or32/orp/start/start.S | 46 +++++++++++++++++++--------- c/src/lib/libbsp/or32/orp/startup/linkcmds | 49 ++++++++++++++++++------------ 4 files changed, 67 insertions(+), 37 deletions(-) (limited to 'c/src/lib/libbsp') diff --git a/c/src/lib/libbsp/or32/orp/ChangeLog b/c/src/lib/libbsp/or32/orp/ChangeLog index 2a9f781460..7d4037ac83 100644 --- a/c/src/lib/libbsp/or32/orp/ChangeLog +++ b/c/src/lib/libbsp/or32/orp/ChangeLog @@ -1,3 +1,8 @@ +2002-08-07 Ivan Guzvinec + + * include/bsp.h, start/start.S, startup/linkcmds: Patches which + were required to make the BSP run. + 2002-08-06 Joel Sherrill * configure.ac: GO back to name bender for the or32/or1200 BSP. diff --git a/c/src/lib/libbsp/or32/orp/include/bsp.h b/c/src/lib/libbsp/or32/orp/include/bsp.h index 3f8150e42e..66d5582f74 100644 --- a/c/src/lib/libbsp/or32/orp/include/bsp.h +++ b/c/src/lib/libbsp/or32/orp/include/bsp.h @@ -70,8 +70,8 @@ extern "C" { /* Constants */ -#define RAM_START 0 -#define RAM_END 0x100000 +#define RAM_START 0x10000000 +#define RAM_END 0x10800000 /* miscellaneous stuff assumed to exist */ diff --git a/c/src/lib/libbsp/or32/orp/start/start.S b/c/src/lib/libbsp/or32/orp/start/start.S index 45cd0d6769..41ed3d4283 100644 --- a/c/src/lib/libbsp/or32/orp/start/start.S +++ b/c/src/lib/libbsp/or32/orp/start/start.S @@ -56,17 +56,18 @@ SYM (Or1k_Interrupt_Vectors): .word 0x00000000 # Breakpoint .word 0x00000000 # Trap +/* PUBLIC(BOTTOM_OF_MEMORY) SYM (BOTTOM_OF_MEMORY): - .word 0x00000000 # Assume RAM @ 0 for the sim + .word 0x10000000 # Assume RAM @ 0 for the sim PUBLIC(TOP_OF_MEMORY) SYM (TOP_OF_MEMORY): - .word 0x800000 # Assume RAM @ 0 for the sim - + .word 0x10800000 # Assume RAM @ 0 for the sim +*/ PUBLIC(_mem_end) SYM (_mem_end): - .word 0x00000000 + .word 0x10800000 BEGIN_CODE .org 0x0 @@ -208,7 +209,20 @@ L2_2: .val . .scl -1 .endef - + +/****************************************************************************/ +/* These constants must be in .text section in order to be */ +/* properly addressed in code. */ + + PUBLIC(BOTTOM_OF_MEMORY) +SYM (BOTTOM_OF_MEMORY): + .word 0x10000000 # Assume RAM @ 0 for the sim + + PUBLIC(TOP_OF_MEMORY) +SYM (TOP_OF_MEMORY): + .word 0x10800000 # Assume RAM @ 0 for the sim + +/****************************************************************************/ /** Currently, about 57 of the 64 valid address locations are being used here. If you add code to the above @@ -706,37 +720,39 @@ _start: that the cache gives us sufficient performance that this is not necessary. It will be very easy to add this later. */ - l.movhi r4,hi(_data_start) - l.ori r4,r4,lo(_data_start) + l.movhi r4,hi(_etext) + l.ori r4,r4,lo(_etext) l.movhi r5,hi(_BOTTOM_OF_MEMORY) l.ori r5,r5,lo(_BOTTOM_OF_MEMORY) l.lwz r5,0(r5) # Dereference it - l.add r5,r5,r4 # Place it in memory above the text segment +/* l.add r5,r5,r4 # Place it in memory above the text segment*/ l.movhi r3,hi(_edata) l.ori r3,r3,lo(_edata) + l.movhi r5,hi(_data_start) + l.ori r5,r5,lo(_data_start) L3_0: l.lwz r6,0(r4) l.addi r5,r5,4 l.addi r4,r4,4 - l.sfeq r3,r4 + l.sfeq r3,r5 l.bnf L3_0 l.sw -4(r5),r6 # Minimize write after read stalls /* Initialize the BSS segment */ - l.movhi r3,hi(_bss_start) - l.ori r3,r3,lo(_bss_start) - l.sub r3,r3,r4 - l.add r3,r3,r5 + l.movhi r3,hi(__end) + l.ori r3,r3,lo(__end) +/* l.sub r3,r3,r4 + l.add r3,r3,r5*/ l.sfleu r3,r5 l.bf L3_2 # Check for no BSS segment! l.nop L3_1: - l.sw 0(r5),r0 + l.addi r5,r5,4 l.sfeq r5,r3 l.bnf L3_1 - l.addi r5,r5,4 + l.sw -4(r5),r0 L3_2: /* Tell everyone where the heap begins */ diff --git a/c/src/lib/libbsp/or32/orp/startup/linkcmds b/c/src/lib/libbsp/or32/orp/startup/linkcmds index 72eb039092..aa91d0ca28 100644 --- a/c/src/lib/libbsp/or32/orp/startup/linkcmds +++ b/c/src/lib/libbsp/or32/orp/startup/linkcmds @@ -14,21 +14,22 @@ MEMORY { - ram : org = 0x0, l = 1M + flash : org = 0x00000000, l = 2M + ram : org = 0x10000000, l = 32M } SECTIONS { - .text 0x0 : - { + .text : AT (0x0) { text_start = . ; _text_start = . ; - *(.text) + + *(.text) . = ALIGN (16); - + *(.eh_fram) . = ALIGN (16); - + /* * C++ constructors */ @@ -43,21 +44,29 @@ SECTIONS LONG(0) __DTOR_END__ = .; _etext = ALIGN( 0x10 ) ; - } - .data ADDR( .text ) + SIZEOF( .text ): - { + . = ALIGN( 0x10) ; + } > flash + + .data : AT ( ADDR(.text) + SIZEOF(.text) ) { data_start = . ; _data_start = . ; - *(.data) - _edata = ALIGN( 0x10 ) ; - } - .bss ADDR( .data ) + SIZEOF( .data ): - { - bss_start = . ; - _bss_start = . ; + + *(.data) + + _edata = ALIGN( 0x10 ); + . = ALIGN (0x10); + } > ram + + .bss : AT ( ADDR(.text) + SIZEOF(.text) + SIZEOF(.data) ) { + bss_start = .; + _bss_start = .; + *(.bss) *(COMMON) - end = . ; - __end = . ; - } -} + + end = ALIGN( 0x10 ); + __end = ALIGN( 0x10 ); + . = ALIGN (0x10); + } > ram + +} \ No newline at end of file -- cgit v1.2.3