From 01629105c2817a59a4f1f05039593f211cf5ddaa Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Mon, 14 Dec 1998 23:15:38 +0000 Subject: Patch from Ralf Corsepius to rename all .s files to .S in conformance with GNU conventions. This is a minor step along the way to supporting automake. --- c/src/lib/libbsp/a29k/portsw/console/Makefile.in | 6 +- c/src/lib/libbsp/a29k/portsw/shmsupp/Makefile.in | 6 +- c/src/lib/libbsp/a29k/portsw/start/Makefile.in | 6 +- c/src/lib/libbsp/a29k/portsw/start/crt0.S | 288 +++++++ c/src/lib/libbsp/a29k/portsw/start/register.S | 393 +++++++++ c/src/lib/libbsp/a29k/portsw/startup/Makefile.in | 6 +- c/src/lib/libbsp/hppa1.1/simhppa/start/Makefile.in | 6 +- c/src/lib/libbsp/hppa1.1/simhppa/start/start.S | 169 ++++ c/src/lib/libbsp/hppa1.1/simhppa/start/start.s | 169 ---- .../lib/libbsp/hppa1.1/simhppa/wrapup/Makefile.in | 15 +- c/src/lib/libbsp/i386/force386/start/Makefile.in | 6 +- c/src/lib/libbsp/i386/force386/start/start.S | 267 +++++++ c/src/lib/libbsp/i386/force386/start/start.s | 267 ------- c/src/lib/libbsp/i386/force386/startup/Makefile.in | 6 +- c/src/lib/libbsp/i386/force386/startup/ldsegs.S | 86 ++ c/src/lib/libbsp/i386/force386/startup/ldsegs.s | 86 -- c/src/lib/libbsp/i386/force386/timer/Makefile.in | 6 +- c/src/lib/libbsp/i386/force386/timer/timerisr.S | 34 + c/src/lib/libbsp/i386/force386/timer/timerisr.s | 34 - c/src/lib/libbsp/i386/force386/wrapup/Makefile.in | 15 +- c/src/lib/libbsp/i386/go32/timer/Makefile.in | 6 +- c/src/lib/libbsp/i386/go32/timer/timerisr.S | 41 + c/src/lib/libbsp/i386/go32/timer/timerisr.s | 41 - c/src/lib/libbsp/i386/i386ex/clock/Makefile.in | 6 +- c/src/lib/libbsp/i386/i386ex/console/Makefile.in | 6 +- c/src/lib/libbsp/i386/i386ex/start/Makefile.in | 6 +- c/src/lib/libbsp/i386/i386ex/start/start.S | 437 +++++++++++ c/src/lib/libbsp/i386/i386ex/start/start.s | 437 ----------- c/src/lib/libbsp/i386/i386ex/startup/Makefile.in | 6 +- c/src/lib/libbsp/i386/i386ex/timer/Makefile.in | 6 +- c/src/lib/libbsp/i386/i386ex/timer/timerisr.S | 40 + c/src/lib/libbsp/i386/i386ex/timer/timerisr.s | 40 - c/src/lib/libbsp/i386/pc386/console/Makefile.in | 6 +- c/src/lib/libbsp/i386/pc386/console/videoAsm.S | 51 ++ c/src/lib/libbsp/i386/pc386/console/videoAsm.s | 51 -- c/src/lib/libbsp/i386/pc386/start/start.S | 202 +++++ c/src/lib/libbsp/i386/pc386/start/start.s | 202 ----- c/src/lib/libbsp/i386/pc386/start/start16.S | 183 +++++ c/src/lib/libbsp/i386/pc386/start/start16.s | 183 ----- c/src/lib/libbsp/i386/pc386/startup/Makefile.in | 6 +- c/src/lib/libbsp/i386/pc386/startup/ldsegs.S | 222 ++++++ c/src/lib/libbsp/i386/pc386/startup/ldsegs.s | 222 ------ c/src/lib/libbsp/i386/pc386/timer/Makefile.in | 6 +- c/src/lib/libbsp/i386/pc386/timer/timerisr.S | 61 ++ c/src/lib/libbsp/i386/pc386/timer/timerisr.s | 61 -- c/src/lib/libbsp/i386/shared/irq/irq_asm.S | 250 ++++++ c/src/lib/libbsp/i386/shared/irq/irq_asm.s | 250 ------ c/src/lib/libbsp/i960/cvme961/start/Makefile.in | 6 +- c/src/lib/libbsp/i960/cvme961/start/start.S | 110 +++ c/src/lib/libbsp/i960/cvme961/timer/Makefile.in | 6 +- c/src/lib/libbsp/i960/cvme961/timer/timerisr.S | 65 ++ c/src/lib/libbsp/i960/cvme961/timer/timerisr.s | 65 -- c/src/lib/libbsp/i960/cvme961/wrapup/Makefile.in | 15 +- c/src/lib/libbsp/m68k/dmv152/timer/Makefile.in | 6 +- c/src/lib/libbsp/m68k/dmv152/timer/timerisr.S | 38 + c/src/lib/libbsp/m68k/dmv152/timer/timerisr.s | 38 - c/src/lib/libbsp/m68k/gen68302/start/Makefile.in | 6 +- c/src/lib/libbsp/m68k/gen68302/start/start.S | 267 +++++++ c/src/lib/libbsp/m68k/gen68302/start/start302.s | 267 ------- .../lib/libbsp/m68k/gen68302/start302/Makefile.in | 6 +- c/src/lib/libbsp/m68k/gen68302/start302/start302.S | 267 +++++++ c/src/lib/libbsp/m68k/gen68302/start302/start302.s | 267 ------- c/src/lib/libbsp/m68k/gen68302/timer/Makefile.in | 6 +- c/src/lib/libbsp/m68k/gen68302/timer/timerisr.S | 28 + c/src/lib/libbsp/m68k/gen68302/timer/timerisr.s | 28 - c/src/lib/libbsp/m68k/gen68340/console/Makefile.in | 6 +- .../libbsp/m68k/gen68340/console/Modif_cpu_asm.S | 184 +++++ .../libbsp/m68k/gen68340/console/Modif_cpu_asm.s | 184 ----- c/src/lib/libbsp/m68k/gen68340/start/Makefile.in | 6 +- c/src/lib/libbsp/m68k/gen68340/start/start.S | 874 +++++++++++++++++++++ c/src/lib/libbsp/m68k/gen68340/start/start340.s | 874 --------------------- .../libbsp/m68k/gen68340/start/startfor340only.S | 499 ++++++++++++ .../libbsp/m68k/gen68340/start/startfor340only.s | 499 ------------ .../lib/libbsp/m68k/gen68340/start340/Makefile.in | 6 +- c/src/lib/libbsp/m68k/gen68340/start340/start340.S | 874 +++++++++++++++++++++ c/src/lib/libbsp/m68k/gen68340/start340/start340.s | 874 --------------------- .../m68k/gen68340/start340/startfor340only.S | 499 ++++++++++++ .../m68k/gen68340/start340/startfor340only.s | 499 ------------ c/src/lib/libbsp/m68k/gen68360/start/Makefile.in | 6 +- c/src/lib/libbsp/m68k/gen68360/start/start.S | 432 ++++++++++ c/src/lib/libbsp/m68k/gen68360/start/start360.s | 432 ---------- .../lib/libbsp/m68k/gen68360/start360/Makefile.in | 6 +- c/src/lib/libbsp/m68k/gen68360/start360/start360.S | 432 ++++++++++ c/src/lib/libbsp/m68k/gen68360/start360/start360.s | 432 ---------- c/src/lib/libbsp/m68k/idp/timer/Makefile.in | 6 +- c/src/lib/libbsp/m68k/idp/timer/timerisr.S | 38 + c/src/lib/libbsp/m68k/idp/timer/timerisr.s | 38 - c/src/lib/libbsp/m68k/mvme136/timer/Makefile.in | 6 +- c/src/lib/libbsp/m68k/mvme136/timer/timerisr.S | 39 + c/src/lib/libbsp/m68k/mvme136/timer/timerisr.s | 39 - c/src/lib/libbsp/m68k/mvme136/wrapup/Makefile.in | 15 +- c/src/lib/libbsp/m68k/mvme147/timer/Makefile.in | 6 +- c/src/lib/libbsp/m68k/mvme147/timer/timerisr.s | 28 - c/src/lib/libbsp/m68k/mvme147/wrapup/Makefile.in | 4 +- c/src/lib/libbsp/m68k/mvme147s/timer/Makefile.in | 6 +- c/src/lib/libbsp/m68k/mvme147s/wrapup/Makefile.in | 15 +- c/src/lib/libbsp/m68k/mvme162/timer/Makefile.in | 6 +- c/src/lib/libbsp/m68k/mvme162/timer/timerisr.S | 47 ++ c/src/lib/libbsp/m68k/mvme162/timer/timerisr.s | 47 -- c/src/lib/libbsp/m68k/ods68302/start/Makefile.in | 6 +- .../lib/libbsp/m68k/ods68302/start302/Makefile.in | 6 +- c/src/lib/libbsp/m68k/ods68302/timer/Makefile.in | 6 +- c/src/lib/libbsp/m68k/ods68302/timer/timerisr.S | 28 + c/src/lib/libbsp/m68k/ods68302/timer/timerisr.s | 28 - c/src/lib/libbsp/m68k/shared/start.S | 153 ++++ .../lib/libbsp/mips64orion/p4000/start/Makefile.in | 4 +- c/src/lib/libbsp/no_cpu/no_bsp/clock/Makefile.in | 6 +- c/src/lib/libbsp/no_cpu/no_bsp/console/Makefile.in | 6 +- c/src/lib/libbsp/no_cpu/no_bsp/shmsupp/Makefile.in | 6 +- c/src/lib/libbsp/no_cpu/no_bsp/startup/Makefile.in | 6 +- c/src/lib/libbsp/no_cpu/no_bsp/timer/Makefile.in | 6 +- c/src/lib/libbsp/no_cpu/no_bsp/wrapup/Makefile.in | 15 +- c/src/lib/libbsp/powerpc/dmv177/clock/Makefile.in | 6 +- c/src/lib/libbsp/powerpc/dmv177/sonic/Makefile.in | 6 +- c/src/lib/libbsp/powerpc/dmv177/start/Makefile.in | 6 +- c/src/lib/libbsp/powerpc/dmv177/start/start.S | 117 +++ c/src/lib/libbsp/powerpc/dmv177/start/start.s | 117 --- .../lib/libbsp/powerpc/dmv177/startup/Makefile.in | 6 +- c/src/lib/libbsp/powerpc/dmv177/timer/Makefile.in | 6 +- .../libbsp/powerpc/helas403/dlentry/Makefile.in | 6 +- .../lib/libbsp/powerpc/helas403/dlentry/dlentry.S | 144 ++++ .../lib/libbsp/powerpc/helas403/dlentry/dlentry.s | 144 ---- .../libbsp/powerpc/helas403/flashentry/Makefile.in | 6 +- .../powerpc/helas403/flashentry/flashentry.S | 469 +++++++++++ .../powerpc/helas403/flashentry/flashentry.s | 469 ----------- .../lib/libbsp/powerpc/papyrus/dlentry/Makefile.in | 6 +- c/src/lib/libbsp/powerpc/papyrus/dlentry/dlentry.S | 251 ++++++ c/src/lib/libbsp/powerpc/papyrus/dlentry/dlentry.s | 251 ------ .../libbsp/powerpc/papyrus/flashentry/Makefile.in | 6 +- .../libbsp/powerpc/papyrus/flashentry/flashentry.S | 289 +++++++ .../libbsp/powerpc/papyrus/flashentry/flashentry.s | 289 ------- c/src/lib/libbsp/powerpc/psim/clock/Makefile.in | 6 +- c/src/lib/libbsp/powerpc/psim/console/Makefile.in | 6 +- c/src/lib/libbsp/powerpc/psim/console/consupp.S | 33 + c/src/lib/libbsp/powerpc/psim/console/consupp.s | 33 - c/src/lib/libbsp/powerpc/psim/start/Makefile.in | 6 +- c/src/lib/libbsp/powerpc/psim/start/start.S | 106 +++ c/src/lib/libbsp/powerpc/psim/start/startsim.s | 106 --- c/src/lib/libbsp/powerpc/psim/startsim/Makefile.in | 6 +- c/src/lib/libbsp/powerpc/psim/startsim/startsim.S | 106 +++ c/src/lib/libbsp/powerpc/psim/startsim/startsim.s | 106 --- c/src/lib/libbsp/powerpc/psim/startup/Makefile.in | 6 +- c/src/lib/libbsp/powerpc/psim/timer/Makefile.in | 6 +- c/src/lib/libbsp/powerpc/psim/vectors/Makefile.in | 6 +- c/src/lib/libbsp/powerpc/psim/vectors/align_h.S | 434 ++++++++++ c/src/lib/libbsp/powerpc/psim/vectors/align_h.s | 434 ---------- c/src/lib/libbsp/powerpc/psim/vectors/vectors.S | 123 +++ c/src/lib/libbsp/powerpc/psim/vectors/vectors.s | 123 --- c/src/lib/libbsp/powerpc/psim/wrapup/Makefile.in | 6 +- c/src/lib/libbsp/sh/gensh1/scitab/Makefile.in | 6 +- c/src/lib/libbsp/sh/gensh1/start/Makefile.in | 6 +- c/src/lib/libbsp/sh/gensh1/start/start.S | 94 +++ c/src/lib/libbsp/sh/gensh1/startup/Makefile.in | 6 +- c/src/lib/libbsp/sparc/erc32/clock/Makefile.in | 6 +- c/src/lib/libbsp/sparc/erc32/console/Makefile.in | 6 +- c/src/lib/libbsp/sparc/erc32/start/Makefile.in | 6 +- c/src/lib/libbsp/sparc/erc32/start/start.S | 309 ++++++++ c/src/lib/libbsp/sparc/erc32/start/startsis.s | 309 -------- c/src/lib/libbsp/sparc/erc32/startsis/Makefile.in | 6 +- c/src/lib/libbsp/sparc/erc32/startsis/startsis.S | 309 ++++++++ c/src/lib/libbsp/sparc/erc32/startsis/startsis.s | 309 -------- c/src/lib/libbsp/sparc/erc32/timer/Makefile.in | 6 +- c/src/lib/libbsp/unix/posix/wrapup/Makefile.in | 26 +- 163 files changed, 10654 insertions(+), 9620 deletions(-) create mode 100644 c/src/lib/libbsp/a29k/portsw/start/crt0.S create mode 100644 c/src/lib/libbsp/a29k/portsw/start/register.S create mode 100644 c/src/lib/libbsp/hppa1.1/simhppa/start/start.S delete mode 100644 c/src/lib/libbsp/hppa1.1/simhppa/start/start.s create mode 100644 c/src/lib/libbsp/i386/force386/start/start.S delete mode 100644 c/src/lib/libbsp/i386/force386/start/start.s create mode 100644 c/src/lib/libbsp/i386/force386/startup/ldsegs.S delete mode 100644 c/src/lib/libbsp/i386/force386/startup/ldsegs.s create mode 100644 c/src/lib/libbsp/i386/force386/timer/timerisr.S delete mode 100644 c/src/lib/libbsp/i386/force386/timer/timerisr.s create mode 100644 c/src/lib/libbsp/i386/go32/timer/timerisr.S delete mode 100644 c/src/lib/libbsp/i386/go32/timer/timerisr.s create mode 100644 c/src/lib/libbsp/i386/i386ex/start/start.S delete mode 100644 c/src/lib/libbsp/i386/i386ex/start/start.s create mode 100644 c/src/lib/libbsp/i386/i386ex/timer/timerisr.S delete mode 100644 c/src/lib/libbsp/i386/i386ex/timer/timerisr.s create mode 100644 c/src/lib/libbsp/i386/pc386/console/videoAsm.S delete mode 100644 c/src/lib/libbsp/i386/pc386/console/videoAsm.s create mode 100644 c/src/lib/libbsp/i386/pc386/start/start.S delete mode 100644 c/src/lib/libbsp/i386/pc386/start/start.s create mode 100644 c/src/lib/libbsp/i386/pc386/start/start16.S delete mode 100644 c/src/lib/libbsp/i386/pc386/start/start16.s create mode 100644 c/src/lib/libbsp/i386/pc386/startup/ldsegs.S delete mode 100644 c/src/lib/libbsp/i386/pc386/startup/ldsegs.s create mode 100644 c/src/lib/libbsp/i386/pc386/timer/timerisr.S delete mode 100644 c/src/lib/libbsp/i386/pc386/timer/timerisr.s create mode 100644 c/src/lib/libbsp/i386/shared/irq/irq_asm.S delete mode 100644 c/src/lib/libbsp/i386/shared/irq/irq_asm.s create mode 100644 c/src/lib/libbsp/i960/cvme961/start/start.S create mode 100644 c/src/lib/libbsp/i960/cvme961/timer/timerisr.S delete mode 100644 c/src/lib/libbsp/i960/cvme961/timer/timerisr.s create mode 100644 c/src/lib/libbsp/m68k/dmv152/timer/timerisr.S delete mode 100644 c/src/lib/libbsp/m68k/dmv152/timer/timerisr.s create mode 100644 c/src/lib/libbsp/m68k/gen68302/start/start.S delete mode 100644 c/src/lib/libbsp/m68k/gen68302/start/start302.s create mode 100644 c/src/lib/libbsp/m68k/gen68302/start302/start302.S delete mode 100644 c/src/lib/libbsp/m68k/gen68302/start302/start302.s create mode 100644 c/src/lib/libbsp/m68k/gen68302/timer/timerisr.S delete mode 100644 c/src/lib/libbsp/m68k/gen68302/timer/timerisr.s create mode 100644 c/src/lib/libbsp/m68k/gen68340/console/Modif_cpu_asm.S delete mode 100644 c/src/lib/libbsp/m68k/gen68340/console/Modif_cpu_asm.s create mode 100644 c/src/lib/libbsp/m68k/gen68340/start/start.S delete mode 100644 c/src/lib/libbsp/m68k/gen68340/start/start340.s create mode 100644 c/src/lib/libbsp/m68k/gen68340/start/startfor340only.S delete mode 100644 c/src/lib/libbsp/m68k/gen68340/start/startfor340only.s create mode 100644 c/src/lib/libbsp/m68k/gen68340/start340/start340.S delete mode 100644 c/src/lib/libbsp/m68k/gen68340/start340/start340.s create mode 100644 c/src/lib/libbsp/m68k/gen68340/start340/startfor340only.S delete mode 100644 c/src/lib/libbsp/m68k/gen68340/start340/startfor340only.s create mode 100644 c/src/lib/libbsp/m68k/gen68360/start/start.S delete mode 100644 c/src/lib/libbsp/m68k/gen68360/start/start360.s create mode 100644 c/src/lib/libbsp/m68k/gen68360/start360/start360.S delete mode 100644 c/src/lib/libbsp/m68k/gen68360/start360/start360.s create mode 100644 c/src/lib/libbsp/m68k/idp/timer/timerisr.S delete mode 100644 c/src/lib/libbsp/m68k/idp/timer/timerisr.s create mode 100644 c/src/lib/libbsp/m68k/mvme136/timer/timerisr.S delete mode 100644 c/src/lib/libbsp/m68k/mvme136/timer/timerisr.s delete mode 100644 c/src/lib/libbsp/m68k/mvme147/timer/timerisr.s create mode 100644 c/src/lib/libbsp/m68k/mvme162/timer/timerisr.S delete mode 100644 c/src/lib/libbsp/m68k/mvme162/timer/timerisr.s create mode 100644 c/src/lib/libbsp/m68k/ods68302/timer/timerisr.S delete mode 100644 c/src/lib/libbsp/m68k/ods68302/timer/timerisr.s create mode 100644 c/src/lib/libbsp/m68k/shared/start.S create mode 100644 c/src/lib/libbsp/powerpc/dmv177/start/start.S delete mode 100644 c/src/lib/libbsp/powerpc/dmv177/start/start.s create mode 100644 c/src/lib/libbsp/powerpc/helas403/dlentry/dlentry.S delete mode 100644 c/src/lib/libbsp/powerpc/helas403/dlentry/dlentry.s create mode 100644 c/src/lib/libbsp/powerpc/helas403/flashentry/flashentry.S delete mode 100644 c/src/lib/libbsp/powerpc/helas403/flashentry/flashentry.s create mode 100644 c/src/lib/libbsp/powerpc/papyrus/dlentry/dlentry.S delete mode 100644 c/src/lib/libbsp/powerpc/papyrus/dlentry/dlentry.s create mode 100644 c/src/lib/libbsp/powerpc/papyrus/flashentry/flashentry.S delete mode 100644 c/src/lib/libbsp/powerpc/papyrus/flashentry/flashentry.s create mode 100644 c/src/lib/libbsp/powerpc/psim/console/consupp.S delete mode 100644 c/src/lib/libbsp/powerpc/psim/console/consupp.s create mode 100644 c/src/lib/libbsp/powerpc/psim/start/start.S delete mode 100644 c/src/lib/libbsp/powerpc/psim/start/startsim.s create mode 100644 c/src/lib/libbsp/powerpc/psim/startsim/startsim.S delete mode 100644 c/src/lib/libbsp/powerpc/psim/startsim/startsim.s create mode 100644 c/src/lib/libbsp/powerpc/psim/vectors/align_h.S delete mode 100644 c/src/lib/libbsp/powerpc/psim/vectors/align_h.s create mode 100644 c/src/lib/libbsp/powerpc/psim/vectors/vectors.S delete mode 100644 c/src/lib/libbsp/powerpc/psim/vectors/vectors.s create mode 100644 c/src/lib/libbsp/sh/gensh1/start/start.S create mode 100644 c/src/lib/libbsp/sparc/erc32/start/start.S delete mode 100644 c/src/lib/libbsp/sparc/erc32/start/startsis.s create mode 100644 c/src/lib/libbsp/sparc/erc32/startsis/startsis.S delete mode 100644 c/src/lib/libbsp/sparc/erc32/startsis/startsis.s (limited to 'c/src/lib/libbsp') diff --git a/c/src/lib/libbsp/a29k/portsw/console/Makefile.in b/c/src/lib/libbsp/a29k/portsw/console/Makefile.in index a7cdd9f374..d0d81e6d80 100644 --- a/c/src/lib/libbsp/a29k/portsw/console/Makefile.in +++ b/c/src/lib/libbsp/a29k/portsw/console/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES=$(srcdir)/concntl.h -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES= -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/a29k/portsw/shmsupp/Makefile.in b/c/src/lib/libbsp/a29k/portsw/shmsupp/Makefile.in index b4967b93cb..746f00b638 100644 --- a/c/src/lib/libbsp/a29k/portsw/shmsupp/Makefile.in +++ b/c/src/lib/libbsp/a29k/portsw/shmsupp/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES= -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/a29k/portsw/start/Makefile.in b/c/src/lib/libbsp/a29k/portsw/start/Makefile.in index f89c5a7e6f..823953baa0 100644 --- a/c/src/lib/libbsp/a29k/portsw/start/Makefile.in +++ b/c/src/lib/libbsp/a29k/portsw/start/Makefile.in @@ -15,10 +15,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=crt0 register -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/a29k/portsw/start/crt0.S b/c/src/lib/libbsp/a29k/portsw/start/crt0.S new file mode 100644 index 0000000000..017f2d4cca --- /dev/null +++ b/c/src/lib/libbsp/a29k/portsw/start/crt0.S @@ -0,0 +1,288 @@ +; @(#)crt0.s 1.3 96/05/31 14:40:27, AMD +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright 1988, 1989, 1990 Advanced Micro Devices, Inc. +; +; This software is the property of Advanced Micro Devices, Inc (AMD) which +; specifically grants the user the right to modify, use and distribute this +; software provided this notice is not removed or altered. All other rights +; are reserved by AMD. +; +; AMD MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS +; SOFTWARE. IN NO EVENT SHALL AMD BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL +; DAMAGES IN CONNECTION WITH OR ARISING FROM THE FURNISHING, PERFORMANCE, OR +; USE OF THIS SOFTWARE. +; +; So that all may benefit from your experience, please report any problems +; or suggestions about this software to the 29K Technical Support Center at +; 800-29-29-AMD (800-292-9263) in the USA, or 0800-89-1131 in the UK, or +; 0031-11-1129 in Japan, toll free. The direct dial number is 512-462-4118. +; +; Advanced Micro Devices, Inc. +; 29K Support Products +; Mail Stop 573 +; 5900 E. Ben White Blvd. +; Austin, TX 78741 +; 800-292-9263 +; +; /* $Id$ */ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + .file "crt0.s" + +; crt0.s version 3.3-0 +; +; This module gets control from the OS. +; It saves away the Am29027 Mode register settings and +; then sets up the pointers to the resident spill and fill +; trap handlers. It then establishes argv and argc for passing +; to main. It then calls _main. If main returns, it calls _exit. +; +; void = start( ); +; NOTE - not C callable (no lead underscore) +; + .include "sysmac.h" +; +; + .extern V_SPILL, V_FILL +; .comm __29027Mode, 8 ; A shadow of the mode register + .comm __LibInit, 4 + + .text + .extern _main, _exit, _atexit + + .word 0 ; Terminating tag word + .global start +start: + sub gr1, gr1, 6 * 4 + asgeu V_SPILL, gr1, rab ; better not ever happen + add lr1, gr1, 6 * 4 + +; +; Save the initial value of the Am29027's Mode register +; +; If your system does not enter crt0 with value for Am29027's Mode +; register in gr96 and gr97, and also the coprocessor is active +; uncomment the next 4 instructions. +; +; const gr96, 0xfc00820 +; consth gr96, 0xfc00820 +; const gr97, 0x1375 +; store 1, 3, gr96, gr97 +; +; const gr98, __29027Mode +; consth gr98, __29027Mode +; store 0, 0, gr96, gr98 +; add gr98, gr98, 4 +; store 0, 0, gr97, gr98 +; +; Now call the system to setup the spill and fill trap handlers +; + const lr3, spill + consth lr3, spill + const lr2, V_SPILL + syscall setvec + const lr3, fill + consth lr3, fill + const lr2, V_FILL + syscall setvec + +; +; atexit(_fini) +; +; const lr0, _atexit +; consth lr0, _atexit +; const lr2,__fini +; calli lr0,lr0 +; consth lr2,__fini +; +; Now call _init +; +; const lr0, __init +; consth lr0, __init +; calli lr0,lr0 +; nop + +; +; Get the argv base address and calculate argc. +; + syscall getargs + add lr3, v0, 0 ; argv + add lr4, v0, 0 + constn lr2, -1 +argcloop: ; scan for NULL terminator + load 0, 0, gr97, lr4 + add lr4, lr4, 4 + cpeq gr97, gr97, 0 + jmpf gr97, argcloop + add lr2, lr2, 1 +; +; Now call LibInit, if there is one. To aid runtime libraries +; that need to do some startup initialization, we have created +; a bss variable called LibInit. If the library doesn't need +; any run-time initialization, the variable is still 0. If the +; library does need run-time initialization, the library will +; contain a definition like +; void (*_LibInit)(void) = LibInitFunction; +; The linker will match up our bss LibInit with this data LibInit +; and the variable will not be 0. This results in the LibInit routine +; being called via the calli instruction below. +; + const lr0, __LibInit + consth lr0, __LibInit + load 0, 0, lr0, lr0 + cpeq gr96, lr0, 0 + jmpt gr96, NoLibInit + nop + calli lr0, lr0 + nop +NoLibInit: + +; +; Call RAMInit to initialize the data memory. +; +; The following code segment was used to create the two flavors of the +; run-time initialization routines (crt0_1.o, and crt0_2.o) as described +; in the User's Manual. If osboot is used to create a stand-alone +; application, or the call to RAMInit is made in the start-up routine, +; then the following is not needed. +; +; .ifdef ROM_LOAD +; .extern RAMInit +; +; const lr0, RAMInit +; consth lr0, RAMInit +; calli gr96, lr0 +; nop +; .else +; nop +; nop +; nop +; nop +; .endif + +; +; Uncomment the following .comm, if you ARE NOT using osboot as released +; with the High C 29K product, AND plan to use the romcoff utility to +; move code and/or data sections to ROM. +; +; .comm RAMInit, 4 +; +; Furthermore, if the above is uncommented, then use the following logic +; to call the RAMInit function, if needed. +; +; const lr0, RAMInit +; consth lr0, RAMInit +; load 0, 0, gr96, lr0 +; cpeq gr96, gr96, 0 ; nothing there? +; jmpt gr96, endRAMInit ; yes, nothing to init +; nop +; calli gr96, lr0 ; no, then instruction found +; nop ; execute function. +; + + +; +; call main, passing it 2 arguments. main( argc, argv ) +; + const lr0, _main + consth lr0, _main + calli lr0, lr0 + nop +; +; call exit +; + const lr0, _exit + consth lr0, _exit + calli lr0, lr0 + add lr2, gr96, 0 +; +; Should never get here, but just in case +; +loop: + syscall exit + jmp loop + nop + .sbttl "Spill and Fill trap handlers" + .eject +; +; SPILL, FILL trap handlers +; +; Note that these Spill and Fill trap handlers allow the OS to +; assume that the only registers of use are between gr1 and rfb. +; Therefore, if the OS desires to, it may simply preserve from +; lr0 for (rfb-gr1)/4 registers when doing a context save. +; +; +; Here is the spill handler +; +; spill registers from [*gr1..*rab) +; and move rab downto where gr1 points +; +; rab must change before rfb for signals to work +; +; On entry: rfb - rab = windowsize, gr1 < rab +; Near the end: rfb - rab > windowsize, gr1 == rab +; On exit: rfb - rab = windowsize, gr1 == rab +; + .global spill +spill: + sub tav, rab, gr1 ; tav = number of bytes to spill + srl tav, tav, 2 ; change byte count to word count + sub tav, tav, 1 ; make count zero based + mtsr CR, tav ; set Count Remaining register + sub tav, rab, gr1 + sub tav, rfb, tav ; pull down free bound and save it in rab + add rab, gr1, 0 ; first pull down allocate bound + storem 0, 0, lr0, tav ; store lr0..lr(tav) into rfb + jmpi tpc ; return... + add rfb, tav, 0 +; +; Here is the fill handler +; +; fill registers from [*rfb..*lr1) +; and move rfb upto where lr1 points. +; +; rab must change before rfb for signals to work +; +; On entry: rfb - rab = windowsize, lr1 > rfb +; Near the end: rfb - rab < windowsize, lr1 == rab + windowsize +; On exit: rfb - rab = windowsize, lr1 == rfb +; + .global fill +fill: + const tav, 0x80 << 2 + or tav, tav, rfb ; tav = ((rfb>>2) | 0x80)<<2 == [rfb]<<2 + mtsr IPA, tav ; ipa = [rfb]<<2 == 1st reg to fill + ; gr0 is now the first reg to fill + sub tav, lr1, rfb ; tav = number of bytes to fill + add rab, rab, tav ; push up allocate bound + srl tav, tav, 2 ; change byte count to word count + sub tav, tav, 1 ; make count zero based + mtsr CR, tav ; set Count Remaining register + loadm 0, 0, gr0, rfb ; load registers + jmpi tpc ; return... + add rfb, lr1, 0 ; ... first pushing up free bound + +; +; The __init function +; +; .sect .init,text +; .use .init +; .global __init +;__init: +; sub gr1,gr1,16 +; asgeu V_SPILL,gr1,gr126 +; add lr1,gr1,24 +; +; +; The __fini function +; +; .sect .fini,text +; .use .fini +; .global __fini +;__fini: +; sub gr1,gr1,16 +; asgeu V_SPILL,gr1,gr126 +; add lr1,gr1,24 +; + .end diff --git a/c/src/lib/libbsp/a29k/portsw/start/register.S b/c/src/lib/libbsp/a29k/portsw/start/register.S new file mode 100644 index 0000000000..4d17071ed1 --- /dev/null +++ b/c/src/lib/libbsp/a29k/portsw/start/register.S @@ -0,0 +1,393 @@ +; /* @(#)register.s 1.1 96/05/23 08:57:34, TEI */ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Register Definitions and Usage Conventions +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; /* $Id$ */ +; + +;* File information and includes. + + .file "c_register.s" + .ident "@(#)register.s 1.1 96/05/23 08:57:34, TEI\n" + +; Basic guidelines for register distribution and usage are derived from +; the AMD application notes. It would be best to stick with the conventions +; laid out by AMD. +; Application Note: Context Switching with 29000 Processor By Daniel Mann. + +; +;************************************************************************* +; + +; +; Rule 1: +; Gr1 is used as a pointer to the register stack +; Lr1 is used as frame pointer +; + + .reg regsp, gr1 ; Register Stack Pointer + .reg fp, lr1 ; frame pointer + + .equ Rrsp, ®sp + .equ Rfp, &fp + + .global Rrsp, Rfp + +; +;************************************************************************* +; + +; +; Gr2-Gr63 are not implemented in silicon +; + +; +;************************************************************************* +; + +; +; Rule 2: +; The registers GR64-GR95 are dedicated for operating system use. +; + +; The register range GR64-GR95 i.e 32 Registers is furthur sub-divided as +; follows... +; gr64-gr67 interrupt handlers. +; gr68-gr71 OS temporaries I +; gr72-gr79 OS temporaries II +; gr80-gr95 OS statics. Dedicated throughout the operation of a program. + + +; +; 32 Registers for Operating System Use. +; + +; +; Assigning Names to Interrupt Handlers Registers. +; + + .reg OSint0, gr64 + .reg OSint1, gr65 + .reg OSint2, gr66 + .reg OSint3, gr67 + + .equ ROSint0, &OSint0 + .equ ROSint1, &OSint1 + .equ ROSint2, &OSint2 + .equ ROSint3, &OSint3 + + .global ROSint0, ROSint1, ROSint2, ROSint3 + + .reg TrapReg, gr64 ; trap register + .reg trapreg, gr64 ; trapreg + + .equ RTrapReg, &TrapReg + .equ Rtrapreg, &trapreg + + .global RTrapReg, Rtrapreg + + +; +; Assigning Names to Scratch/Temporary Registers. +; + + .reg OStmp0, gr68 + .reg OStmp1, gr69 + .reg OStmp2, gr70 + .reg OStmp3, gr71 + + .reg OStmp4, gr72 + .reg OStmp5, gr73 + .reg OStmp6, gr74 + .reg OStmp7, gr75 + + .reg OStmp8, gr76 + .reg OStmp9, gr77 + .reg OStmp10, gr78 + .reg OStmp11, gr79 + + .equ ROStmp0, &OStmp0 + .equ ROStmp1, &OStmp1 + .equ ROStmp2, &OStmp2 + .equ ROStmp3, &OStmp3 + + .equ ROStmp4, &OStmp4 + .equ ROStmp5, &OStmp5 + .equ ROStmp6, &OStmp6 + .equ ROStmp7, &OStmp7 + + .equ ROStmp8, &OStmp8 + .equ ROStmp9, &OStmp9 + .equ ROStmp10, &OStmp10 + .equ ROStmp11, &OStmp11 + + .global ROStmp0, ROStmp1, ROStmp2, ROStmp3 + .global ROStmp4, ROStmp5, ROStmp6, ROStmp7 + .global ROStmp8, ROStmp9, ROStmp10, ROStmp11 + +; +; Assigning Names to Statics/Permanent Registers. +; + + .reg OSsta0, gr80 ; Spill Address Register + .reg OSsta1, gr81 ; Fill Address Register + .reg OSsta2, gr82 ; Signal Address Register + .reg OSsta3, gr83 ; pcb Register + + .reg OSsta4, gr84 ; + .reg OSsta5, gr85 ; + .reg OSsta6, gr86 ; + .reg OSsta7, gr87 ; + + .reg OSsta8, gr88 ; + .reg OSsta9, gr89 ; + .reg OSsta10, gr90 ; + .reg OSsta11, gr91 ; + + .reg OSsta12, gr92 ; + .reg OSsta13, gr93 ; + .reg OSsta14, gr94 ; + .reg OSsta15, gr95 ; + +; +; Round 2 of Name Assignments +; + +; +; Assignment of Specific Use oriented names to statics. +; + .reg SpillAddrReg, gr80 + .reg FillAddrReg, gr81 + .reg SignalAddrReg, gr82 + .reg pcb, gr83 + + .reg etx, gr80 + .reg ety, gr81 + .reg etz, gr82 + .reg etc, gr83 + +;* + + .reg TimerExt, gr84 + .reg TimerUtil, gr85 + +;* + + .reg LEDReg, gr86 + .reg ERRReg, gr87 + + .reg eta, gr86 + .reg etb, gr87 + +;* + + +;* The following registers are used by switching code + + .reg et0, gr88 + .reg et1, gr89 + .reg et2, gr90 + .reg et3, gr91 + + .reg et4, gr92 + .reg et5, gr93 + .reg et6, gr94 + .reg et7, gr95 + + +; The floating point trap handlers need a few static registers + + .reg FPStat0, gr88 + .reg FPStat1, gr89 + .reg FPStat2, gr90 + .reg FPStat3, gr91 + +; The following registers are used temporarily during diagnostics. + + .reg XLINXReg, gr92 + .reg VMBCReg, gr93 + .reg UARTReg, gr94 + .reg ETHERReg, gr95 + +;* + +;;* + .reg heapptr, gr90 + .reg ArgvPtr, gr91 +;;* + + + +; +;* Preparing to export Register Names for the Linkers benefit. +; + + .equ RSpillAddrReg, &SpillAddrReg + .equ RFillAddrReg, &FillAddrReg + .equ RSignalAddrReg, &SignalAddrReg + .equ Rpcb, &pcb + + .equ Retx, &etx + .equ Rety, &ety + .equ Retz, &etz + .equ Reta, &eta + + .equ Retb, &etb + .equ Retc, &etc + .equ RTimerExt, &TimerExt + .equ RTimerUtil, &TimerUtil + + .equ RLEDReg, &LEDReg + .equ RERRReg, &ERRReg + + .equ Ret0, &et0 + .equ Ret1, &et1 + .equ Ret2, &et2 + .equ Ret3, &et3 + + .equ RFPStat0, &FPStat0 + .equ RFPStat1, &FPStat1 + .equ RFPStat2, &FPStat2 + .equ RFPStat3, &FPStat3 + + .equ Rheapptr, &heapptr + .equ RHeapPtr, &heapptr + .equ RArgvPtr, &ArgvPtr + + .equ Ret4, &et4 + .equ Ret5, &et5 + .equ Ret6, &et6 + .equ Ret7, &et7 + + .equ RXLINXReg, &XLINXReg + .equ RVMBCReg, &VMBCReg + .equ RUARTReg, &UARTReg + .equ RETHERReg, ÐERReg + + .global RSpillAddrReg, RFillAddrReg, RSignalAddrReg + .global Rpcb, Retc + .global RTimerExt, RTimerUtil, RLEDReg, RERRReg + .global Ret0, Ret1, Ret2, Ret3, Ret4, Ret5, Ret6, Ret7, Reta, Retb + .global Retx, Rety, Retz + .global RFPStat0, RFPStat1, RFPStat2, RFPStat3 + .global Rheapptr, RHeapPtr, RArgvPtr + .global RXLINXReg, RVMBCReg, RUARTReg, RETHERReg + +; +;************************************************************************* +; + + +; +; Rule 3: +; Gr96-Gr127 Compiler & Programmer use registers. +; 32 Registers for Compiler & Programmer use + +; +; 16 Registers for Compiler Use. +; + +; +; Compiler Temporaries and Function Return Values +; + + .reg v0, gr96 ; First word of Return Value + .reg v1, gr97 + .reg v2, gr98 + .reg v3, gr99 + + .reg v4, gr100 + .reg v5, gr101 + .reg v6, gr102 + .reg v7, gr103 + + .reg v8, gr104 + .reg v9, gr105 + .reg v10, gr106 + .reg v11, gr107 + + .reg v12, gr108 + .reg v13, gr109 + .reg v14, gr110 + .reg v15, gr111 + + .equ Rv0, &v0 + .equ Rv1, &v1 + .equ Rv2, &v2 + .equ Rv3, &v3 + + .equ Rv4, &v4 + .equ Rv5, &v5 + .equ Rv6, &v6 + .equ Rv7, &v7 + + .equ Rv8, &v8 + .equ Rv9, &v9 + .equ Rv10, &v10 + .equ Rv11, &v11 + + .equ Rv12, &v12 + .equ Rv13, &v13 + .equ Rv14, &v14 + .equ Rv15, &v15 + + .global Rv0, Rv1, Rv2, Rv3, Rv4, Rv5, Rv6, Rv7, Rv8, Rv9 + .global Rv10, Rv11, Rv12, Rv13, Rv14, Rv15 + + +; +; User Process Statics Registers +; + + .reg rp0, gr112 ; Reserved for Programmer, #0 + .reg rp1, gr113 ; Reserved for Programmer, #1 + .reg rp2, gr114 ; Reserved for Programmer, #2 + .reg rp3, gr115 ; Reserved for Programmer, #3 + + .equ Rrp0, &rp0 + .equ Rrp1, &rp1 + .equ Rrp2, &rp2 + .equ Rrp3, &rp3 + + .global Rrp0, Rrp1, Rrp2, Rrp3 + +; +; Compiler Temporaries II +; + + .reg tv0, gr116 ; + .reg tv1, gr117 ; + .reg tv2, gr118 ; + .reg tv3, gr119 ; + .reg tv4, gr120 ; + + .equ Rtv0, &tv0 ; + .equ Rtv1, &tv1 ; + .equ Rtv2, &tv2 ; + .equ Rtv3, &tv3 ; + .equ Rtv4, &tv4 ; + + .global Rtv0, Rtv1, Rtv2, Rtv3, Rtv4 + +; +; Special pointers and registers for handlers and stack operations. +; + + .reg tav, gr121 ; Temp, Arg for Trap Handlers + .reg tpc, gr122 ; Temp, Ret PC for Trap Handlers + .reg lrp, gr123 ; Large Return Pointer + .reg slp, gr124 ; Static Link Pointer + + .reg msp, gr125 ; Memory Stack Pointer + .reg rab, gr126 ; Register Allocate Bound + .reg rfb, gr127 ; Register Free Bound + + .equ Rtav, &tav + .equ Rtpc, &tpc + .equ Rlrp, &lrp + .equ Rslp, &slp + .equ Rmsp, &msp + .equ Rrab, &rab + .equ Rrfb, &rfb + + .global Rtav, Rtpc, Rlrp, Rslp, Rmsp, Rrab, Rrfb diff --git a/c/src/lib/libbsp/a29k/portsw/startup/Makefile.in b/c/src/lib/libbsp/a29k/portsw/startup/Makefile.in index d1b6c6f459..c7affcea52 100644 --- a/c/src/lib/libbsp/a29k/portsw/startup/Makefile.in +++ b/c/src/lib/libbsp/a29k/portsw/startup/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES= -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=ramlink romlink $(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/hppa1.1/simhppa/start/Makefile.in b/c/src/lib/libbsp/hppa1.1/simhppa/start/Makefile.in index bafd65a3ff..d982cdec4c 100644 --- a/c/src/lib/libbsp/hppa1.1/simhppa/start/Makefile.in +++ b/c/src/lib/libbsp/hppa1.1/simhppa/start/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=start -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/hppa1.1/simhppa/start/start.S b/c/src/lib/libbsp/hppa1.1/simhppa/start/start.S new file mode 100644 index 0000000000..86298f0304 --- /dev/null +++ b/c/src/lib/libbsp/hppa1.1/simhppa/start/start.S @@ -0,0 +1,169 @@ +/* + * crt0.S -- startup file for hppa on RTEMS + * + * $Id$ + */ + + .COPYRIGHT "crt0.S for hppa" + + .DATA + +_progname .STRINGZ "simhppa" +_crt0_argv .WORD _progname, 0 + +/* + * Set up the standard spaces (sections) These definitions come + * from /lib/pcc_prefix.s. + */ + .TEXT + +/* + * stuff we need that is defined elsewhere. + */ + .IMPORT boot_card, CODE + .IMPORT _bss_start, DATA + .IMPORT _bss_end, DATA + .IMPORT environ, DATA + +/* + * start -- set things up so the application will run. + * + */ + .PROC + .CALLINFO SAVE_SP, FRAME=48 + .EXPORT $START$,ENTRY + .EXPORT start,ENTRY +$START$ +start: + +/* + * Get a stack + */ + + ldil L%crt_stack+48,%r30 + ldo R%crt_stack+48(%r30),%r30 + +/* + * we need to set %r27 (global data pointer) here + */ + + ldil L%$global$,%r27 + ldo R%$global$(%r27),%r27 + +/* + * zerobss -- zero out the bss section + * XXX We don't do this since simulator and boot rom will do this for us. + */ +#if 0 + ; load the start of bss + ldil L%_bss_start,%r4 + ldo R%_bss_start(%r4),%r4 + + ; load the end of bss + ldil L%_bss_end,%r5 + ldo R%_bss_end(%r5),%r5 + + +bssloop + addi -1,%r5,%r5 ; decrement _bss_end + stb %r0,0(0,%r5) ; we do this by bytes for now even + ; though it is slower, it is safer + combf,= %r4,%r5, bssloop + nop +#endif + + ldi 1,%ret0 + +/* + * Call the "boot_card" routine from the application to get it going. + * We call it as boot_card(1, argv, 0) + */ + + copy %r0, %r24 + + ldil L%_crt0_argv,%r25 + ldo R%_crt0_argv(%r25),%r25 + + bl boot_card,%r2 + ldo 1(%r0), %r26 + + .PROCEND +/* + * _exit -- Exit from the application. Normally we cause a user trap + * to return to the ROM monitor for another run, but with + * this monitor we can not. Still, "C" wants this symbol, it + * should be here. Jumping to 0xF0000004 jumps back into the + * firmware, while writing a 5 to 0xFFFE0030 causes a reset. + */ +_exit_fallthru + .PROC + .CALLINFO + .ENTRY + + ;; This just causes a breakpoint exception + break 0x0,0x0 + bv,n (%rp) + nop + .EXIT + .PROCEND + +/* + * _sr4export -- support for called functions. (mostly for GDB) + */ + .EXPORT _sr4export, ENTRY +_sr4export: + .PROC + .CALLINFO + .ENTRY + + ble 0(%sr4,%r22) + copy %r31,%rp + ldw -18(%sr0,%sp),%rp + ldsid (%sr0,%rp),%r1 + mtsp %r1,%sr0 + be,n 0(%sr0,%rp) + nop + .EXIT + .PROCEND + + + .subspa $UNWIND_START$,QUAD=0,ALIGN=8,ACCESS=0x2c,SORT=56 + .export $UNWIND_START +$UNWIND_START + .subspa $UNWIND$,QUAD=0,ALIGN=8,ACCESS=0x2c,SORT=64 + .subspa $UNWIND_END$,QUAD=0,ALIGN=8,ACCESS=0x2c,SORT=72 + .export $UNWIND_END +$UNWIND_END + .subspa $RECOVER_START$,QUAD=0,ALIGN=4,ACCESS=0x2c,SORT=73 + .export $RECOVER_START +$RECOVER_START + .subspa $RECOVER$,QUAD=0,ALIGN=4,ACCESS=0x2c,SORT=80 + .subspa $RECOVER_END$,QUAD=0,ALIGN=4,ACCESS=0x2c,SORT=88 + .export $RECOVER_END +$RECOVER_END + +/* + * Here we set up the standard date sub spaces. + * + * Set up some room for a stack. We just grab a chunk of memory. + * We also setup some space for the global variable space, which + * must be done using the reserved name "$global$" so "C" code + * can find it. The stack grows towards the higher addresses. + */ + + .subspa $DATA$,QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=16 + .subspa $SHORTDATA$,QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=24 + .subspa $GLOBAL$,QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=40 + .export $global$ +$global$ + .subspa $SHORTBSS$,QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=80,ZERO + .subspa $BSS$,QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=82,ZERO + + .subspa $STACK$,QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=88,ZERO + + .export crt_stack +crt_stack + .comm 0x1000 + + .end + diff --git a/c/src/lib/libbsp/hppa1.1/simhppa/start/start.s b/c/src/lib/libbsp/hppa1.1/simhppa/start/start.s deleted file mode 100644 index 86298f0304..0000000000 --- a/c/src/lib/libbsp/hppa1.1/simhppa/start/start.s +++ /dev/null @@ -1,169 +0,0 @@ -/* - * crt0.S -- startup file for hppa on RTEMS - * - * $Id$ - */ - - .COPYRIGHT "crt0.S for hppa" - - .DATA - -_progname .STRINGZ "simhppa" -_crt0_argv .WORD _progname, 0 - -/* - * Set up the standard spaces (sections) These definitions come - * from /lib/pcc_prefix.s. - */ - .TEXT - -/* - * stuff we need that is defined elsewhere. - */ - .IMPORT boot_card, CODE - .IMPORT _bss_start, DATA - .IMPORT _bss_end, DATA - .IMPORT environ, DATA - -/* - * start -- set things up so the application will run. - * - */ - .PROC - .CALLINFO SAVE_SP, FRAME=48 - .EXPORT $START$,ENTRY - .EXPORT start,ENTRY -$START$ -start: - -/* - * Get a stack - */ - - ldil L%crt_stack+48,%r30 - ldo R%crt_stack+48(%r30),%r30 - -/* - * we need to set %r27 (global data pointer) here - */ - - ldil L%$global$,%r27 - ldo R%$global$(%r27),%r27 - -/* - * zerobss -- zero out the bss section - * XXX We don't do this since simulator and boot rom will do this for us. - */ -#if 0 - ; load the start of bss - ldil L%_bss_start,%r4 - ldo R%_bss_start(%r4),%r4 - - ; load the end of bss - ldil L%_bss_end,%r5 - ldo R%_bss_end(%r5),%r5 - - -bssloop - addi -1,%r5,%r5 ; decrement _bss_end - stb %r0,0(0,%r5) ; we do this by bytes for now even - ; though it is slower, it is safer - combf,= %r4,%r5, bssloop - nop -#endif - - ldi 1,%ret0 - -/* - * Call the "boot_card" routine from the application to get it going. - * We call it as boot_card(1, argv, 0) - */ - - copy %r0, %r24 - - ldil L%_crt0_argv,%r25 - ldo R%_crt0_argv(%r25),%r25 - - bl boot_card,%r2 - ldo 1(%r0), %r26 - - .PROCEND -/* - * _exit -- Exit from the application. Normally we cause a user trap - * to return to the ROM monitor for another run, but with - * this monitor we can not. Still, "C" wants this symbol, it - * should be here. Jumping to 0xF0000004 jumps back into the - * firmware, while writing a 5 to 0xFFFE0030 causes a reset. - */ -_exit_fallthru - .PROC - .CALLINFO - .ENTRY - - ;; This just causes a breakpoint exception - break 0x0,0x0 - bv,n (%rp) - nop - .EXIT - .PROCEND - -/* - * _sr4export -- support for called functions. (mostly for GDB) - */ - .EXPORT _sr4export, ENTRY -_sr4export: - .PROC - .CALLINFO - .ENTRY - - ble 0(%sr4,%r22) - copy %r31,%rp - ldw -18(%sr0,%sp),%rp - ldsid (%sr0,%rp),%r1 - mtsp %r1,%sr0 - be,n 0(%sr0,%rp) - nop - .EXIT - .PROCEND - - - .subspa $UNWIND_START$,QUAD=0,ALIGN=8,ACCESS=0x2c,SORT=56 - .export $UNWIND_START -$UNWIND_START - .subspa $UNWIND$,QUAD=0,ALIGN=8,ACCESS=0x2c,SORT=64 - .subspa $UNWIND_END$,QUAD=0,ALIGN=8,ACCESS=0x2c,SORT=72 - .export $UNWIND_END -$UNWIND_END - .subspa $RECOVER_START$,QUAD=0,ALIGN=4,ACCESS=0x2c,SORT=73 - .export $RECOVER_START -$RECOVER_START - .subspa $RECOVER$,QUAD=0,ALIGN=4,ACCESS=0x2c,SORT=80 - .subspa $RECOVER_END$,QUAD=0,ALIGN=4,ACCESS=0x2c,SORT=88 - .export $RECOVER_END -$RECOVER_END - -/* - * Here we set up the standard date sub spaces. - * - * Set up some room for a stack. We just grab a chunk of memory. - * We also setup some space for the global variable space, which - * must be done using the reserved name "$global$" so "C" code - * can find it. The stack grows towards the higher addresses. - */ - - .subspa $DATA$,QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=16 - .subspa $SHORTDATA$,QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=24 - .subspa $GLOBAL$,QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=40 - .export $global$ -$global$ - .subspa $SHORTBSS$,QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=80,ZERO - .subspa $BSS$,QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=82,ZERO - - .subspa $STACK$,QUAD=1,ALIGN=8,ACCESS=0x1f,SORT=88,ZERO - - .export crt_stack -crt_stack - .comm 0x1000 - - .end - diff --git a/c/src/lib/libbsp/hppa1.1/simhppa/wrapup/Makefile.in b/c/src/lib/libbsp/hppa1.1/simhppa/wrapup/Makefile.in index c072dea725..ef2b28198d 100644 --- a/c/src/lib/libbsp/hppa1.1/simhppa/wrapup/Makefile.in +++ b/c/src/lib/libbsp/hppa1.1/simhppa/wrapup/Makefile.in @@ -8,10 +8,18 @@ VPATH = @srcdir@ RTEMS_ROOT = @top_srcdir@ PROJECT_ROOT = @PROJECT_ROOT@ -BSP_PIECES=startup tty shmsupp +BSP_PIECES=startup tty # pieces to pick up out of libcpu/hppa CPU_PIECES=clock milli timer -GENERIC_PIECES=shmdr +GENERIC_PIECES= + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/lib.cfg + +ifeq ($(HAS_MP),yes) +GENERIC_PIECES += shmdr +BSP_PIECES += shmsupp +endif # bummer; have to use $foreach since % pattern subst rules only replace 1x OBJS=$(foreach piece, $(BSP_PIECES), ../$(piece)/$(ARCH)/$(piece).rel) \ @@ -21,9 +29,6 @@ OBJS=$(foreach piece, $(BSP_PIECES), ../$(piece)/$(ARCH)/$(piece).rel) \ ../../../$(piece)/$(ARCH)/$(piece).rel) LIB=$(ARCH)/libbsp.a -include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg -include $(RTEMS_ROOT)/make/lib.cfg - # # (OPTIONAL) Add local stuff here using += # diff --git a/c/src/lib/libbsp/i386/force386/start/Makefile.in b/c/src/lib/libbsp/i386/force386/start/Makefile.in index 388e25b482..02ce42102d 100644 --- a/c/src/lib/libbsp/i386/force386/start/Makefile.in +++ b/c/src/lib/libbsp/i386/force386/start/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=start -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/i386/force386/start/start.S b/c/src/lib/libbsp/i386/force386/start/start.S new file mode 100644 index 0000000000..c1d0ffd099 --- /dev/null +++ b/c/src/lib/libbsp/i386/force386/start/start.S @@ -0,0 +1,267 @@ +/* start.s + * + * This file contains the entry point for the application. + * The name of this entry point is compiler dependent. + * It jumps to the BSP which is responsible for performing + * all initialization. + * + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include "asm.h" + +/* + * A Descriptor table register has the following format + */ + +.set DTR_LIMIT, 0 # offset of two byte limit +.set DTR_BASE, 2 # offset of four byte base address +.set DTR_SIZE, 6 # size of DTR register + + BEGIN_DATA + EXTERN (Do_Load_IDT) + EXTERN (Do_Load_GDT) + END_DATA + + BEGIN_CODE + + PUBLIC (start) # GNU default entry point + + EXTERN (boot_card) + EXTERN (load_segments) + EXTERN (exit) + +SYM (start): + nop + cli # DISABLE INTERRUPTS!!! +/* + * Load the segment registers + * + * NOTE: Upon return, gs will contain the segment descriptor for + * a segment which maps directly to all of physical memory. + */ + jmp SYM (_load_segments) # load board dependent segments + +/* + * Set up the stack + */ + + PUBLIC (_establish_stack) +SYM (_establish_stack): + + movl $end,eax # eax = end of bss/start of heap + addl $heap_size,eax # eax = end of heap + movl eax,stack_start # Save for brk() routine + addl $stack_size,eax # make room for stack + andl $0xffffffc0,eax # align it on 16 byte boundary + movl eax,esp # set stack pointer + movl eax,ebp # set base pointer +/* + * Zero out the BSS segment + */ +SYM (zero_bss): + cld # make direction flag count up + movl $ SYM (end),ecx # find end of .bss + movl $ SYM (_bss_start),edi # edi = beginning of .bss + subl edi,ecx # ecx = size of .bss in bytes + shrl ecx # size of .bss in longs + shrl ecx + xorl eax,eax # value to clear out memory + repne # while ecx != 0 + stosl # clear a long in the bss + +/* + * Copy the Global Descriptor Table to our space + */ + + sgdt SYM (_Original_GDTR) # save original GDT + movzwl SYM (_Original_GDTR)+DTR_LIMIT,ecx + /* size of GDT in bytes; limit is */ + /* 8192 entries * 8 bytes per */ + + /* + * make ds:esi point to the original GDT + */ + + movl SYM (_Original_GDTR)+DTR_BASE,esi + push ds # save ds + movw gs,ax + movw ax,ds + + /* + * make es:edi point to the new (our copy) GDT + */ + + movl $ SYM (_Global_descriptor_table),edi + + rep + movsb # copy the GDT (ds:esi -> es:edi) + + pop ds # restore ds + + /* + * Build and load new contents of GDTR + */ + movw SYM (_Original_GDTR)+DTR_LIMIT,ecx # set new limit + movw cx, SYM (_New_GDTR)+DTR_LIMIT + + push $ SYM (_Global_descriptor_table) + push es + call SYM (i386_Logical_to_physical) + addl $6,esp + movl eax, SYM (_New_GDTR)+DTR_BASE # set new base + + cmpb $0, SYM (_Do_Load_GDT) # Should the new GDT be loaded? + je SYM (no_gdt_load) # NO, then branch + lgdt SYM (_New_GDTR) # load the new GDT +SYM (no_gdt_load): + +/* + * Copy the Interrupt Descriptor Table to our space + */ + + sidt SYM (_Original_IDTR) # save original IDT + movzwl SYM (_Original_IDTR)+DTR_LIMIT,ecx + /* size of IDT in bytes; limit is */ + /* 256 entries * 8 bytes per */ + + + /* + * make ds:esi point to the original IDT + */ + movl SYM (_Original_IDTR)+DTR_BASE,esi + + push ds # save ds + movw gs,ax + movw ax,ds + + /* + * make es:edi point to the new (our copy) IDT + */ + movl $ SYM (Interrupt_descriptor_table),edi + + rep + movsb # copy the IDT (ds:esi -> es:edi) + pop ds # restore ds + + /* + * Build and load new contents of IDTR + */ + movw SYM (_Original_IDTR+DTR_LIMIT),ecx # set new limit + movw cx,SYM (_New_IDTR)+DTR_LIMIT + + push $ SYM (Interrupt_descriptor_table) + push es + call SYM (i386_Logical_to_physical) + addl $6,esp + movl eax, SYM (_New_IDTR)+DTR_BASE # set new base + + cmpb $0, SYM (_Do_Load_IDT) # Should the new IDT be loaded? + je SYM (no_idt_load) # NO, then branch + lidt SYM (_New_IDTR) # load the new IDT +SYM (no_idt_load): + +/* + * Initialize the i387. + * + * Using the NO WAIT form of the instruction insures that + * if it is not present the board will not lock up or get an + * exception. + */ + + fninit # MUST USE NO-WAIT FORM + +/* + * Transfer control to User's Board Support Package + */ + pushl $0 # environp + pushl $0 # argv + pushl $0 # argc + call SYM (boot_card) + addl $12,esp + +/* + * Clean up + */ + + EXTERN (return_to_monitor) + + PUBLIC (Bsp_cleanup) +SYM (Bsp_cleanup): + cmpb $0, SYM (_Do_Load_IDT) # Was the new IDT loaded? + je SYM (no_idt_restore) # NO, then branch + lidt SYM (_Original_IDTR) # restore the new IDT +SYM (no_idt_restore): + + cmpb $0, SYM (_Do_Load_GDT) # Was the new GDT loaded? + je SYM (no_gdt_restore) # NO, then branch + lgdt SYM (_Original_GDTR) # restore the new GDT +SYM (no_gdt_restore): + jmp SYM (_return_to_monitor) + +END_CODE + +BEGIN_DATA + + .align 2 + PUBLIC (start_frame) +SYM (start_frame): + .long 0 + + PUBLIC (stack_start) +SYM (stack_start): + .long 0 + +END_DATA + +BEGIN_BSS + + PUBLIC(heap_size) + .set heap_size,0x2000 + + PUBLIC(stack_size) + .set stack_size,0x1000 + + PUBLIC (Interrupt_descriptor_table) +SYM (Interrupt_descriptor_table): + .space 256*8 + + PUBLIC (_Original_IDTR) +SYM (_Original_IDTR): + .space DTR_SIZE + + PUBLIC (_New_IDTR) +SYM (_New_IDTR): + .space DTR_SIZE + + PUBLIC (_Global_descriptor_table) +SYM (_Global_descriptor_table): + .space 8192*8 + + PUBLIC (_Original_GDTR) +SYM (_Original_GDTR): + .space DTR_SIZE + + PUBLIC (_New_GDTR) +SYM (_New_GDTR): + .space DTR_SIZE + + PUBLIC (_Physical_base_of_ds) +SYM (_Physical_base_of_ds): + .space 4 + + PUBLIC (_Physical_base_of_cs) +SYM (_Physical_base_of_cs): + .space 4 + +END_BSS +END diff --git a/c/src/lib/libbsp/i386/force386/start/start.s b/c/src/lib/libbsp/i386/force386/start/start.s deleted file mode 100644 index c1d0ffd099..0000000000 --- a/c/src/lib/libbsp/i386/force386/start/start.s +++ /dev/null @@ -1,267 +0,0 @@ -/* start.s - * - * This file contains the entry point for the application. - * The name of this entry point is compiler dependent. - * It jumps to the BSP which is responsible for performing - * all initialization. - * - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include "asm.h" - -/* - * A Descriptor table register has the following format - */ - -.set DTR_LIMIT, 0 # offset of two byte limit -.set DTR_BASE, 2 # offset of four byte base address -.set DTR_SIZE, 6 # size of DTR register - - BEGIN_DATA - EXTERN (Do_Load_IDT) - EXTERN (Do_Load_GDT) - END_DATA - - BEGIN_CODE - - PUBLIC (start) # GNU default entry point - - EXTERN (boot_card) - EXTERN (load_segments) - EXTERN (exit) - -SYM (start): - nop - cli # DISABLE INTERRUPTS!!! -/* - * Load the segment registers - * - * NOTE: Upon return, gs will contain the segment descriptor for - * a segment which maps directly to all of physical memory. - */ - jmp SYM (_load_segments) # load board dependent segments - -/* - * Set up the stack - */ - - PUBLIC (_establish_stack) -SYM (_establish_stack): - - movl $end,eax # eax = end of bss/start of heap - addl $heap_size,eax # eax = end of heap - movl eax,stack_start # Save for brk() routine - addl $stack_size,eax # make room for stack - andl $0xffffffc0,eax # align it on 16 byte boundary - movl eax,esp # set stack pointer - movl eax,ebp # set base pointer -/* - * Zero out the BSS segment - */ -SYM (zero_bss): - cld # make direction flag count up - movl $ SYM (end),ecx # find end of .bss - movl $ SYM (_bss_start),edi # edi = beginning of .bss - subl edi,ecx # ecx = size of .bss in bytes - shrl ecx # size of .bss in longs - shrl ecx - xorl eax,eax # value to clear out memory - repne # while ecx != 0 - stosl # clear a long in the bss - -/* - * Copy the Global Descriptor Table to our space - */ - - sgdt SYM (_Original_GDTR) # save original GDT - movzwl SYM (_Original_GDTR)+DTR_LIMIT,ecx - /* size of GDT in bytes; limit is */ - /* 8192 entries * 8 bytes per */ - - /* - * make ds:esi point to the original GDT - */ - - movl SYM (_Original_GDTR)+DTR_BASE,esi - push ds # save ds - movw gs,ax - movw ax,ds - - /* - * make es:edi point to the new (our copy) GDT - */ - - movl $ SYM (_Global_descriptor_table),edi - - rep - movsb # copy the GDT (ds:esi -> es:edi) - - pop ds # restore ds - - /* - * Build and load new contents of GDTR - */ - movw SYM (_Original_GDTR)+DTR_LIMIT,ecx # set new limit - movw cx, SYM (_New_GDTR)+DTR_LIMIT - - push $ SYM (_Global_descriptor_table) - push es - call SYM (i386_Logical_to_physical) - addl $6,esp - movl eax, SYM (_New_GDTR)+DTR_BASE # set new base - - cmpb $0, SYM (_Do_Load_GDT) # Should the new GDT be loaded? - je SYM (no_gdt_load) # NO, then branch - lgdt SYM (_New_GDTR) # load the new GDT -SYM (no_gdt_load): - -/* - * Copy the Interrupt Descriptor Table to our space - */ - - sidt SYM (_Original_IDTR) # save original IDT - movzwl SYM (_Original_IDTR)+DTR_LIMIT,ecx - /* size of IDT in bytes; limit is */ - /* 256 entries * 8 bytes per */ - - - /* - * make ds:esi point to the original IDT - */ - movl SYM (_Original_IDTR)+DTR_BASE,esi - - push ds # save ds - movw gs,ax - movw ax,ds - - /* - * make es:edi point to the new (our copy) IDT - */ - movl $ SYM (Interrupt_descriptor_table),edi - - rep - movsb # copy the IDT (ds:esi -> es:edi) - pop ds # restore ds - - /* - * Build and load new contents of IDTR - */ - movw SYM (_Original_IDTR+DTR_LIMIT),ecx # set new limit - movw cx,SYM (_New_IDTR)+DTR_LIMIT - - push $ SYM (Interrupt_descriptor_table) - push es - call SYM (i386_Logical_to_physical) - addl $6,esp - movl eax, SYM (_New_IDTR)+DTR_BASE # set new base - - cmpb $0, SYM (_Do_Load_IDT) # Should the new IDT be loaded? - je SYM (no_idt_load) # NO, then branch - lidt SYM (_New_IDTR) # load the new IDT -SYM (no_idt_load): - -/* - * Initialize the i387. - * - * Using the NO WAIT form of the instruction insures that - * if it is not present the board will not lock up or get an - * exception. - */ - - fninit # MUST USE NO-WAIT FORM - -/* - * Transfer control to User's Board Support Package - */ - pushl $0 # environp - pushl $0 # argv - pushl $0 # argc - call SYM (boot_card) - addl $12,esp - -/* - * Clean up - */ - - EXTERN (return_to_monitor) - - PUBLIC (Bsp_cleanup) -SYM (Bsp_cleanup): - cmpb $0, SYM (_Do_Load_IDT) # Was the new IDT loaded? - je SYM (no_idt_restore) # NO, then branch - lidt SYM (_Original_IDTR) # restore the new IDT -SYM (no_idt_restore): - - cmpb $0, SYM (_Do_Load_GDT) # Was the new GDT loaded? - je SYM (no_gdt_restore) # NO, then branch - lgdt SYM (_Original_GDTR) # restore the new GDT -SYM (no_gdt_restore): - jmp SYM (_return_to_monitor) - -END_CODE - -BEGIN_DATA - - .align 2 - PUBLIC (start_frame) -SYM (start_frame): - .long 0 - - PUBLIC (stack_start) -SYM (stack_start): - .long 0 - -END_DATA - -BEGIN_BSS - - PUBLIC(heap_size) - .set heap_size,0x2000 - - PUBLIC(stack_size) - .set stack_size,0x1000 - - PUBLIC (Interrupt_descriptor_table) -SYM (Interrupt_descriptor_table): - .space 256*8 - - PUBLIC (_Original_IDTR) -SYM (_Original_IDTR): - .space DTR_SIZE - - PUBLIC (_New_IDTR) -SYM (_New_IDTR): - .space DTR_SIZE - - PUBLIC (_Global_descriptor_table) -SYM (_Global_descriptor_table): - .space 8192*8 - - PUBLIC (_Original_GDTR) -SYM (_Original_GDTR): - .space DTR_SIZE - - PUBLIC (_New_GDTR) -SYM (_New_GDTR): - .space DTR_SIZE - - PUBLIC (_Physical_base_of_ds) -SYM (_Physical_base_of_ds): - .space 4 - - PUBLIC (_Physical_base_of_cs) -SYM (_Physical_base_of_cs): - .space 4 - -END_BSS -END diff --git a/c/src/lib/libbsp/i386/force386/startup/Makefile.in b/c/src/lib/libbsp/i386/force386/startup/Makefile.in index bda5bb88da..100f7c7385 100644 --- a/c/src/lib/libbsp/i386/force386/startup/Makefile.in +++ b/c/src/lib/libbsp/i386/force386/startup/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=ldsegs -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(srcdir)/linkcmds $(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/i386/force386/startup/ldsegs.S b/c/src/lib/libbsp/i386/force386/startup/ldsegs.S new file mode 100644 index 0000000000..7689a7693f --- /dev/null +++ b/c/src/lib/libbsp/i386/force386/startup/ldsegs.S @@ -0,0 +1,86 @@ +/* _load_segments + * + * This file assists the board independent startup code by + * loading the proper segment register values. The values + * loaded are board dependent. + * + * NOTE: No stack has been established when this routine + * is invoked. It returns by jumping back to bspentry. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include "asm.h" + +BEGIN_CODE + +/* + * FORCEBUG loads us into a virtual address space which + * really starts at PHYSICAL_ADDRESS_BASE. + */ + +.set PHYSICAL_ADDRESS_BASE, 0x00002000 + +/* + * At reset time, FORCEBUG normally has the segment selectors preloaded. + * If a human resets the instruction pointer, this will not have occurred. + * However, no guarantee can be made of the other registers if cs:ip was + * modified to restart the program. Because of this, the BSP reloads all + * segment registers (except cs) with the values they have following + * a reset. + */ + + +.set RESET_SS, 0x40 # initial value of stack segment register +.set RESET_DS, 0x40 # initial value of data segment register +.set RESET_ES, 0x40 # initial value of extra segment register +.set RESET_FS, 0x40 # initial value of "f" segment register +.set RESET_GS, 0x30 # initial value of "g" segment register + + +#define LOAD_SEGMENTS(_value,_segment) \ + movw $ ## _value, ax ; \ + movw ax, _segment + + EXTERN (establish_stack) + + PUBLIC (_load_segments) +SYM (_load_segments): + LOAD_SEGMENTS( RESET_SS, ss ) + LOAD_SEGMENTS( RESET_DS, ds ) + LOAD_SEGMENTS( RESET_ES, es ) + LOAD_SEGMENTS( RESET_FS, fs ) + LOAD_SEGMENTS( RESET_GS, gs ) + + jmp SYM (_establish_stack) # return to the bsp entry code + + PUBLIC (_return_to_monitor) +SYM (_return_to_monitor): + + call SYM (Clock_exit) + movb $0,al + int $0x20 # restart FORCEbug + jmp SYM (start) # FORCEbug does not reset PC + +END_CODE + +BEGIN_DATA + + PUBLIC (_Do_Load_IDT) +SYM (_Do_Load_IDT): + .byte 1 + + PUBLIC (_Do_Load_GDT) +SYM (_Do_Load_GDT): + .byte 0 + +END_DATA +END diff --git a/c/src/lib/libbsp/i386/force386/startup/ldsegs.s b/c/src/lib/libbsp/i386/force386/startup/ldsegs.s deleted file mode 100644 index 7689a7693f..0000000000 --- a/c/src/lib/libbsp/i386/force386/startup/ldsegs.s +++ /dev/null @@ -1,86 +0,0 @@ -/* _load_segments - * - * This file assists the board independent startup code by - * loading the proper segment register values. The values - * loaded are board dependent. - * - * NOTE: No stack has been established when this routine - * is invoked. It returns by jumping back to bspentry. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include "asm.h" - -BEGIN_CODE - -/* - * FORCEBUG loads us into a virtual address space which - * really starts at PHYSICAL_ADDRESS_BASE. - */ - -.set PHYSICAL_ADDRESS_BASE, 0x00002000 - -/* - * At reset time, FORCEBUG normally has the segment selectors preloaded. - * If a human resets the instruction pointer, this will not have occurred. - * However, no guarantee can be made of the other registers if cs:ip was - * modified to restart the program. Because of this, the BSP reloads all - * segment registers (except cs) with the values they have following - * a reset. - */ - - -.set RESET_SS, 0x40 # initial value of stack segment register -.set RESET_DS, 0x40 # initial value of data segment register -.set RESET_ES, 0x40 # initial value of extra segment register -.set RESET_FS, 0x40 # initial value of "f" segment register -.set RESET_GS, 0x30 # initial value of "g" segment register - - -#define LOAD_SEGMENTS(_value,_segment) \ - movw $ ## _value, ax ; \ - movw ax, _segment - - EXTERN (establish_stack) - - PUBLIC (_load_segments) -SYM (_load_segments): - LOAD_SEGMENTS( RESET_SS, ss ) - LOAD_SEGMENTS( RESET_DS, ds ) - LOAD_SEGMENTS( RESET_ES, es ) - LOAD_SEGMENTS( RESET_FS, fs ) - LOAD_SEGMENTS( RESET_GS, gs ) - - jmp SYM (_establish_stack) # return to the bsp entry code - - PUBLIC (_return_to_monitor) -SYM (_return_to_monitor): - - call SYM (Clock_exit) - movb $0,al - int $0x20 # restart FORCEbug - jmp SYM (start) # FORCEbug does not reset PC - -END_CODE - -BEGIN_DATA - - PUBLIC (_Do_Load_IDT) -SYM (_Do_Load_IDT): - .byte 1 - - PUBLIC (_Do_Load_GDT) -SYM (_Do_Load_GDT): - .byte 0 - -END_DATA -END diff --git a/c/src/lib/libbsp/i386/force386/timer/Makefile.in b/c/src/lib/libbsp/i386/force386/timer/Makefile.in index 24809cbed8..21ca9675e7 100644 --- a/c/src/lib/libbsp/i386/force386/timer/Makefile.in +++ b/c/src/lib/libbsp/i386/force386/timer/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=timerisr -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/i386/force386/timer/timerisr.S b/c/src/lib/libbsp/i386/force386/timer/timerisr.S new file mode 100644 index 0000000000..3264248b05 --- /dev/null +++ b/c/src/lib/libbsp/i386/force386/timer/timerisr.S @@ -0,0 +1,34 @@ +/* timer_isr() + * + * This routine provides the ISR for the Z8036 timer on the MVME136 + * board. The timer is set up to generate an interrupt at maximum + * intervals. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include "asm.h" + + BEGIN_CODE + + EXTERN (Ttimer_val) + + PUBLIC (timerisr) +SYM (timerisr): + addl $250, SYM (Ttimer_val) # another 250 microseconds + iret + +END_CODE +END diff --git a/c/src/lib/libbsp/i386/force386/timer/timerisr.s b/c/src/lib/libbsp/i386/force386/timer/timerisr.s deleted file mode 100644 index 3264248b05..0000000000 --- a/c/src/lib/libbsp/i386/force386/timer/timerisr.s +++ /dev/null @@ -1,34 +0,0 @@ -/* timer_isr() - * - * This routine provides the ISR for the Z8036 timer on the MVME136 - * board. The timer is set up to generate an interrupt at maximum - * intervals. - * - * Input parameters: NONE - * - * Output parameters: NONE - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include "asm.h" - - BEGIN_CODE - - EXTERN (Ttimer_val) - - PUBLIC (timerisr) -SYM (timerisr): - addl $250, SYM (Ttimer_val) # another 250 microseconds - iret - -END_CODE -END diff --git a/c/src/lib/libbsp/i386/force386/wrapup/Makefile.in b/c/src/lib/libbsp/i386/force386/wrapup/Makefile.in index 4dc4ea5208..aecc98b975 100644 --- a/c/src/lib/libbsp/i386/force386/wrapup/Makefile.in +++ b/c/src/lib/libbsp/i386/force386/wrapup/Makefile.in @@ -8,17 +8,22 @@ VPATH = @srcdir@ RTEMS_ROOT = @top_srcdir@ PROJECT_ROOT = @PROJECT_ROOT@ -BSP_PIECES=startup clock console shmsupp timer -GENERIC_PIECES=shmdr +BSP_PIECES=startup clock console timer +GENERIC_PIECES= + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/lib.cfg + +ifeq ($(HAS_MP),yes) +GENERIC_PIECES += shmdr +BSP_PIECES += shmsupp +endif # bummer; have to use $foreach since % pattern subst rules only replace 1x OBJS=$(foreach piece, $(BSP_PIECES), ../$(piece)/$(ARCH)/$(piece).rel) \ $(foreach piece, $(GENERIC_PIECES), ../../../$(piece)/$(ARCH)/$(piece).rel) LIB=$(ARCH)/libbsp.a -include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg -include $(RTEMS_ROOT)/make/lib.cfg - # # (OPTIONAL) Add local stuff here using += # diff --git a/c/src/lib/libbsp/i386/go32/timer/Makefile.in b/c/src/lib/libbsp/i386/go32/timer/Makefile.in index 2b32db0b00..939382f56f 100644 --- a/c/src/lib/libbsp/i386/go32/timer/Makefile.in +++ b/c/src/lib/libbsp/i386/go32/timer/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=timerisr -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/i386/go32/timer/timerisr.S b/c/src/lib/libbsp/i386/go32/timer/timerisr.S new file mode 100644 index 0000000000..2e9ccf0dc7 --- /dev/null +++ b/c/src/lib/libbsp/i386/go32/timer/timerisr.S @@ -0,0 +1,41 @@ +/* timer_isr() + * + * This routine provides the ISR for the timer. The timer is set up + * to generate an interrupt at maximum intervals. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include "asm.h" + + BEGIN_CODE + + EXTERN(_Ttimer_val) + + PUBLIC(timerisr) + +SYM (timerisr): + addl $1,_Ttimer_val # another tick + push edx + push eax + movw $0x20,dx + mov edx,eax + outb al,(dx) # touch interrupt controller + pop eax + pop edx + iret + +END_CODE +END diff --git a/c/src/lib/libbsp/i386/go32/timer/timerisr.s b/c/src/lib/libbsp/i386/go32/timer/timerisr.s deleted file mode 100644 index 2e9ccf0dc7..0000000000 --- a/c/src/lib/libbsp/i386/go32/timer/timerisr.s +++ /dev/null @@ -1,41 +0,0 @@ -/* timer_isr() - * - * This routine provides the ISR for the timer. The timer is set up - * to generate an interrupt at maximum intervals. - * - * Input parameters: NONE - * - * Output parameters: NONE - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include "asm.h" - - BEGIN_CODE - - EXTERN(_Ttimer_val) - - PUBLIC(timerisr) - -SYM (timerisr): - addl $1,_Ttimer_val # another tick - push edx - push eax - movw $0x20,dx - mov edx,eax - outb al,(dx) # touch interrupt controller - pop eax - pop edx - iret - -END_CODE -END diff --git a/c/src/lib/libbsp/i386/i386ex/clock/Makefile.in b/c/src/lib/libbsp/i386/i386ex/clock/Makefile.in index e40e10fb1a..fa1ee1bb31 100644 --- a/c/src/lib/libbsp/i386/i386ex/clock/Makefile.in +++ b/c/src/lib/libbsp/i386/i386ex/clock/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES= -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/i386/i386ex/console/Makefile.in b/c/src/lib/libbsp/i386/i386ex/console/Makefile.in index e774529a2b..d1514c7109 100644 --- a/c/src/lib/libbsp/i386/i386ex/console/Makefile.in +++ b/c/src/lib/libbsp/i386/i386ex/console/Makefile.in @@ -19,10 +19,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES= -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/i386/i386ex/start/Makefile.in b/c/src/lib/libbsp/i386/i386ex/start/Makefile.in index e5e5d1c9a0..2c6435a980 100644 --- a/c/src/lib/libbsp/i386/i386ex/start/Makefile.in +++ b/c/src/lib/libbsp/i386/i386ex/start/Makefile.in @@ -18,10 +18,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=start -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/i386/i386ex/start/start.S b/c/src/lib/libbsp/i386/i386ex/start/start.S new file mode 100644 index 0000000000..543a300744 --- /dev/null +++ b/c/src/lib/libbsp/i386/i386ex/start/start.S @@ -0,0 +1,437 @@ +/* + * This file is the main boot and configuration file for the i386ex. It is + * solely responsible for initializing the internal register set to reflect + * the proper board configuration. This version is the "generic" i386ex + * startup: + * + * 1) 512K flask ROM @3f80000 + * 2) 1 Mb RAM @ 0x0 + * 3) Timer0 used as RTEMS clock ticker, 1 msec tick rate. + * 4) READY# is generated by CPU + * + * The file is a multi-section file, with sections as follows: + * 1) interrupt gates, in section "ints" + * 2) interrupt descriptor table, in section "idt" + * 3) global descriptor table, in section "gdt" + * 4) reset in section "reset" + * 5) and initial boot code in section " initial" + * + * Submitted by: + * + * Erik Ivanenko + * University of Toronto + * erik.ivanenko@utoronto.ca + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + + +changes: + SetExRegByte(ICW3S , 0x02 ) # MUST be 0x02 according to intel + SetExRegByte(ICW3M , 0x04 ) # IR2 is cascaded internally: was 0x02 => IR1 is cascaded + + */ + +#include "asm.h" +#include "macros.inc" +#include "80386ex.inc" + +/* + * NEW_GAS Needed for binutils 2.9.1.0.7 and higher + */ + + EXTERN (boot_card) /* exits to bspstart */ + EXTERN (stack_start) /* defined in startup/linkcmds */ + EXTERN (Clock_exit) + + PUBLIC (Interrupt_descriptor_table) + PUBLIC ( SYM(IDTR) ) + PUBLIC( SYM(_initInternalRegisters) ) + +BEGIN_DATA +SYM(IDTR): DESC3( SYM(Interrupt_descriptor_table), 0x07ff ); + +SYM(Interrupt_descriptor_table): /* Now in data section */ + .rept 256 + .word 0,0,0,0 + .endr + +END_DATA + +BEGIN_DATA + PUBLIC (_Global_descriptor_table) + +SYM(GDTR): DESC3( GDT_TABLE, 0x1f ); # one less than the size +SYM (_Global_descriptor_table): +SYM(GDT_TABLE): DESC2(0,0,0,0,0,0); +SYM(GDT_ALIAS): DESC2(32,0x1000,0x0,0x93,0,0x0); +SYM(GDT_CODE): DESC2(0xffff,0,0x0,0x9B,0xDF,0x00); +SYM(GDT_DATA): DESC2(0xffff,0,0x0,0x92,0xDF,0x00); # was CF +SYM(GDT_END): + +END_DATA + + +/* This section is the section that is used by the interrupt + descriptor table. It is used to provide the IDT with the + correct vector offsets. It is for symbol definition only. +*/ + + + .section .reset + + PUBLIC ( SYM(reset) ) +SYM(reset): + nop + cli + jmp SYM(_initInternalRegisters) /* different section in this file */ + .code32 /* in case this section moves */ + nop /* required by CHIP LAB to pad out size */ + nop + nop + nop + nop + + + + .section .initial + +/* + * Enable access to peripheral register at expanded I/O addresses + */ +SYM(_initInternalRegisters): + .code16 + movw $0x8000 , ax + outb al , $REMAPCFGH + xchg al , ah + outb al,$REMAPCFGL + outw ax, $REMAPCFG ; + + +/* + * Configure operation of the A20 Address Line + */ +SYM(A20): + movw $PORT92 , dx + + inb dx , al # clear A20 port reset + andb $0xfe , al # b0 Fast Reset(0)=disabled,(1)=reset triggered + orb $0x02 , al # Bit 1 Fast A20 = 0 (always 0) else enabled. + outb al , dx + +SYM(Watchdog): + movw $WDTSTATUS , dx # address the WDT status port + inb dx , al # get the WDT status + orb $0x01 , al # set the CLKDIS bit + outb al , dx # disable the clock to the WDT + +/* + * Initialize Refresh Control Unit for: + * Refresh Address = 0x0000 + + * Refresh gate between rows is 15.6 uSec + * Using a CLK2 frequency of 50Mhz ( 25Mhz CPU ) + * The refresh unit is enabled + * The refresh pin is not used. + */ + +SYM(InitRCU): + SetExRegWord( RFSCIR , 390) # refresh interval was 390, tried 312 + SetExRegWord( RFSBAD , 0x0) # base address + SetExRegWord( RFSADD , 0x0) # address register + SetExRegWord( RFSCON , 0x8000) # enable bit + +/* + * Initialize clock and power mgmt unit for: + * Clock Frequency = 50 Mhz + * Prescaled clock output = 1 Mhz + * Normal halt instructions + */ + +SYM(InitClk): + SetExRegByte( PWRCON, 0x0 ) + SetExRegWord( CLKPRS, 0x17) # 0x13 for 1.19318 MHz. 0x17 for 1MHz. + +/************************************************************** + * Initialize the Pin Configurations + *************************************************************/ + +/* + * Initialize I/O port 1 for: + * PIN 0 = 1, DCD0# to package pin + * PIN 1 = 1, RTS0# to package pin + * PIN 2 = 1, DTR0# to package pin + * PIN 3 = 1, DSR0# to package pin + * PIN 4 = 1, RI0# to package pin + * PIN 5 = 0, Outport (FLASH Vpp Enable, 0=Enable 1=Disable) + * PIN 6 = 0, Outport (P16_HOLD to 386ex option header JP7 pin 5) + * PIN 7 = 0, Outport (P17_HOLD to 386ex option header JP7 pin 3) + */ + +SYM(InitPort1): + SetExRegByte( P1LTC , 0xff ) + SetExRegByte( P1DIR , 0x0 ) + SetExRegByte( P1CFG , 0x1f) + +/* + * Initialize I/O port 2 for: + * PIN 0 = 0, Outport (P20_CS0# to 386ex option header JP7 pin 11) + * PIN 1 = 0, Outport (P21_CS1# to 386ex option header JP7 pin 9) + * PIN 2 = 1, CS2# (SMRAM) If not using CS2 can be configured as.? + * PIN 3 = 0, Outport ( no connect ) + * PIN 4 = 1, CS#4 (DRAM) + * PIN 5 = 1, RXD0 input. See not for I/0 port 1 pins 1-4 + * PIN 6 = 1, TXD0 output. + * PIN 7 = 1, CTS0# input. + */ + +SYM(InitPort2): + SetExRegByte( P2LTC , 0xff ) + SetExRegByte( P2DIR , 0x0 ) + SetExRegByte( P2CFG , 0xfe) + +/* + * Initialize I/O port 3 P3CFG + * PIN 0 = 1, TMROUT0 to package pin + * PIN 1 = 0, (TMROUT1 to 386ex option header JP7 pin 23) + * PIN 2 = 0, INT0 (IR1) disabled, (P3.2 out to JP7 pin 21) + * PIN 3 = 0, INT1 (IR5) disbled (P3.3 to option header JP7 pin 19) + * PIN 4 = 0, INT2 (IR6) disbled (P3.4 to option header JP7 pin 17) + * PIN 5 = 0, INT2 (IR7) disabled (P3.5 to 386ex header JP7 pin 15) + * PIN 6 = 0, Inport (Debugger Break P3.6/PWRD to package pin ) + * P3.6 selected + * PIN 7 = 0, COMCLK output disabled, 1.8432 Mhz OSC1 oscillator. + * ( Debbugger uses COMCLK as the clocking source ) + * P3.7 connected to package pin. + */ + +SYM(InitPort3): + SetExRegByte( P3LTC , 0xff ) + SetExRegByte( P3DIR , 0x41 ) + SetExRegByte( P3CFG , 0x09 ) # can check TMROUT0 +/* + * Initialize Peripheral Pin Configurations: + * PIN 0 = 1, RTS1# to package pin + * PIN 1 = 1, DTR1# to package pin + * PIN 2 = 1, TXD1 out to package pin + * PIN 3 = 0, EOP#/TC + * PIN 4 = 0, DACK0# + * PIN 5 = 1, Timer2 + * PIN 6 = 0, 0 => CS6# connected to package pin + * PIN 7 = 0, Don't care + */ + +SYM(InitPeriph): + SetExRegByte( PINCFG , 0x24) + +/* + * Initialize the Asynchronous Serial Ports: + * BIT 7 = 1, Internal SIO1 modem signals + * BIT 6 = 1, Internal SIO0 modem signals + * BIT 2 = 0, PSCLK for SSIO clock + * BIT 1 = 1, SERCLK for SIO1 clock + * BIT 0 = 1, SERCLK for SIO0 clock + */ + +SYM(InitSIO): + SetExRegByte( SIOCFG, 0xC3 ) # SIOn clocked internally + + SetExRegByte( LCR0, 0x80 ) # latch DLL0, DLH0 + SetExRegByte( DLL0, 0x51 ) # 0x51 sets to 9600 baud 0x7 -> 115,200 + SetExRegByte( DLH0, 0x00 ) # 0x145 is 2400 baud + SetExRegByte( LCR0, 0x03 ) # enable r/w buffers, IER0 accessible + # mode 8-n-1 + SetExRegByte( IER0, 0x00 ) # was 0x0f All interrupts detected + + SetExRegByte( LCR1, 0x80 ) # latch DLL0, DLH0 + SetExRegByte( DLL1, 0x51 ) # 0x51 set to 9600 baud, 0x7 = 115200 + SetExRegByte( DLH1, 0x00 ) # 0x145 is 2400 baud + SetExRegByte( LCR1, 0x03 ) # enable r/w buffers, IER1 accessible + # reg 8-n-1 + SetExRegByte( IER1, 0x00 ) # was 0x0f - All interrupts detected + +SYM(InitMCR): +/* + * Initialize Timer for: + * BIT 7 = 1, Timer clocks disabled + * BIT 6 = 0, Reserved + * BIT 5 = 1, TMRCLK2 instead of Vcc to Gate2 + * BIT 4 = 0, PSCLK to CLK2 + * BIT 3 = 1, TMRCLK1 instead of Vcc to Gate1 + * BIT 2 = 0, PSCLK to Gate1 + * BIT 1 = 0, Vcc to Gate0 + * BIT 0 = 0, PSCLK to Gate0 + */ + +SYM(InitTimer): + SetExRegByte(TMRCFG , 0x80 ) # All counters disabled, Gates 0,1 + # and 2 are set to Vcc + + SetExRegByte(TMRCON , 0x34 ) # prepare to write counter 0 LSB,MSB + SetExRegByte(TMR0 , 0x00 ) # sfa + SetExRegByte(TMR0 , 0x00 ) # sfa + + + SetExRegByte(TMRCON , 0x70 ) # mode 0 disables on Gate= Vcc + SetExRegByte(TMR1 , 0x00 ) # sfa + SetExRegByte(TMR1 , 0x00 ) # sfa + + SetExRegByte(TMRCON , 0xB0 ) # mode 0 disables on gate =Vcc + SetExRegByte(TMR2 , 0x00 ) # + SetExRegByte(TMR2 , 0x00 ) # + + SetExRegByte(TMRCFG , 0x80 ) # Enable = 0x00 + +/* + * Initialize the DMACFG register for: + * BIT 7 = 1 , Disable DACK#1 + * BITs 6:4 = 100, TMROUT2 connected to DRQ1 + * BIT 3 = 1 , Disable DACK0# + * BIT 2:0 = 000, Pin is connected to DRQ0 + */ + + SetExRegByte(DMACFG , 0xC0 ) + SetExRegByte(DMACMD1, 0x00 ) # disable both DMA channels + SetExRegByte(DMAMOD1, 0x40 ) +/* + * Initialize the INTCFG register for: + * BIT 7 = 0, 8259 cascade disabled + * BIT 3 = 0, SLAVE IR6 connected to Vss + * BIT 2 = 0, SLAVE IR5 connected to Vss + * BIT 1 = 0, SLAVE IR1 connected to SSIOINT + * BIT 0 = 0, SLAVE IR0 connected to Vss + */ + +SYM(InitInt): + + cli # ! + + SetExRegByte(ICW1S , 0x11 ) # EDGE TRIGGERED + SetExRegByte(ICW2S , 0x28 ) # Slave base vector after Master + SetExRegByte(ICW3S , 0x02 ) # slave cascaded to IR2 on master + SetExRegByte(ICW4S , 0x01 ) # must be 0x01 + + SetExRegByte(ICW1M , 0x11 ) # edge triggered + SetExRegByte(ICW2M , 0x20 ) # base vector starts at byte 32 + SetExRegByte(ICW3M , 0x04) # IR2 is cascaded internally + SetExRegByte(ICW4M , 0x01 ) # idem + + SetExRegByte(OCW1M , 0xde ) # IR0 only = 0xfe. for IR5 and IR0 active use 0xde + SetExRegByte(INTCFG , 0x00 ) + + movw $0xFFFB, SYM(i8259s_cache) /* set up same values in cache */ + +SYM(SetCS4): + SetExRegWord(CS4ADL , 0x702) #Configure chip select 4 + SetExRegWord(CS4ADH , 0x00) + SetExRegWord(CS4MSKH, 0x03F) + SetExRegWord(CS4MSKL, 0xFC01) + +SYM(SetUCS1): + SetExRegWord(UCSADL , 0x0304) # 512K block starting at 0x80000 until 0x3f80000 + SetExRegWord(UCSADH , 0x03F8) + SetExRegWord(UCSMSKH, 0x03F7) + SetExRegWord(UCSMSKL, 0xFC01) # configure upper chip select + +/****************************************************** +* The GDT must be in RAM since it must be writeable, +* So, move the whole data section down. +********************************************************/ + + movw $ _ram_data_offset , di + movw $ _ram_data_segment, cx + mov cx , es + + movw $ _data_size , cx + movw $ _rom_data_segment, ax + movw $ _rom_data_offset , si + mov ax , ds + + repne + movsb + +/***************************** + * Load the Global Descriptor + * Table Register + ****************************/ + +#ifdef NEW_GAS + data32 + addr32 +#endif + lgdt SYM(GDTR) # location of GDT + + +SYM(SetUCS): + SetExRegWord(UCSADL, 0x0702) # now 512K starting at 0x3f80000. + SetExRegWord(UCSADH, 0x03f8) + SetExRegWord(UCSMSKH, 0x0007) + SetExRegWord(UCSMSKL, 0xFC01) # configure upper chip select + +/*************************** + * Switch to Protected Mode + ***************************/ + mov cr0, eax + orw $0x1, ax + mov eax, cr0 + +/************************** + * Flush prefetch queue, + * and load CS selector + *********************/ + + ljmpl $ GDT_CODE_PTR , $ SYM(_load_segment_registers) # sets the code selector + +/* + * Load the segment registers + */ +SYM(_load_segment_registers): + .code32 + pLOAD_SEGMENT( GDT_DATA_PTR, fs) + pLOAD_SEGMENT( GDT_DATA_PTR, gs) + pLOAD_SEGMENT( GDT_DATA_PTR, ss) + pLOAD_SEGMENT( GDT_DATA_PTR, ds) + pLOAD_SEGMENT( GDT_DATA_PTR, es) + +/* + * Set up the stack + */ + +SYM(lidtr): + lidt SYM(IDTR) + +SYM (_establish_stack): + movl $end, eax # stack starts right after bss + movl $stack_origin, esp # this is the high starting address + movl $stack_origin, ebp +/* + * Zero out the BSS segment + */ +SYM (zero_bss): + cld # make direction flag count up + movl $ SYM (end),ecx # find end of .bss + movl $ SYM (_bss_start),edi # edi = beginning of .bss + subl edi,ecx # ecx = size of .bss in bytes + shrl ecx # size of .bss in longs + shrl ecx + xorl eax,eax # value to clear out memory + repne # while ecx != 0 + stosl # clear a long in the bss + +/* + * Transfer control to User's Board Support Package + */ + pushl $0 # environp + pushl $0 # argv + pushl $0 # argc + call SYM(boot_card) + addl $12,esp + + cli # stops interrupts from being processed after hlt! + hlt # shutdown + +END + diff --git a/c/src/lib/libbsp/i386/i386ex/start/start.s b/c/src/lib/libbsp/i386/i386ex/start/start.s deleted file mode 100644 index 543a300744..0000000000 --- a/c/src/lib/libbsp/i386/i386ex/start/start.s +++ /dev/null @@ -1,437 +0,0 @@ -/* - * This file is the main boot and configuration file for the i386ex. It is - * solely responsible for initializing the internal register set to reflect - * the proper board configuration. This version is the "generic" i386ex - * startup: - * - * 1) 512K flask ROM @3f80000 - * 2) 1 Mb RAM @ 0x0 - * 3) Timer0 used as RTEMS clock ticker, 1 msec tick rate. - * 4) READY# is generated by CPU - * - * The file is a multi-section file, with sections as follows: - * 1) interrupt gates, in section "ints" - * 2) interrupt descriptor table, in section "idt" - * 3) global descriptor table, in section "gdt" - * 4) reset in section "reset" - * 5) and initial boot code in section " initial" - * - * Submitted by: - * - * Erik Ivanenko - * University of Toronto - * erik.ivanenko@utoronto.ca - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - - -changes: - SetExRegByte(ICW3S , 0x02 ) # MUST be 0x02 according to intel - SetExRegByte(ICW3M , 0x04 ) # IR2 is cascaded internally: was 0x02 => IR1 is cascaded - - */ - -#include "asm.h" -#include "macros.inc" -#include "80386ex.inc" - -/* - * NEW_GAS Needed for binutils 2.9.1.0.7 and higher - */ - - EXTERN (boot_card) /* exits to bspstart */ - EXTERN (stack_start) /* defined in startup/linkcmds */ - EXTERN (Clock_exit) - - PUBLIC (Interrupt_descriptor_table) - PUBLIC ( SYM(IDTR) ) - PUBLIC( SYM(_initInternalRegisters) ) - -BEGIN_DATA -SYM(IDTR): DESC3( SYM(Interrupt_descriptor_table), 0x07ff ); - -SYM(Interrupt_descriptor_table): /* Now in data section */ - .rept 256 - .word 0,0,0,0 - .endr - -END_DATA - -BEGIN_DATA - PUBLIC (_Global_descriptor_table) - -SYM(GDTR): DESC3( GDT_TABLE, 0x1f ); # one less than the size -SYM (_Global_descriptor_table): -SYM(GDT_TABLE): DESC2(0,0,0,0,0,0); -SYM(GDT_ALIAS): DESC2(32,0x1000,0x0,0x93,0,0x0); -SYM(GDT_CODE): DESC2(0xffff,0,0x0,0x9B,0xDF,0x00); -SYM(GDT_DATA): DESC2(0xffff,0,0x0,0x92,0xDF,0x00); # was CF -SYM(GDT_END): - -END_DATA - - -/* This section is the section that is used by the interrupt - descriptor table. It is used to provide the IDT with the - correct vector offsets. It is for symbol definition only. -*/ - - - .section .reset - - PUBLIC ( SYM(reset) ) -SYM(reset): - nop - cli - jmp SYM(_initInternalRegisters) /* different section in this file */ - .code32 /* in case this section moves */ - nop /* required by CHIP LAB to pad out size */ - nop - nop - nop - nop - - - - .section .initial - -/* - * Enable access to peripheral register at expanded I/O addresses - */ -SYM(_initInternalRegisters): - .code16 - movw $0x8000 , ax - outb al , $REMAPCFGH - xchg al , ah - outb al,$REMAPCFGL - outw ax, $REMAPCFG ; - - -/* - * Configure operation of the A20 Address Line - */ -SYM(A20): - movw $PORT92 , dx - - inb dx , al # clear A20 port reset - andb $0xfe , al # b0 Fast Reset(0)=disabled,(1)=reset triggered - orb $0x02 , al # Bit 1 Fast A20 = 0 (always 0) else enabled. - outb al , dx - -SYM(Watchdog): - movw $WDTSTATUS , dx # address the WDT status port - inb dx , al # get the WDT status - orb $0x01 , al # set the CLKDIS bit - outb al , dx # disable the clock to the WDT - -/* - * Initialize Refresh Control Unit for: - * Refresh Address = 0x0000 - - * Refresh gate between rows is 15.6 uSec - * Using a CLK2 frequency of 50Mhz ( 25Mhz CPU ) - * The refresh unit is enabled - * The refresh pin is not used. - */ - -SYM(InitRCU): - SetExRegWord( RFSCIR , 390) # refresh interval was 390, tried 312 - SetExRegWord( RFSBAD , 0x0) # base address - SetExRegWord( RFSADD , 0x0) # address register - SetExRegWord( RFSCON , 0x8000) # enable bit - -/* - * Initialize clock and power mgmt unit for: - * Clock Frequency = 50 Mhz - * Prescaled clock output = 1 Mhz - * Normal halt instructions - */ - -SYM(InitClk): - SetExRegByte( PWRCON, 0x0 ) - SetExRegWord( CLKPRS, 0x17) # 0x13 for 1.19318 MHz. 0x17 for 1MHz. - -/************************************************************** - * Initialize the Pin Configurations - *************************************************************/ - -/* - * Initialize I/O port 1 for: - * PIN 0 = 1, DCD0# to package pin - * PIN 1 = 1, RTS0# to package pin - * PIN 2 = 1, DTR0# to package pin - * PIN 3 = 1, DSR0# to package pin - * PIN 4 = 1, RI0# to package pin - * PIN 5 = 0, Outport (FLASH Vpp Enable, 0=Enable 1=Disable) - * PIN 6 = 0, Outport (P16_HOLD to 386ex option header JP7 pin 5) - * PIN 7 = 0, Outport (P17_HOLD to 386ex option header JP7 pin 3) - */ - -SYM(InitPort1): - SetExRegByte( P1LTC , 0xff ) - SetExRegByte( P1DIR , 0x0 ) - SetExRegByte( P1CFG , 0x1f) - -/* - * Initialize I/O port 2 for: - * PIN 0 = 0, Outport (P20_CS0# to 386ex option header JP7 pin 11) - * PIN 1 = 0, Outport (P21_CS1# to 386ex option header JP7 pin 9) - * PIN 2 = 1, CS2# (SMRAM) If not using CS2 can be configured as.? - * PIN 3 = 0, Outport ( no connect ) - * PIN 4 = 1, CS#4 (DRAM) - * PIN 5 = 1, RXD0 input. See not for I/0 port 1 pins 1-4 - * PIN 6 = 1, TXD0 output. - * PIN 7 = 1, CTS0# input. - */ - -SYM(InitPort2): - SetExRegByte( P2LTC , 0xff ) - SetExRegByte( P2DIR , 0x0 ) - SetExRegByte( P2CFG , 0xfe) - -/* - * Initialize I/O port 3 P3CFG - * PIN 0 = 1, TMROUT0 to package pin - * PIN 1 = 0, (TMROUT1 to 386ex option header JP7 pin 23) - * PIN 2 = 0, INT0 (IR1) disabled, (P3.2 out to JP7 pin 21) - * PIN 3 = 0, INT1 (IR5) disbled (P3.3 to option header JP7 pin 19) - * PIN 4 = 0, INT2 (IR6) disbled (P3.4 to option header JP7 pin 17) - * PIN 5 = 0, INT2 (IR7) disabled (P3.5 to 386ex header JP7 pin 15) - * PIN 6 = 0, Inport (Debugger Break P3.6/PWRD to package pin ) - * P3.6 selected - * PIN 7 = 0, COMCLK output disabled, 1.8432 Mhz OSC1 oscillator. - * ( Debbugger uses COMCLK as the clocking source ) - * P3.7 connected to package pin. - */ - -SYM(InitPort3): - SetExRegByte( P3LTC , 0xff ) - SetExRegByte( P3DIR , 0x41 ) - SetExRegByte( P3CFG , 0x09 ) # can check TMROUT0 -/* - * Initialize Peripheral Pin Configurations: - * PIN 0 = 1, RTS1# to package pin - * PIN 1 = 1, DTR1# to package pin - * PIN 2 = 1, TXD1 out to package pin - * PIN 3 = 0, EOP#/TC - * PIN 4 = 0, DACK0# - * PIN 5 = 1, Timer2 - * PIN 6 = 0, 0 => CS6# connected to package pin - * PIN 7 = 0, Don't care - */ - -SYM(InitPeriph): - SetExRegByte( PINCFG , 0x24) - -/* - * Initialize the Asynchronous Serial Ports: - * BIT 7 = 1, Internal SIO1 modem signals - * BIT 6 = 1, Internal SIO0 modem signals - * BIT 2 = 0, PSCLK for SSIO clock - * BIT 1 = 1, SERCLK for SIO1 clock - * BIT 0 = 1, SERCLK for SIO0 clock - */ - -SYM(InitSIO): - SetExRegByte( SIOCFG, 0xC3 ) # SIOn clocked internally - - SetExRegByte( LCR0, 0x80 ) # latch DLL0, DLH0 - SetExRegByte( DLL0, 0x51 ) # 0x51 sets to 9600 baud 0x7 -> 115,200 - SetExRegByte( DLH0, 0x00 ) # 0x145 is 2400 baud - SetExRegByte( LCR0, 0x03 ) # enable r/w buffers, IER0 accessible - # mode 8-n-1 - SetExRegByte( IER0, 0x00 ) # was 0x0f All interrupts detected - - SetExRegByte( LCR1, 0x80 ) # latch DLL0, DLH0 - SetExRegByte( DLL1, 0x51 ) # 0x51 set to 9600 baud, 0x7 = 115200 - SetExRegByte( DLH1, 0x00 ) # 0x145 is 2400 baud - SetExRegByte( LCR1, 0x03 ) # enable r/w buffers, IER1 accessible - # reg 8-n-1 - SetExRegByte( IER1, 0x00 ) # was 0x0f - All interrupts detected - -SYM(InitMCR): -/* - * Initialize Timer for: - * BIT 7 = 1, Timer clocks disabled - * BIT 6 = 0, Reserved - * BIT 5 = 1, TMRCLK2 instead of Vcc to Gate2 - * BIT 4 = 0, PSCLK to CLK2 - * BIT 3 = 1, TMRCLK1 instead of Vcc to Gate1 - * BIT 2 = 0, PSCLK to Gate1 - * BIT 1 = 0, Vcc to Gate0 - * BIT 0 = 0, PSCLK to Gate0 - */ - -SYM(InitTimer): - SetExRegByte(TMRCFG , 0x80 ) # All counters disabled, Gates 0,1 - # and 2 are set to Vcc - - SetExRegByte(TMRCON , 0x34 ) # prepare to write counter 0 LSB,MSB - SetExRegByte(TMR0 , 0x00 ) # sfa - SetExRegByte(TMR0 , 0x00 ) # sfa - - - SetExRegByte(TMRCON , 0x70 ) # mode 0 disables on Gate= Vcc - SetExRegByte(TMR1 , 0x00 ) # sfa - SetExRegByte(TMR1 , 0x00 ) # sfa - - SetExRegByte(TMRCON , 0xB0 ) # mode 0 disables on gate =Vcc - SetExRegByte(TMR2 , 0x00 ) # - SetExRegByte(TMR2 , 0x00 ) # - - SetExRegByte(TMRCFG , 0x80 ) # Enable = 0x00 - -/* - * Initialize the DMACFG register for: - * BIT 7 = 1 , Disable DACK#1 - * BITs 6:4 = 100, TMROUT2 connected to DRQ1 - * BIT 3 = 1 , Disable DACK0# - * BIT 2:0 = 000, Pin is connected to DRQ0 - */ - - SetExRegByte(DMACFG , 0xC0 ) - SetExRegByte(DMACMD1, 0x00 ) # disable both DMA channels - SetExRegByte(DMAMOD1, 0x40 ) -/* - * Initialize the INTCFG register for: - * BIT 7 = 0, 8259 cascade disabled - * BIT 3 = 0, SLAVE IR6 connected to Vss - * BIT 2 = 0, SLAVE IR5 connected to Vss - * BIT 1 = 0, SLAVE IR1 connected to SSIOINT - * BIT 0 = 0, SLAVE IR0 connected to Vss - */ - -SYM(InitInt): - - cli # ! - - SetExRegByte(ICW1S , 0x11 ) # EDGE TRIGGERED - SetExRegByte(ICW2S , 0x28 ) # Slave base vector after Master - SetExRegByte(ICW3S , 0x02 ) # slave cascaded to IR2 on master - SetExRegByte(ICW4S , 0x01 ) # must be 0x01 - - SetExRegByte(ICW1M , 0x11 ) # edge triggered - SetExRegByte(ICW2M , 0x20 ) # base vector starts at byte 32 - SetExRegByte(ICW3M , 0x04) # IR2 is cascaded internally - SetExRegByte(ICW4M , 0x01 ) # idem - - SetExRegByte(OCW1M , 0xde ) # IR0 only = 0xfe. for IR5 and IR0 active use 0xde - SetExRegByte(INTCFG , 0x00 ) - - movw $0xFFFB, SYM(i8259s_cache) /* set up same values in cache */ - -SYM(SetCS4): - SetExRegWord(CS4ADL , 0x702) #Configure chip select 4 - SetExRegWord(CS4ADH , 0x00) - SetExRegWord(CS4MSKH, 0x03F) - SetExRegWord(CS4MSKL, 0xFC01) - -SYM(SetUCS1): - SetExRegWord(UCSADL , 0x0304) # 512K block starting at 0x80000 until 0x3f80000 - SetExRegWord(UCSADH , 0x03F8) - SetExRegWord(UCSMSKH, 0x03F7) - SetExRegWord(UCSMSKL, 0xFC01) # configure upper chip select - -/****************************************************** -* The GDT must be in RAM since it must be writeable, -* So, move the whole data section down. -********************************************************/ - - movw $ _ram_data_offset , di - movw $ _ram_data_segment, cx - mov cx , es - - movw $ _data_size , cx - movw $ _rom_data_segment, ax - movw $ _rom_data_offset , si - mov ax , ds - - repne - movsb - -/***************************** - * Load the Global Descriptor - * Table Register - ****************************/ - -#ifdef NEW_GAS - data32 - addr32 -#endif - lgdt SYM(GDTR) # location of GDT - - -SYM(SetUCS): - SetExRegWord(UCSADL, 0x0702) # now 512K starting at 0x3f80000. - SetExRegWord(UCSADH, 0x03f8) - SetExRegWord(UCSMSKH, 0x0007) - SetExRegWord(UCSMSKL, 0xFC01) # configure upper chip select - -/*************************** - * Switch to Protected Mode - ***************************/ - mov cr0, eax - orw $0x1, ax - mov eax, cr0 - -/************************** - * Flush prefetch queue, - * and load CS selector - *********************/ - - ljmpl $ GDT_CODE_PTR , $ SYM(_load_segment_registers) # sets the code selector - -/* - * Load the segment registers - */ -SYM(_load_segment_registers): - .code32 - pLOAD_SEGMENT( GDT_DATA_PTR, fs) - pLOAD_SEGMENT( GDT_DATA_PTR, gs) - pLOAD_SEGMENT( GDT_DATA_PTR, ss) - pLOAD_SEGMENT( GDT_DATA_PTR, ds) - pLOAD_SEGMENT( GDT_DATA_PTR, es) - -/* - * Set up the stack - */ - -SYM(lidtr): - lidt SYM(IDTR) - -SYM (_establish_stack): - movl $end, eax # stack starts right after bss - movl $stack_origin, esp # this is the high starting address - movl $stack_origin, ebp -/* - * Zero out the BSS segment - */ -SYM (zero_bss): - cld # make direction flag count up - movl $ SYM (end),ecx # find end of .bss - movl $ SYM (_bss_start),edi # edi = beginning of .bss - subl edi,ecx # ecx = size of .bss in bytes - shrl ecx # size of .bss in longs - shrl ecx - xorl eax,eax # value to clear out memory - repne # while ecx != 0 - stosl # clear a long in the bss - -/* - * Transfer control to User's Board Support Package - */ - pushl $0 # environp - pushl $0 # argv - pushl $0 # argc - call SYM(boot_card) - addl $12,esp - - cli # stops interrupts from being processed after hlt! - hlt # shutdown - -END - diff --git a/c/src/lib/libbsp/i386/i386ex/startup/Makefile.in b/c/src/lib/libbsp/i386/i386ex/startup/Makefile.in index c12bd4662f..c16b99c71e 100644 --- a/c/src/lib/libbsp/i386/i386ex/startup/Makefile.in +++ b/c/src/lib/libbsp/i386/i386ex/startup/Makefile.in @@ -18,11 +18,11 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S # removed initcsu piece, ldsegs piece and flush S_PIECES=irq_asm -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(srcdir)/linkcmds $(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/i386/i386ex/timer/Makefile.in b/c/src/lib/libbsp/i386/i386ex/timer/Makefile.in index 2b32db0b00..939382f56f 100644 --- a/c/src/lib/libbsp/i386/i386ex/timer/Makefile.in +++ b/c/src/lib/libbsp/i386/i386ex/timer/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=timerisr -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/i386/i386ex/timer/timerisr.S b/c/src/lib/libbsp/i386/i386ex/timer/timerisr.S new file mode 100644 index 0000000000..53463e1e70 --- /dev/null +++ b/c/src/lib/libbsp/i386/i386ex/timer/timerisr.S @@ -0,0 +1,40 @@ +/* timer_isr() + * + * This routine provides the ISR for the Z8036 timer on the MVME136 + * board. The timer is set up to generate an interrupt at maximum + * intervals. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include "asm.h" + + BEGIN_CODE + + EXTERN (Ttimer_val) + + PUBLIC (timerisr) +SYM (timerisr): + addl $250, SYM (Ttimer_val) # another 250 microseconds + pushl eax + movb 0xa0,al /* signal generic End Of Interrupt (EOI) to slave PIC */ + outb al, $0x20 + movb $0x20, al + outb al, $0x20 /* signal generic EOI to Master PIC */ + popl eax + iret + +END_CODE +END diff --git a/c/src/lib/libbsp/i386/i386ex/timer/timerisr.s b/c/src/lib/libbsp/i386/i386ex/timer/timerisr.s deleted file mode 100644 index 53463e1e70..0000000000 --- a/c/src/lib/libbsp/i386/i386ex/timer/timerisr.s +++ /dev/null @@ -1,40 +0,0 @@ -/* timer_isr() - * - * This routine provides the ISR for the Z8036 timer on the MVME136 - * board. The timer is set up to generate an interrupt at maximum - * intervals. - * - * Input parameters: NONE - * - * Output parameters: NONE - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include "asm.h" - - BEGIN_CODE - - EXTERN (Ttimer_val) - - PUBLIC (timerisr) -SYM (timerisr): - addl $250, SYM (Ttimer_val) # another 250 microseconds - pushl eax - movb 0xa0,al /* signal generic End Of Interrupt (EOI) to slave PIC */ - outb al, $0x20 - movb $0x20, al - outb al, $0x20 /* signal generic EOI to Master PIC */ - popl eax - iret - -END_CODE -END diff --git a/c/src/lib/libbsp/i386/pc386/console/Makefile.in b/c/src/lib/libbsp/i386/pc386/console/Makefile.in index fa09ab4c80..db76e36aff 100644 --- a/c/src/lib/libbsp/i386/pc386/console/Makefile.in +++ b/c/src/lib/libbsp/i386/pc386/console/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=videoAsm -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/i386/pc386/console/videoAsm.S b/c/src/lib/libbsp/i386/pc386/console/videoAsm.S new file mode 100644 index 0000000000..a8f5cb3156 --- /dev/null +++ b/c/src/lib/libbsp/i386/pc386/console/videoAsm.S @@ -0,0 +1,51 @@ +/* + * videoAsm.S - This file contains code for displaying cursor on the console + * + * Copyright (C) 1998 valette@crf.canon.fr + * + * This code is free software; you can redistribute it and/or + * modify it under the terms of the GNU Library General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This code is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Library General Public License for more details. + * + * You should have received a copy of the GNU Library General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * $Id$ + */ + + .file "videoAsm.s" + +#include + + .text + .align 4 + .globl wr_cursor /* Move cursor position */ + +/* + * void wr_cursor(newPosition, ioBaseAddr) + */ + +wr_cursor: pushl %ecx + movl 8(%esp), %ecx /* Get new cursor position */ + movb $CC_CURSHIGH, %al /* Cursor high location */ + movl 12(%esp), %edx /* Get IO base address */ + outb (%dx) + incw %dx /* Program Data register */ + movb %ch, %al + outb (%dx) /* Update high location cursor */ + decw %dx /* Program Index Register */ + movb $CC_CURSLOW, %al /* Cursor low location */ + outb (%dx) + incw %dx /* Program Data Register */ + movb %cl, %al + outb (%dx) /* Update low location cursor */ + popl %ecx + ret + diff --git a/c/src/lib/libbsp/i386/pc386/console/videoAsm.s b/c/src/lib/libbsp/i386/pc386/console/videoAsm.s deleted file mode 100644 index a8f5cb3156..0000000000 --- a/c/src/lib/libbsp/i386/pc386/console/videoAsm.s +++ /dev/null @@ -1,51 +0,0 @@ -/* - * videoAsm.S - This file contains code for displaying cursor on the console - * - * Copyright (C) 1998 valette@crf.canon.fr - * - * This code is free software; you can redistribute it and/or - * modify it under the terms of the GNU Library General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This code is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Library General Public License for more details. - * - * You should have received a copy of the GNU Library General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * - * $Id$ - */ - - .file "videoAsm.s" - -#include - - .text - .align 4 - .globl wr_cursor /* Move cursor position */ - -/* - * void wr_cursor(newPosition, ioBaseAddr) - */ - -wr_cursor: pushl %ecx - movl 8(%esp), %ecx /* Get new cursor position */ - movb $CC_CURSHIGH, %al /* Cursor high location */ - movl 12(%esp), %edx /* Get IO base address */ - outb (%dx) - incw %dx /* Program Data register */ - movb %ch, %al - outb (%dx) /* Update high location cursor */ - decw %dx /* Program Index Register */ - movb $CC_CURSLOW, %al /* Cursor low location */ - outb (%dx) - incw %dx /* Program Data Register */ - movb %cl, %al - outb (%dx) /* Update low location cursor */ - popl %ecx - ret - diff --git a/c/src/lib/libbsp/i386/pc386/start/start.S b/c/src/lib/libbsp/i386/pc386/start/start.S new file mode 100644 index 0000000000..323aa3d088 --- /dev/null +++ b/c/src/lib/libbsp/i386/pc386/start/start.S @@ -0,0 +1,202 @@ +/*-------------------------------------------------------------------------+ +| start.s v1.1 - PC386 BSP - 1997/08/07 ++--------------------------------------------------------------------------+ +| This file contains the entry point for the application. +| The name of this entry point is compiler dependent. +| It jumps to the BSP which is responsible for performing all initialization. ++--------------------------------------------------------------------------+ +| (C) Copyright 1997 - +| - NavIST Group - Real-Time Distributed Systems and Industrial Automation +| +| http://pandora.ist.utl.pt +| +| Instituto Superior Tecnico * Lisboa * PORTUGAL ++--------------------------------------------------------------------------+ +| Modified the 20/05/1998 by valette@crf.canon.fr in order to give a working +| example of eraly stage debugging via the DEBUG_EARLY_START define. ++--------------------------------------------------------------------------+ +| Disclaimer: +| +| This file is provided "AS IS" without warranty of any kind, either +| expressed or implied. ++--------------------------------------------------------------------------+ +| This code is based on an earlier generation RTEMS i386 start.s and the +| following copyright applies: +| +| ************************************************************************** +| * COPYRIGHT (c) 1989-1998. +| * On-Line Applications Research Corporation (OAR). +| * Copyright assigned to U.S. Government, 1994. +| * +| * The license and distribution terms for this file may be +| * found in the file LICENSE in this distribution or at +| * http://www.OARcorp.com/rtems/license.html. +| ************************************************************************** +| +| $Id$ ++--------------------------------------------------------------------------*/ + +/* + * The most trivial start.s possible. It does not know anything + * about system it is running on, so it will jump to appropriate + * place in BSP specific place to do things it knows nothing about + */ + +#include "asm.h" + +/*----------------------------------------------------------------------------+ +| Size of heap and stack: ++----------------------------------------------------------------------------*/ + +.set STACK_SIZE, 0x1000 + +/*----------------------------------------------------------------------------+ +| CODE section ++----------------------------------------------------------------------------*/ + +BEGIN_CODE + + PUBLIC (start) # GNU default entry point + + EXTERN (boot_card) + EXTERN (_load_segments) + EXTERN (_return_to_monitor) + EXTERN (_IBMPC_initVideo) + EXTERN (debugPollingGetChar) + EXTERN (checkCPUtypeSetCr0) + + +/* + * In case this crashes on your machine and this is not due + * to video mode set by the loader, you may try to define + * the following variable: + */ +/* #define DEBUG_EARLY_START */ + +SYM (start): + /* + * When things are really, REALLY!, bad -- turn on the speaker and + * lock up. This shows whether or not we make it to a certain + * location. + */ +#if 0 + inb $0x61, al + orb $0x03, al + outb al, $0x61 # enable the speaker +speakl: jmp speakl # and SPIN!!! +#endif + + nop + cli # DISABLE INTERRUPTS!!! + cld +#ifdef DEBUG_EARLY_START + /* + * Must get video attribute to have a working printk. + * Note that the following code assume we already have + * valid segments and a stack. It should be true for + * any loader starting RTEMS in protected mode (or + * at least I hope so : -)). + */ + call _IBMPC_initVideo + /* + * try printk and a getchar in polling mode ASAP + */ + pushl $welcome_msg + call printk + addl $4, esp + + /* call debugPollingGetChar */ + +#endif + +/*----------------------------------------------------------------------------+ +| Load the segment registers (this is done by the board's BSP) and perform any +| other board specific initialization procedures, this piece of code +| does not know anything about +| +| NOTE: Upon return, gs will contain the segment descriptor for a segment which +| maps directly to all of physical memory. ++----------------------------------------------------------------------------*/ + + jmp SYM (_load_segments) # load board dependent segments + +/*----------------------------------------------------------------------------+ +| Set up the stack ++----------------------------------------------------------------------------*/ + + PUBLIC (_establish_stack) +SYM (_establish_stack): + + movl $_end, eax # eax = end of bss/start of heap + addl $STACK_SIZE, eax # make room for stack + andl $0xffffffc0, eax # align it on 16 byte boundary + movl eax, esp # set stack pointer + movl eax, ebp # set base pointer + +/*----------------------------------------------------------------------------+ +| Zero out the BSS segment ++----------------------------------------------------------------------------*/ + +SYM (zero_bss): + cld # make direction flag count up + movl $ SYM (_end), ecx # find end of .bss + movl $ SYM (_bss_start), edi # edi = beginning of .bss + subl edi, ecx # ecx = size of .bss in bytes + shrl ecx # size of .bss in longs + shrl ecx + xorl eax, eax # value to clear out memory + repne # while ecx != 0 + stosl # clear a long in the bss + +/*---------------------------------------------------------------------+ +| Check CPU type. Enable Cache and init coprocessor if needed. ++---------------------------------------------------------------------*/ + call checkCPUtypeSetCr0 +/*---------------------------------------------------------------------+ +| Transfer control to User's Board Support Package ++---------------------------------------------------------------------*/ + + pushl $0 # environp + pushl $0 # argv + pushl $0 # argc + call SYM (boot_card) + addl $12, esp + +/*---------------------------------------------------------------------+ +| Clean up - we do not know anything about it, so we will +| jump to BSP specific code to do cleanup ++---------------------------------------------------------------------*/ + + jmp SYM (_return_to_monitor) + +END_CODE + +BEGIN_DATA + + PUBLIC(_stack_size) +SYM(_stack_size): + .long STACK_SIZE + +#ifdef DEBUG_EARLY_START + + PUBLIC (welcome_msg) +SYM (welcome_msg) : + .string "Ready to debug RTEMS ?\nEnter \n" + + PUBLIC (hex_msg) +SYM (hex_msg) : + .string "0x%x\n" + + PUBLIC (made_it_msg) +SYM (made_it_msg) : + .string "made it to %d\n" + +#endif + +END_DATA + +END + + + + diff --git a/c/src/lib/libbsp/i386/pc386/start/start.s b/c/src/lib/libbsp/i386/pc386/start/start.s deleted file mode 100644 index 323aa3d088..0000000000 --- a/c/src/lib/libbsp/i386/pc386/start/start.s +++ /dev/null @@ -1,202 +0,0 @@ -/*-------------------------------------------------------------------------+ -| start.s v1.1 - PC386 BSP - 1997/08/07 -+--------------------------------------------------------------------------+ -| This file contains the entry point for the application. -| The name of this entry point is compiler dependent. -| It jumps to the BSP which is responsible for performing all initialization. -+--------------------------------------------------------------------------+ -| (C) Copyright 1997 - -| - NavIST Group - Real-Time Distributed Systems and Industrial Automation -| -| http://pandora.ist.utl.pt -| -| Instituto Superior Tecnico * Lisboa * PORTUGAL -+--------------------------------------------------------------------------+ -| Modified the 20/05/1998 by valette@crf.canon.fr in order to give a working -| example of eraly stage debugging via the DEBUG_EARLY_START define. -+--------------------------------------------------------------------------+ -| Disclaimer: -| -| This file is provided "AS IS" without warranty of any kind, either -| expressed or implied. -+--------------------------------------------------------------------------+ -| This code is based on an earlier generation RTEMS i386 start.s and the -| following copyright applies: -| -| ************************************************************************** -| * COPYRIGHT (c) 1989-1998. -| * On-Line Applications Research Corporation (OAR). -| * Copyright assigned to U.S. Government, 1994. -| * -| * The license and distribution terms for this file may be -| * found in the file LICENSE in this distribution or at -| * http://www.OARcorp.com/rtems/license.html. -| ************************************************************************** -| -| $Id$ -+--------------------------------------------------------------------------*/ - -/* - * The most trivial start.s possible. It does not know anything - * about system it is running on, so it will jump to appropriate - * place in BSP specific place to do things it knows nothing about - */ - -#include "asm.h" - -/*----------------------------------------------------------------------------+ -| Size of heap and stack: -+----------------------------------------------------------------------------*/ - -.set STACK_SIZE, 0x1000 - -/*----------------------------------------------------------------------------+ -| CODE section -+----------------------------------------------------------------------------*/ - -BEGIN_CODE - - PUBLIC (start) # GNU default entry point - - EXTERN (boot_card) - EXTERN (_load_segments) - EXTERN (_return_to_monitor) - EXTERN (_IBMPC_initVideo) - EXTERN (debugPollingGetChar) - EXTERN (checkCPUtypeSetCr0) - - -/* - * In case this crashes on your machine and this is not due - * to video mode set by the loader, you may try to define - * the following variable: - */ -/* #define DEBUG_EARLY_START */ - -SYM (start): - /* - * When things are really, REALLY!, bad -- turn on the speaker and - * lock up. This shows whether or not we make it to a certain - * location. - */ -#if 0 - inb $0x61, al - orb $0x03, al - outb al, $0x61 # enable the speaker -speakl: jmp speakl # and SPIN!!! -#endif - - nop - cli # DISABLE INTERRUPTS!!! - cld -#ifdef DEBUG_EARLY_START - /* - * Must get video attribute to have a working printk. - * Note that the following code assume we already have - * valid segments and a stack. It should be true for - * any loader starting RTEMS in protected mode (or - * at least I hope so : -)). - */ - call _IBMPC_initVideo - /* - * try printk and a getchar in polling mode ASAP - */ - pushl $welcome_msg - call printk - addl $4, esp - - /* call debugPollingGetChar */ - -#endif - -/*----------------------------------------------------------------------------+ -| Load the segment registers (this is done by the board's BSP) and perform any -| other board specific initialization procedures, this piece of code -| does not know anything about -| -| NOTE: Upon return, gs will contain the segment descriptor for a segment which -| maps directly to all of physical memory. -+----------------------------------------------------------------------------*/ - - jmp SYM (_load_segments) # load board dependent segments - -/*----------------------------------------------------------------------------+ -| Set up the stack -+----------------------------------------------------------------------------*/ - - PUBLIC (_establish_stack) -SYM (_establish_stack): - - movl $_end, eax # eax = end of bss/start of heap - addl $STACK_SIZE, eax # make room for stack - andl $0xffffffc0, eax # align it on 16 byte boundary - movl eax, esp # set stack pointer - movl eax, ebp # set base pointer - -/*----------------------------------------------------------------------------+ -| Zero out the BSS segment -+----------------------------------------------------------------------------*/ - -SYM (zero_bss): - cld # make direction flag count up - movl $ SYM (_end), ecx # find end of .bss - movl $ SYM (_bss_start), edi # edi = beginning of .bss - subl edi, ecx # ecx = size of .bss in bytes - shrl ecx # size of .bss in longs - shrl ecx - xorl eax, eax # value to clear out memory - repne # while ecx != 0 - stosl # clear a long in the bss - -/*---------------------------------------------------------------------+ -| Check CPU type. Enable Cache and init coprocessor if needed. -+---------------------------------------------------------------------*/ - call checkCPUtypeSetCr0 -/*---------------------------------------------------------------------+ -| Transfer control to User's Board Support Package -+---------------------------------------------------------------------*/ - - pushl $0 # environp - pushl $0 # argv - pushl $0 # argc - call SYM (boot_card) - addl $12, esp - -/*---------------------------------------------------------------------+ -| Clean up - we do not know anything about it, so we will -| jump to BSP specific code to do cleanup -+---------------------------------------------------------------------*/ - - jmp SYM (_return_to_monitor) - -END_CODE - -BEGIN_DATA - - PUBLIC(_stack_size) -SYM(_stack_size): - .long STACK_SIZE - -#ifdef DEBUG_EARLY_START - - PUBLIC (welcome_msg) -SYM (welcome_msg) : - .string "Ready to debug RTEMS ?\nEnter \n" - - PUBLIC (hex_msg) -SYM (hex_msg) : - .string "0x%x\n" - - PUBLIC (made_it_msg) -SYM (made_it_msg) : - .string "made it to %d\n" - -#endif - -END_DATA - -END - - - - diff --git a/c/src/lib/libbsp/i386/pc386/start/start16.S b/c/src/lib/libbsp/i386/pc386/start/start16.S new file mode 100644 index 0000000000..4b12408cd6 --- /dev/null +++ b/c/src/lib/libbsp/i386/pc386/start/start16.S @@ -0,0 +1,183 @@ +/*-------------------------------------------------------------------------+ +| start16.s v1.0 - PC386 BSP - 1998/04/13 ++--------------------------------------------------------------------------+ +| This file contains the entry point for the application. +| The name of this entry point is compiler dependent. +| It jumps to the BSP which is responsible for performing all initialization. ++--------------------------------------------------------------------------+ +| (C) Copyright 1997 - +| - NavIST Group - Real-Time Distributed Systems and Industrial Automation +| +| http://pandora.ist.utl.pt +| +| Instituto Superior Tecnico * Lisboa * PORTUGAL ++--------------------------------------------------------------------------+ +| Disclaimer: +| +| This file is provided "AS IS" without warranty of any kind, either +| expressed or implied. ++--------------------------------------------------------------------------+ +| This code is partly based on (from the Linux source tree): +| video.S - Copyright (C) 1995, 1996 Martin Mares ++--------------------------------------------------------------------------*/ + + +/*----------------------------------------------------------------------------+ +| Constants ++----------------------------------------------------------------------------*/ + +.set PROT_CODE_SEG, 0x08 # offset of code segment descriptor into GDT +.set PROT_DATA_SEG, 0x10 # offset of code segment descriptor into GDT +.set CR0_PE, 1 # protected mode flag on CR0 register +.set HDRSTART, HEADERADDR # address of start of bin2boot header +.set HDROFF, 0x24 # offset into bin2boot header of start32 addr +.set STACKOFF, 0x200-0x10 # offset to load into %esp, from start of image + + /* #define NEW_GAS */ +/*----------------------------------------------------------------------------+ +| CODE section ++----------------------------------------------------------------------------*/ + +.text + + .globl _start16 # entry point + .globl start16 +start16: +_start16: + +.code16 + + cli # DISABLE INTERRUPTS!!! + + movw %cs, %ax # + movw %ax, %ds # set the rest of real mode registers + movw %ax, %es # + movw %ax, %ss # + +#if defined(RTEMS_VIDEO_80x50) + + /*---------------------------------------------------------------------+ + | Switch VGA video to 80 lines x 50 columns mode. Has to be done before + | turning protected mode on since it uses BIOS int 10h (video) services. + +---------------------------------------------------------------------*/ + + movw $0x0003, %ax # forced set + int $0x10 + movw $0x1112, %ax # use 8x8 font + xorb %bl, %bl + int $0x10 + movw $0x1201, %ax # turn off cursor emulation + movb $0x34, %bl + int $0x10 + movb $0x01, %ah # define cursor (scan lines 0 to 7) + movw $0x0007, %cx + int $0x10 + +#endif /* RTEMS_VIDEO_80x50 */ + + /*---------------------------------------------------------------------+ + | Bare PC machines boot in real mode! We have to turn protected mode on. + +---------------------------------------------------------------------*/ +#ifdef NEW_GAS + data32 + addr32 +#endif + lgdt gdtptr - start16 # load Global Descriptor Table + movl %cr0, %eax + orl $CR0_PE, %eax + movl %eax, %cr0 # turn on protected mode + +#ifdef NEW_GAS + ljmpl $PROT_CODE_SEG, $1f # flush prefetch queue, and reload %cs +#else + ljmp $PROT_CODE_SEG, $1f # flush prefetch queue, and reload %cs +#endif +.code32 +1: + /*---------------------------------------------------------------------+ + | load the other segment registers + +---------------------------------------------------------------------*/ + movl $PROT_DATA_SEG, %eax + movl %ax, %ds + movl %ax, %es + movl %ax, %ss + movl $start16 + STACKOFF, %esp # set up stack pointer + addl $start16 + STACKOFF, %ebp # set up stack pointer + + /*---------------------------------------------------------------------+ + | we have to enable A20 in order to access memory above 1MByte + +---------------------------------------------------------------------*/ + call empty_8042 + movb $0xD1, %al # command write + outb %al, $0x64 + call empty_8042 + movb $0xDF, %al # A20 on + outb %al, $0x60 + call empty_8042 + + movl %cs:HDRSTART + HDROFF, %eax # + pushl %eax # jump to start of 32 bit code + ret # + +/*----------------------------------------------------------------------------+ +| delay ++------------------------------------------------------------------------------ +| Delay is needed after doing I/O. We do it by writing to a non-existent port. ++----------------------------------------------------------------------------*/ + .globl _delay + .globl delay +delay: +_delay: + outb %al, $0xED # about 1uS delay + ret + +/*----------------------------------------------------------------------------+ +| empty_8042 ++------------------------------------------------------------------------------ +| This routine checks that the keyboard command queue is empty (after emptying +| the output buffers). +| No timeout is used - if this hangs there is something wrong with the machine, +| and we probably couldn't proceed anyway. ++----------------------------------------------------------------------------*/ + .globl _empty_8042 + .globl empty_8042 +empty_8042: +_empty_8042: + call delay + inb $0x64, %al # 8042 status port + testb $0x01, %al # output buffer? + jz no_output + call delay + in $0x60, %al # read it + jmp empty_8042 +no_output: + test $0x02, %al # is input buffer full? + jnz empty_8042 # yes - loop + ret + +/*----------------------------------------------------------------------------+ +| DATA section ++----------------------------------------------------------------------------*/ + +/************************** +* GLOBAL DESCRIPTOR TABLE * +**************************/ + + .p2align 4 +gdtptr: + /* we use the NULL descriptor to store the GDT pointer - a trick quite + nifty due to: Robert Collins (rcollins@x86.org) */ + .word gdtlen - 1 + .long gdtptr + .word 0x0000 + + /* code segment */ + .word 0xffff, 0 + .byte 0, 0x9f, 0xcf, 0 + + /* data segment */ + .word 0xffff, 0 + .byte 0, 0x93, 0xcf, 0 + + .set gdtlen, . - gdtptr # length of GDT + diff --git a/c/src/lib/libbsp/i386/pc386/start/start16.s b/c/src/lib/libbsp/i386/pc386/start/start16.s deleted file mode 100644 index 4b12408cd6..0000000000 --- a/c/src/lib/libbsp/i386/pc386/start/start16.s +++ /dev/null @@ -1,183 +0,0 @@ -/*-------------------------------------------------------------------------+ -| start16.s v1.0 - PC386 BSP - 1998/04/13 -+--------------------------------------------------------------------------+ -| This file contains the entry point for the application. -| The name of this entry point is compiler dependent. -| It jumps to the BSP which is responsible for performing all initialization. -+--------------------------------------------------------------------------+ -| (C) Copyright 1997 - -| - NavIST Group - Real-Time Distributed Systems and Industrial Automation -| -| http://pandora.ist.utl.pt -| -| Instituto Superior Tecnico * Lisboa * PORTUGAL -+--------------------------------------------------------------------------+ -| Disclaimer: -| -| This file is provided "AS IS" without warranty of any kind, either -| expressed or implied. -+--------------------------------------------------------------------------+ -| This code is partly based on (from the Linux source tree): -| video.S - Copyright (C) 1995, 1996 Martin Mares -+--------------------------------------------------------------------------*/ - - -/*----------------------------------------------------------------------------+ -| Constants -+----------------------------------------------------------------------------*/ - -.set PROT_CODE_SEG, 0x08 # offset of code segment descriptor into GDT -.set PROT_DATA_SEG, 0x10 # offset of code segment descriptor into GDT -.set CR0_PE, 1 # protected mode flag on CR0 register -.set HDRSTART, HEADERADDR # address of start of bin2boot header -.set HDROFF, 0x24 # offset into bin2boot header of start32 addr -.set STACKOFF, 0x200-0x10 # offset to load into %esp, from start of image - - /* #define NEW_GAS */ -/*----------------------------------------------------------------------------+ -| CODE section -+----------------------------------------------------------------------------*/ - -.text - - .globl _start16 # entry point - .globl start16 -start16: -_start16: - -.code16 - - cli # DISABLE INTERRUPTS!!! - - movw %cs, %ax # - movw %ax, %ds # set the rest of real mode registers - movw %ax, %es # - movw %ax, %ss # - -#if defined(RTEMS_VIDEO_80x50) - - /*---------------------------------------------------------------------+ - | Switch VGA video to 80 lines x 50 columns mode. Has to be done before - | turning protected mode on since it uses BIOS int 10h (video) services. - +---------------------------------------------------------------------*/ - - movw $0x0003, %ax # forced set - int $0x10 - movw $0x1112, %ax # use 8x8 font - xorb %bl, %bl - int $0x10 - movw $0x1201, %ax # turn off cursor emulation - movb $0x34, %bl - int $0x10 - movb $0x01, %ah # define cursor (scan lines 0 to 7) - movw $0x0007, %cx - int $0x10 - -#endif /* RTEMS_VIDEO_80x50 */ - - /*---------------------------------------------------------------------+ - | Bare PC machines boot in real mode! We have to turn protected mode on. - +---------------------------------------------------------------------*/ -#ifdef NEW_GAS - data32 - addr32 -#endif - lgdt gdtptr - start16 # load Global Descriptor Table - movl %cr0, %eax - orl $CR0_PE, %eax - movl %eax, %cr0 # turn on protected mode - -#ifdef NEW_GAS - ljmpl $PROT_CODE_SEG, $1f # flush prefetch queue, and reload %cs -#else - ljmp $PROT_CODE_SEG, $1f # flush prefetch queue, and reload %cs -#endif -.code32 -1: - /*---------------------------------------------------------------------+ - | load the other segment registers - +---------------------------------------------------------------------*/ - movl $PROT_DATA_SEG, %eax - movl %ax, %ds - movl %ax, %es - movl %ax, %ss - movl $start16 + STACKOFF, %esp # set up stack pointer - addl $start16 + STACKOFF, %ebp # set up stack pointer - - /*---------------------------------------------------------------------+ - | we have to enable A20 in order to access memory above 1MByte - +---------------------------------------------------------------------*/ - call empty_8042 - movb $0xD1, %al # command write - outb %al, $0x64 - call empty_8042 - movb $0xDF, %al # A20 on - outb %al, $0x60 - call empty_8042 - - movl %cs:HDRSTART + HDROFF, %eax # - pushl %eax # jump to start of 32 bit code - ret # - -/*----------------------------------------------------------------------------+ -| delay -+------------------------------------------------------------------------------ -| Delay is needed after doing I/O. We do it by writing to a non-existent port. -+----------------------------------------------------------------------------*/ - .globl _delay - .globl delay -delay: -_delay: - outb %al, $0xED # about 1uS delay - ret - -/*----------------------------------------------------------------------------+ -| empty_8042 -+------------------------------------------------------------------------------ -| This routine checks that the keyboard command queue is empty (after emptying -| the output buffers). -| No timeout is used - if this hangs there is something wrong with the machine, -| and we probably couldn't proceed anyway. -+----------------------------------------------------------------------------*/ - .globl _empty_8042 - .globl empty_8042 -empty_8042: -_empty_8042: - call delay - inb $0x64, %al # 8042 status port - testb $0x01, %al # output buffer? - jz no_output - call delay - in $0x60, %al # read it - jmp empty_8042 -no_output: - test $0x02, %al # is input buffer full? - jnz empty_8042 # yes - loop - ret - -/*----------------------------------------------------------------------------+ -| DATA section -+----------------------------------------------------------------------------*/ - -/************************** -* GLOBAL DESCRIPTOR TABLE * -**************************/ - - .p2align 4 -gdtptr: - /* we use the NULL descriptor to store the GDT pointer - a trick quite - nifty due to: Robert Collins (rcollins@x86.org) */ - .word gdtlen - 1 - .long gdtptr - .word 0x0000 - - /* code segment */ - .word 0xffff, 0 - .byte 0, 0x9f, 0xcf, 0 - - /* data segment */ - .word 0xffff, 0 - .byte 0, 0x93, 0xcf, 0 - - .set gdtlen, . - gdtptr # length of GDT - diff --git a/c/src/lib/libbsp/i386/pc386/startup/Makefile.in b/c/src/lib/libbsp/i386/pc386/startup/Makefile.in index c0da505e2d..6fb8f9cca7 100644 --- a/c/src/lib/libbsp/i386/pc386/startup/Makefile.in +++ b/c/src/lib/libbsp/i386/pc386/startup/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=ldsegs irq_asm -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(srcdir)/linkcmds $(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/i386/pc386/startup/ldsegs.S b/c/src/lib/libbsp/i386/pc386/startup/ldsegs.S new file mode 100644 index 0000000000..8805128e69 --- /dev/null +++ b/c/src/lib/libbsp/i386/pc386/startup/ldsegs.S @@ -0,0 +1,222 @@ +/*-------------------------------------------------------------------------+ +| ldsegs.s v1.1 - PC386 BSP - 1997/08/07 ++--------------------------------------------------------------------------+ +| This file assists the board independent startup code by loading the proper +| segment register values. The values loaded are board dependent. In addition +| it contains code to enable the A20 line and to reprogram the PIC to relocate +| the IRQ interrupt vectors to 0x20 -> 0x2f. +| NOTE: No stack has been established when this routine is invoked. +| It returns by jumping back to bspentry. ++--------------------------------------------------------------------------+ +| (C) Copyright 1997 - +| - NavIST Group - Real-Time Distributed Systems and Industrial Automation +| +| http://pandora.ist.utl.pt +| +| Instituto Superior Tecnico * Lisboa * PORTUGAL ++--------------------------------------------------------------------------+ +| Disclaimer: +| +| This file is provided "AS IS" without warranty of any kind, either +| expressed or implied. ++--------------------------------------------------------------------------+ +| This code is base on: +| ldsegs.s,v 1.4 1996/04/20 16:48:30 joel Exp - go32 BSP +| With the following copyright notice: +| ************************************************************************** +| * COPYRIGHT (c) 1989-1998. +| * On-Line Applications Research Corporation (OAR). +| * Copyright assigned to U.S. Government, 1994. +| * +| * The license and distribution terms for this file may be +| * found in found in the file LICENSE in this distribution or at +| * http://www.OARcorp.com/rtems/license.html. +| ************************************************************************** +| +| $Id$ +| +| Also based on (from the Linux source tree): +| setup.S - Copyright (C) 1991, 1992 Linus Torvalds ++--------------------------------------------------------------------------*/ + + +#include "asm.h" + +/*----------------------------------------------------------------------------+ +| CODE section ++----------------------------------------------------------------------------*/ +EXTERN (rtems_i8259_masks) + +BEGIN_CODE + + EXTERN (_establish_stack) + EXTERN (Timer_exit) + EXTERN (clockOff) + + .p2align 4 +/*----------------------------------------------------------------------------+ +| delay ++------------------------------------------------------------------------------ +| Delay is needed after doing I/O. We do it by writing to a non-existent port. ++----------------------------------------------------------------------------*/ +SYM(delay): + outb al, $0xED # about 1uS delay + ret + +/*-------------------------------------------------------------------------+ +| Function: _load_segments +| Description: Current environment is standard PC booted by grub. +| So, there is no value in saving current GDT and IDT +| settings we have to set it up ourseves. (Naturally +| it will be not so in case we are booted by some +| boot monitor, however, then it will be different +| BSP). After that we have to load board segment registers +| with apropriate values + reprogram PIC. +| Global Variables: None. +| Arguments: None. +| Returns: Nothing. ++--------------------------------------------------------------------------*/ + .p2align 4 + + PUBLIC (_load_segments) +SYM (_load_segments): + + lgdt SYM(gdtdesc) + lidt SYM(idtdesc) + + /* Load CS, flush prefetched queue */ + ljmp $0x8, $next_step + +next_step: + /* Load segment registers */ + movw $0x10, ax + movw ax, ss + movw ax, ds + movw ax, es + movw ax, fs + movw ax, gs + +/*---------------------------------------------------------------------+ +| Now we have to reprogram the interrupts :-(. We put them right after +| the intel-reserved hardware interrupts, at int 0x20-0x2F. There they +| won't mess up anything. Sadly IBM really messed this up with the +| original PC, and they haven't been able to rectify it afterwards. Thus +| the bios puts interrupts at 0x08-0x0f, which is used for the internal +| hardware interrupts as well. We just have to reprogram the 8259's, and +| it isn't fun. ++---------------------------------------------------------------------*/ + + movb $0x11, al /* initialization sequence */ + outb al, $0x20 /* send it to 8259A-1 */ + call SYM(delay) + outb al, $0xA0 /* and to 8259A-2 */ + call SYM(delay) + + movb $0x20, al /* start of hardware int's (0x20) */ + outb al, $0x21 + call SYM(delay) + movb $0x28, al /* start of hardware int's 2 (0x28) */ + outb al, $0xA1 + call SYM(delay) + + movb $0x04, al /* 8259-1 is master */ + outb al, $0x21 + call SYM(delay) + movb $0x02, al /* 8259-2 is slave */ + outb al, $0xA1 + call SYM(delay) + + movb $0x01, al /* 8086 mode for both */ + outb al, $0x21 + call SYM(delay) + outb al, $0xA1 + call SYM(delay) + + movb $0xFF, al /* mask off all interrupts for now */ + outb al, $0xA1 + call SYM(delay) + movb $0xFB, al /* mask all irq's but irq2 which */ + outb al, $0x21 /* is cascaded */ + call SYM(delay) + + movw $0xFFFB, SYM(i8259s_cache) /* set up same values in cache */ + + jmp SYM (_establish_stack) # return to the bsp entry code + +/*-------------------------------------------------------------------------+ +| Function: _return_to_monitor +| Description: Return to board's monitor (we have none so simply restart). +| Global Variables: None. +| Arguments: None. +| Returns: Nothing. ++--------------------------------------------------------------------------*/ + + .p2align 4 + + PUBLIC (_return_to_monitor) +SYM (_return_to_monitor): + + call SYM (Timer_exit) + call SYM (Clock_exit) + jmp SYM (start) + +/*-------------------------------------------------------------------------+ +| Function: _default_int_handler +| Description: default interrupt handler +| Global Variables: None. +| Arguments: None. +| Returns: Nothing. ++--------------------------------------------------------------------------*/ + .p2align 4 + +/*---------------------------------------------------------------------------+ +| GDT itself ++--------------------------------------------------------------------------*/ + + .p2align 4 + + PUBLIC (_Global_descriptor_table) +SYM (_Global_descriptor_table): + + /* NULL segment */ + .word 0, 0 + .byte 0, 0, 0, 0 + + /* code segment */ + .word 0xffff, 0 + .byte 0, 0x9e, 0xcf, 0 + + /* data segment */ + .word 0xffff, 0 + .byte 0, 0x92, 0xcf, 0 + + +/*---------------------------------------------------------------------------+ +| Descriptor of GDT ++--------------------------------------------------------------------------*/ +SYM (gdtdesc): + .word (3*8 - 1) + .long SYM (_Global_descriptor_table) + + +/*---------------------------------------------------------------------------+ +| IDT itself ++---------------------------------------------------------------------------*/ + .p2align 4 + + PUBLIC(Interrupt_descriptor_table) +SYM(Interrupt_descriptor_table): + .rept 256 + .word 0,0,0,0 + .endr + +/*---------------------------------------------------------------------------+ +| Descriptor of IDT ++--------------------------------------------------------------------------*/ +SYM(idtdesc): + .word (256*8 - 1) + .long SYM (Interrupt_descriptor_table) + +END_CODE + +END diff --git a/c/src/lib/libbsp/i386/pc386/startup/ldsegs.s b/c/src/lib/libbsp/i386/pc386/startup/ldsegs.s deleted file mode 100644 index 8805128e69..0000000000 --- a/c/src/lib/libbsp/i386/pc386/startup/ldsegs.s +++ /dev/null @@ -1,222 +0,0 @@ -/*-------------------------------------------------------------------------+ -| ldsegs.s v1.1 - PC386 BSP - 1997/08/07 -+--------------------------------------------------------------------------+ -| This file assists the board independent startup code by loading the proper -| segment register values. The values loaded are board dependent. In addition -| it contains code to enable the A20 line and to reprogram the PIC to relocate -| the IRQ interrupt vectors to 0x20 -> 0x2f. -| NOTE: No stack has been established when this routine is invoked. -| It returns by jumping back to bspentry. -+--------------------------------------------------------------------------+ -| (C) Copyright 1997 - -| - NavIST Group - Real-Time Distributed Systems and Industrial Automation -| -| http://pandora.ist.utl.pt -| -| Instituto Superior Tecnico * Lisboa * PORTUGAL -+--------------------------------------------------------------------------+ -| Disclaimer: -| -| This file is provided "AS IS" without warranty of any kind, either -| expressed or implied. -+--------------------------------------------------------------------------+ -| This code is base on: -| ldsegs.s,v 1.4 1996/04/20 16:48:30 joel Exp - go32 BSP -| With the following copyright notice: -| ************************************************************************** -| * COPYRIGHT (c) 1989-1998. -| * On-Line Applications Research Corporation (OAR). -| * Copyright assigned to U.S. Government, 1994. -| * -| * The license and distribution terms for this file may be -| * found in found in the file LICENSE in this distribution or at -| * http://www.OARcorp.com/rtems/license.html. -| ************************************************************************** -| -| $Id$ -| -| Also based on (from the Linux source tree): -| setup.S - Copyright (C) 1991, 1992 Linus Torvalds -+--------------------------------------------------------------------------*/ - - -#include "asm.h" - -/*----------------------------------------------------------------------------+ -| CODE section -+----------------------------------------------------------------------------*/ -EXTERN (rtems_i8259_masks) - -BEGIN_CODE - - EXTERN (_establish_stack) - EXTERN (Timer_exit) - EXTERN (clockOff) - - .p2align 4 -/*----------------------------------------------------------------------------+ -| delay -+------------------------------------------------------------------------------ -| Delay is needed after doing I/O. We do it by writing to a non-existent port. -+----------------------------------------------------------------------------*/ -SYM(delay): - outb al, $0xED # about 1uS delay - ret - -/*-------------------------------------------------------------------------+ -| Function: _load_segments -| Description: Current environment is standard PC booted by grub. -| So, there is no value in saving current GDT and IDT -| settings we have to set it up ourseves. (Naturally -| it will be not so in case we are booted by some -| boot monitor, however, then it will be different -| BSP). After that we have to load board segment registers -| with apropriate values + reprogram PIC. -| Global Variables: None. -| Arguments: None. -| Returns: Nothing. -+--------------------------------------------------------------------------*/ - .p2align 4 - - PUBLIC (_load_segments) -SYM (_load_segments): - - lgdt SYM(gdtdesc) - lidt SYM(idtdesc) - - /* Load CS, flush prefetched queue */ - ljmp $0x8, $next_step - -next_step: - /* Load segment registers */ - movw $0x10, ax - movw ax, ss - movw ax, ds - movw ax, es - movw ax, fs - movw ax, gs - -/*---------------------------------------------------------------------+ -| Now we have to reprogram the interrupts :-(. We put them right after -| the intel-reserved hardware interrupts, at int 0x20-0x2F. There they -| won't mess up anything. Sadly IBM really messed this up with the -| original PC, and they haven't been able to rectify it afterwards. Thus -| the bios puts interrupts at 0x08-0x0f, which is used for the internal -| hardware interrupts as well. We just have to reprogram the 8259's, and -| it isn't fun. -+---------------------------------------------------------------------*/ - - movb $0x11, al /* initialization sequence */ - outb al, $0x20 /* send it to 8259A-1 */ - call SYM(delay) - outb al, $0xA0 /* and to 8259A-2 */ - call SYM(delay) - - movb $0x20, al /* start of hardware int's (0x20) */ - outb al, $0x21 - call SYM(delay) - movb $0x28, al /* start of hardware int's 2 (0x28) */ - outb al, $0xA1 - call SYM(delay) - - movb $0x04, al /* 8259-1 is master */ - outb al, $0x21 - call SYM(delay) - movb $0x02, al /* 8259-2 is slave */ - outb al, $0xA1 - call SYM(delay) - - movb $0x01, al /* 8086 mode for both */ - outb al, $0x21 - call SYM(delay) - outb al, $0xA1 - call SYM(delay) - - movb $0xFF, al /* mask off all interrupts for now */ - outb al, $0xA1 - call SYM(delay) - movb $0xFB, al /* mask all irq's but irq2 which */ - outb al, $0x21 /* is cascaded */ - call SYM(delay) - - movw $0xFFFB, SYM(i8259s_cache) /* set up same values in cache */ - - jmp SYM (_establish_stack) # return to the bsp entry code - -/*-------------------------------------------------------------------------+ -| Function: _return_to_monitor -| Description: Return to board's monitor (we have none so simply restart). -| Global Variables: None. -| Arguments: None. -| Returns: Nothing. -+--------------------------------------------------------------------------*/ - - .p2align 4 - - PUBLIC (_return_to_monitor) -SYM (_return_to_monitor): - - call SYM (Timer_exit) - call SYM (Clock_exit) - jmp SYM (start) - -/*-------------------------------------------------------------------------+ -| Function: _default_int_handler -| Description: default interrupt handler -| Global Variables: None. -| Arguments: None. -| Returns: Nothing. -+--------------------------------------------------------------------------*/ - .p2align 4 - -/*---------------------------------------------------------------------------+ -| GDT itself -+--------------------------------------------------------------------------*/ - - .p2align 4 - - PUBLIC (_Global_descriptor_table) -SYM (_Global_descriptor_table): - - /* NULL segment */ - .word 0, 0 - .byte 0, 0, 0, 0 - - /* code segment */ - .word 0xffff, 0 - .byte 0, 0x9e, 0xcf, 0 - - /* data segment */ - .word 0xffff, 0 - .byte 0, 0x92, 0xcf, 0 - - -/*---------------------------------------------------------------------------+ -| Descriptor of GDT -+--------------------------------------------------------------------------*/ -SYM (gdtdesc): - .word (3*8 - 1) - .long SYM (_Global_descriptor_table) - - -/*---------------------------------------------------------------------------+ -| IDT itself -+---------------------------------------------------------------------------*/ - .p2align 4 - - PUBLIC(Interrupt_descriptor_table) -SYM(Interrupt_descriptor_table): - .rept 256 - .word 0,0,0,0 - .endr - -/*---------------------------------------------------------------------------+ -| Descriptor of IDT -+--------------------------------------------------------------------------*/ -SYM(idtdesc): - .word (256*8 - 1) - .long SYM (Interrupt_descriptor_table) - -END_CODE - -END diff --git a/c/src/lib/libbsp/i386/pc386/timer/Makefile.in b/c/src/lib/libbsp/i386/pc386/timer/Makefile.in index 24809cbed8..21ca9675e7 100644 --- a/c/src/lib/libbsp/i386/pc386/timer/Makefile.in +++ b/c/src/lib/libbsp/i386/pc386/timer/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=timerisr -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/i386/pc386/timer/timerisr.S b/c/src/lib/libbsp/i386/pc386/timer/timerisr.S new file mode 100644 index 0000000000..f6670efdc1 --- /dev/null +++ b/c/src/lib/libbsp/i386/pc386/timer/timerisr.S @@ -0,0 +1,61 @@ +/*-------------------------------------------------------------------------+ +| timerisr.s v1.1 - PC386 BSP - 1997/08/07 ++--------------------------------------------------------------------------+ +| This file contains the PC386 timer interrupt handler. ++--------------------------------------------------------------------------+ +| (C) Copyright 1997 - +| - NavIST Group - Real-Time Distributed Systems and Industrial Automation +| +| http://pandora.ist.utl.pt +| +| Instituto Superior Tecnico * Lisboa * PORTUGAL ++--------------------------------------------------------------------------+ +| Disclaimer: +| +| This file is provided "AS IS" without warranty of any kind, either +| expressed or implied. ++--------------------------------------------------------------------------+ +| This code is base on: +| timerisr.s,v 1.5 1995/12/19 20:07:45 joel Exp - go32 BSP +| With the following copyright notice: +| ************************************************************************** +| * COPYRIGHT (c) 1989-1998. +| * On-Line Applications Research Corporation (OAR). +| * Copyright assigned to U.S. Government, 1994. +| * +| * The license and distribution terms for this file may be +| * found in found in the file LICENSE in this distribution or at +| * http://www.OARcorp.com/rtems/license.html. +| ************************************************************************** +| +| $Id$ ++--------------------------------------------------------------------------*/ + + +#include "asm.h" + +BEGIN_CODE + + EXTERN(Ttimer_val) + +/*-------------------------------------------------------------------------+ +| Function: rtems_isr timerisr(rtems_vector_number); +| Description: ISR for the timer. The timer is set up to generate an +| interrupt at maximum intervals. +| Global Variables: None. +| Arguments: standard - see RTEMS documentation. +| Returns: standard return value - see RTEMS documentation. ++--------------------------------------------------------------------------*/ + PUBLIC(timerisr) +SYM (timerisr): + incl Ttimer_val # another tick + pushl eax + movb $0x20, al + outb al, $0x20 # signal generic End Of Interrupt (EOI) to PIC + popl eax + iret + +END_CODE + +END + diff --git a/c/src/lib/libbsp/i386/pc386/timer/timerisr.s b/c/src/lib/libbsp/i386/pc386/timer/timerisr.s deleted file mode 100644 index f6670efdc1..0000000000 --- a/c/src/lib/libbsp/i386/pc386/timer/timerisr.s +++ /dev/null @@ -1,61 +0,0 @@ -/*-------------------------------------------------------------------------+ -| timerisr.s v1.1 - PC386 BSP - 1997/08/07 -+--------------------------------------------------------------------------+ -| This file contains the PC386 timer interrupt handler. -+--------------------------------------------------------------------------+ -| (C) Copyright 1997 - -| - NavIST Group - Real-Time Distributed Systems and Industrial Automation -| -| http://pandora.ist.utl.pt -| -| Instituto Superior Tecnico * Lisboa * PORTUGAL -+--------------------------------------------------------------------------+ -| Disclaimer: -| -| This file is provided "AS IS" without warranty of any kind, either -| expressed or implied. -+--------------------------------------------------------------------------+ -| This code is base on: -| timerisr.s,v 1.5 1995/12/19 20:07:45 joel Exp - go32 BSP -| With the following copyright notice: -| ************************************************************************** -| * COPYRIGHT (c) 1989-1998. -| * On-Line Applications Research Corporation (OAR). -| * Copyright assigned to U.S. Government, 1994. -| * -| * The license and distribution terms for this file may be -| * found in found in the file LICENSE in this distribution or at -| * http://www.OARcorp.com/rtems/license.html. -| ************************************************************************** -| -| $Id$ -+--------------------------------------------------------------------------*/ - - -#include "asm.h" - -BEGIN_CODE - - EXTERN(Ttimer_val) - -/*-------------------------------------------------------------------------+ -| Function: rtems_isr timerisr(rtems_vector_number); -| Description: ISR for the timer. The timer is set up to generate an -| interrupt at maximum intervals. -| Global Variables: None. -| Arguments: standard - see RTEMS documentation. -| Returns: standard return value - see RTEMS documentation. -+--------------------------------------------------------------------------*/ - PUBLIC(timerisr) -SYM (timerisr): - incl Ttimer_val # another tick - pushl eax - movb $0x20, al - outb al, $0x20 # signal generic End Of Interrupt (EOI) to PIC - popl eax - iret - -END_CODE - -END - diff --git a/c/src/lib/libbsp/i386/shared/irq/irq_asm.S b/c/src/lib/libbsp/i386/shared/irq/irq_asm.S new file mode 100644 index 0000000000..4be08ed992 --- /dev/null +++ b/c/src/lib/libbsp/i386/shared/irq/irq_asm.S @@ -0,0 +1,250 @@ +/* irq.c + * + * This file contains the implementation of the function described in irq.h + * + * CopyRight (C) 1998 valette@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include "asm.h" +#include + + BEGIN_CODE + +SYM (_ISR_Handler): + /* + * Before this was point is reached the vectors unique + * entry point did the following: + * + * 1. saved scratch registers registers eax edx ecx" + * 2. put the vector number in ecx. + * + * BEGINNING OF ESTABLISH SEGMENTS + * + * WARNING: If an interrupt can occur when the segments are + * not correct, then this is where we should establish + * the segments. In addition to establishing the + * segments, it may be necessary to establish a stack + * in the current data area on the outermost interrupt. + * + * NOTE: If the previous values of the segment registers are + * pushed, do not forget to adjust SAVED_REGS. + * + * NOTE: Make sure the exit code which restores these + * when this type of code is needed. + */ + + /***** ESTABLISH SEGMENTS CODE GOES HERE ******/ + + /* + * END OF ESTABLISH SEGMENTS + */ + + /* + * Now switch stacks if necessary + */ + + movw SYM (i8259s_cache), ax # move current i8259 interrupt mask in ax + pushl eax # push it on the stack + /* + * compute the new PIC mask: + * + * = | irq_mask_or_tbl[] + */ + movw SYM (irq_mask_or_tbl) (,ecx,2), dx + orw dx, ax + /* + * Install new computed value on the i8259 and update cache + * accordingly + */ + movw ax, SYM (i8259s_cache) + outb $PIC_MASTER_IMR_IO_PORT + movb ah, al + outb $PIC_SLAVE_IMR_IO_PORT + + /* + * acknowledge the interrupt + * + */ + movb $PIC_EOI, al + cmpl $7, ecx + jbe .master + outb $PIC_SLAVE_COMMAND_IO_PORT +.master: + outb $PIC_MASTER_COMMAND_IO_PORT + +.check_stack_switch: + pushl ebp + movl esp, ebp # ebp = previous stack pointer + cmpl $0, SYM (_ISR_Nest_level) # is this the outermost interrupt? + jne nested # No, then continue + movl SYM (_CPU_Interrupt_stack_high), esp + + /* + * We want to insure that the old stack pointer is on the + * stack we will be on at the end of the ISR when we restore it. + * By saving it on every interrupt, all we have to do is pop it + * near the end of every interrupt. + */ + +nested: + incl SYM (_ISR_Nest_level) # one nest level deeper + incl SYM (_Thread_Dispatch_disable_level) # disable multitasking + /* + * re-enable interrupts at processor level as the current + * interrupt source is now masked via i8259 + */ + sti + + /* + * ECX is preloaded with the vector number but it is a scratch register + * so we must save it again. + */ + + pushl ecx # push vector number + mov SYM (current_irq) (,ecx,4),eax + # eax = Users handler + call *eax # invoke user ISR + /* + * disable interrupts_again + */ + cli + popl ecx # ecx = vector number + /* + * restore stack + */ + movl ebp, esp + popl ebp + + /* + * restore the original i8259 masks + */ + popl eax + movw ax, SYM (i8259s_cache) + outb $PIC_MASTER_IMR_IO_PORT + movb ah, al + outb $PIC_SLAVE_IMR_IO_PORT + + + decl SYM (_ISR_Nest_level) # one less ISR nest level + # If interrupts are nested, + # then dispatching is disabled + + decl SYM (_Thread_Dispatch_disable_level) + # unnest multitasking + # Is dispatch disabled + jne .exit # Yes, then exit + + cmpl $0, SYM (_Context_Switch_necessary) + # Is task switch necessary? + jne .schedule # Yes, then call the scheduler + + cmpl $0, SYM (_ISR_Signals_to_thread_executing) + # signals sent to Run_thread + # while in interrupt handler? + je .exit # No, exit + + +.bframe: + movl $0, SYM (_ISR_Signals_to_thread_executing) + /* + * This code is the less critical path. In order to have a single + * Thread Context, we take the same frame than the one pushed on + * exceptions. This makes sense because Signal is a software + * exception. + */ + popl edx + popl ecx + popl eax + + pushl $0 # fake fault code + pushl $0 # fake exception number + + pusha + pushl esp + call _ThreadProcessSignalsFromIrq + addl $4, esp + popa + addl $8, esp + iret + +.schedule: + /* + * the scratch registers have already been saved and we are already + * back on the thread system stack. So we can call _Thread_Displatch + * directly + */ + call _Thread_Dispatch + /* + * fall through exit to restore complete contex (scratch registers + * eip, CS, Flags). + */ +.exit: + /* + * BEGINNING OF DE-ESTABLISH SEGMENTS + * + * NOTE: Make sure there is code here if code is added to + * load the segment registers. + * + */ + + /******* DE-ESTABLISH SEGMENTS CODE GOES HERE ********/ + + /* + * END OF DE-ESTABLISH SEGMENTS + */ + popl edx + popl ecx + popl eax + iret + + +#define DISTINCT_INTERRUPT_ENTRY(_vector) \ + .p2align 4 ; \ + PUBLIC (rtems_irq_prologue_ ## _vector ) ; \ +SYM (rtems_irq_prologue_ ## _vector ): \ + pushl eax ; \ + pushl ecx ; \ + pushl edx ; \ + movl $ _vector, ecx ; \ + jmp SYM (_ISR_Handler) ; + +DISTINCT_INTERRUPT_ENTRY(0) +DISTINCT_INTERRUPT_ENTRY(1) +DISTINCT_INTERRUPT_ENTRY(2) +DISTINCT_INTERRUPT_ENTRY(3) +DISTINCT_INTERRUPT_ENTRY(4) +DISTINCT_INTERRUPT_ENTRY(5) +DISTINCT_INTERRUPT_ENTRY(6) +DISTINCT_INTERRUPT_ENTRY(7) +DISTINCT_INTERRUPT_ENTRY(8) +DISTINCT_INTERRUPT_ENTRY(9) +DISTINCT_INTERRUPT_ENTRY(10) +DISTINCT_INTERRUPT_ENTRY(11) +DISTINCT_INTERRUPT_ENTRY(12) +DISTINCT_INTERRUPT_ENTRY(13) +DISTINCT_INTERRUPT_ENTRY(14) +DISTINCT_INTERRUPT_ENTRY(15) + + /* + * routine used to initialize the IDT by default + */ + +PUBLIC (default_raw_idt_handler) +PUBLIC (raw_idt_notify) + +SYM (default_raw_idt_handler): + pusha + cld + call raw_idt_notify + popa + iret + +END_CODE + +END diff --git a/c/src/lib/libbsp/i386/shared/irq/irq_asm.s b/c/src/lib/libbsp/i386/shared/irq/irq_asm.s deleted file mode 100644 index 4be08ed992..0000000000 --- a/c/src/lib/libbsp/i386/shared/irq/irq_asm.s +++ /dev/null @@ -1,250 +0,0 @@ -/* irq.c - * - * This file contains the implementation of the function described in irq.h - * - * CopyRight (C) 1998 valette@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include "asm.h" -#include - - BEGIN_CODE - -SYM (_ISR_Handler): - /* - * Before this was point is reached the vectors unique - * entry point did the following: - * - * 1. saved scratch registers registers eax edx ecx" - * 2. put the vector number in ecx. - * - * BEGINNING OF ESTABLISH SEGMENTS - * - * WARNING: If an interrupt can occur when the segments are - * not correct, then this is where we should establish - * the segments. In addition to establishing the - * segments, it may be necessary to establish a stack - * in the current data area on the outermost interrupt. - * - * NOTE: If the previous values of the segment registers are - * pushed, do not forget to adjust SAVED_REGS. - * - * NOTE: Make sure the exit code which restores these - * when this type of code is needed. - */ - - /***** ESTABLISH SEGMENTS CODE GOES HERE ******/ - - /* - * END OF ESTABLISH SEGMENTS - */ - - /* - * Now switch stacks if necessary - */ - - movw SYM (i8259s_cache), ax # move current i8259 interrupt mask in ax - pushl eax # push it on the stack - /* - * compute the new PIC mask: - * - * = | irq_mask_or_tbl[] - */ - movw SYM (irq_mask_or_tbl) (,ecx,2), dx - orw dx, ax - /* - * Install new computed value on the i8259 and update cache - * accordingly - */ - movw ax, SYM (i8259s_cache) - outb $PIC_MASTER_IMR_IO_PORT - movb ah, al - outb $PIC_SLAVE_IMR_IO_PORT - - /* - * acknowledge the interrupt - * - */ - movb $PIC_EOI, al - cmpl $7, ecx - jbe .master - outb $PIC_SLAVE_COMMAND_IO_PORT -.master: - outb $PIC_MASTER_COMMAND_IO_PORT - -.check_stack_switch: - pushl ebp - movl esp, ebp # ebp = previous stack pointer - cmpl $0, SYM (_ISR_Nest_level) # is this the outermost interrupt? - jne nested # No, then continue - movl SYM (_CPU_Interrupt_stack_high), esp - - /* - * We want to insure that the old stack pointer is on the - * stack we will be on at the end of the ISR when we restore it. - * By saving it on every interrupt, all we have to do is pop it - * near the end of every interrupt. - */ - -nested: - incl SYM (_ISR_Nest_level) # one nest level deeper - incl SYM (_Thread_Dispatch_disable_level) # disable multitasking - /* - * re-enable interrupts at processor level as the current - * interrupt source is now masked via i8259 - */ - sti - - /* - * ECX is preloaded with the vector number but it is a scratch register - * so we must save it again. - */ - - pushl ecx # push vector number - mov SYM (current_irq) (,ecx,4),eax - # eax = Users handler - call *eax # invoke user ISR - /* - * disable interrupts_again - */ - cli - popl ecx # ecx = vector number - /* - * restore stack - */ - movl ebp, esp - popl ebp - - /* - * restore the original i8259 masks - */ - popl eax - movw ax, SYM (i8259s_cache) - outb $PIC_MASTER_IMR_IO_PORT - movb ah, al - outb $PIC_SLAVE_IMR_IO_PORT - - - decl SYM (_ISR_Nest_level) # one less ISR nest level - # If interrupts are nested, - # then dispatching is disabled - - decl SYM (_Thread_Dispatch_disable_level) - # unnest multitasking - # Is dispatch disabled - jne .exit # Yes, then exit - - cmpl $0, SYM (_Context_Switch_necessary) - # Is task switch necessary? - jne .schedule # Yes, then call the scheduler - - cmpl $0, SYM (_ISR_Signals_to_thread_executing) - # signals sent to Run_thread - # while in interrupt handler? - je .exit # No, exit - - -.bframe: - movl $0, SYM (_ISR_Signals_to_thread_executing) - /* - * This code is the less critical path. In order to have a single - * Thread Context, we take the same frame than the one pushed on - * exceptions. This makes sense because Signal is a software - * exception. - */ - popl edx - popl ecx - popl eax - - pushl $0 # fake fault code - pushl $0 # fake exception number - - pusha - pushl esp - call _ThreadProcessSignalsFromIrq - addl $4, esp - popa - addl $8, esp - iret - -.schedule: - /* - * the scratch registers have already been saved and we are already - * back on the thread system stack. So we can call _Thread_Displatch - * directly - */ - call _Thread_Dispatch - /* - * fall through exit to restore complete contex (scratch registers - * eip, CS, Flags). - */ -.exit: - /* - * BEGINNING OF DE-ESTABLISH SEGMENTS - * - * NOTE: Make sure there is code here if code is added to - * load the segment registers. - * - */ - - /******* DE-ESTABLISH SEGMENTS CODE GOES HERE ********/ - - /* - * END OF DE-ESTABLISH SEGMENTS - */ - popl edx - popl ecx - popl eax - iret - - -#define DISTINCT_INTERRUPT_ENTRY(_vector) \ - .p2align 4 ; \ - PUBLIC (rtems_irq_prologue_ ## _vector ) ; \ -SYM (rtems_irq_prologue_ ## _vector ): \ - pushl eax ; \ - pushl ecx ; \ - pushl edx ; \ - movl $ _vector, ecx ; \ - jmp SYM (_ISR_Handler) ; - -DISTINCT_INTERRUPT_ENTRY(0) -DISTINCT_INTERRUPT_ENTRY(1) -DISTINCT_INTERRUPT_ENTRY(2) -DISTINCT_INTERRUPT_ENTRY(3) -DISTINCT_INTERRUPT_ENTRY(4) -DISTINCT_INTERRUPT_ENTRY(5) -DISTINCT_INTERRUPT_ENTRY(6) -DISTINCT_INTERRUPT_ENTRY(7) -DISTINCT_INTERRUPT_ENTRY(8) -DISTINCT_INTERRUPT_ENTRY(9) -DISTINCT_INTERRUPT_ENTRY(10) -DISTINCT_INTERRUPT_ENTRY(11) -DISTINCT_INTERRUPT_ENTRY(12) -DISTINCT_INTERRUPT_ENTRY(13) -DISTINCT_INTERRUPT_ENTRY(14) -DISTINCT_INTERRUPT_ENTRY(15) - - /* - * routine used to initialize the IDT by default - */ - -PUBLIC (default_raw_idt_handler) -PUBLIC (raw_idt_notify) - -SYM (default_raw_idt_handler): - pusha - cld - call raw_idt_notify - popa - iret - -END_CODE - -END diff --git a/c/src/lib/libbsp/i960/cvme961/start/Makefile.in b/c/src/lib/libbsp/i960/cvme961/start/Makefile.in index 68dcd2196e..1ed947fc54 100644 --- a/c/src/lib/libbsp/i960/cvme961/start/Makefile.in +++ b/c/src/lib/libbsp/i960/cvme961/start/Makefile.in @@ -15,10 +15,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=start -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/i960/cvme961/start/start.S b/c/src/lib/libbsp/i960/cvme961/start/start.S new file mode 100644 index 0000000000..1d6055363a --- /dev/null +++ b/c/src/lib/libbsp/i960/cvme961/start/start.S @@ -0,0 +1,110 @@ +/* entry.s + * + * This file contains the entry point for the application. + * The name of this entry point is compiler dependent. + * It jumps to the BSP which is responsible for performing + * all initialization. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include "asm.h" + + BEGIN_CODE + PUBLIC(start) # GNU960 default entry point + +SYM(start): + mov 3, r12 + modpc r12, r12, r12 # enable tracing/trace faults + mov g5, g5 # NOP + mov 0, g14 # initialize constant for C + + /* + * zero out uninitialized data area + */ +zerobss: + lda _end, r4 /* find end of .bss */ + lda _bss_start, r5 /* find beginning of .bss */ + ldconst 0, r6 + +loop: st r6, (r5) /* to zero out uninitialized */ + addo 4, r5, r5 /* data area */ + cmpobl r5, r4, loop /* loop until _end reached */ + +/* set up stack pointer: + * The heap will begin at '_end'; its length is 'heap_size' + * bytes. The stack will begin at the first 64-byte-aligned + * block after the heap. + * + * A default value of 'heap_size' is set by linking with libnindy.a + * The default can be overridden by redefining this symbol at link + * time (with a line of the form 'heap_size=XXXX;' in the lnk960 + * linker specification file; or one of the form + * "-defsym heap_size=XXXX" on the gld960 invocation line). + */ + + ldconst _end, sp /* set sp = address of end of heap */ + lda heap_size(sp),sp + lda 64(sp), sp /* Now round up to 64-byte boundary */ + ldconst 0xffffffc0, r12 + and r12, sp, sp + st sp, _stack_start /* Save for brk() routine */ + + call init_frames + ret /* return to monitor */ + +init_frames: + mov 0, g14 /* initialize constant for C */ + ldconst 0x3b001000, g0 + ldconst 0x00009107, g1 + modac g1, g0, g0 /* set AC controls */ + + /* + * remember the frame, so that we can set it up if necessary + */ + + st fp, _start_frame + + /* + * Call application boot_card. + * Someday, real values of argc and argv will be set up. + * For now, they are set to 0. + */ + ldconst 0,g0 + ldconst 0,g1 + ldconst 0,g2 + call _boot_card + ret + +END_CODE + + BEGIN_DATA + + PUBLIC(_start_frame) + PUBLIC(start_frame) +SYM (_start_frame): +SYM (start_frame): + .word 0 # addr of first user frame: for gdb960 + + PUBLIC(_stack_start) + PUBLIC(stack_start) +SYM (_stack_start): +SYM (stack_start): + .word 0 # addr of first user frame: for gdb960 + +END_DATA + +BEGIN_BSS + PUBLIC(heap_size) + .set heap_size,0x2000 +END_BSS + +END diff --git a/c/src/lib/libbsp/i960/cvme961/timer/Makefile.in b/c/src/lib/libbsp/i960/cvme961/timer/Makefile.in index 24809cbed8..21ca9675e7 100644 --- a/c/src/lib/libbsp/i960/cvme961/timer/Makefile.in +++ b/c/src/lib/libbsp/i960/cvme961/timer/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=timerisr -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/i960/cvme961/timer/timerisr.S b/c/src/lib/libbsp/i960/cvme961/timer/timerisr.S new file mode 100644 index 0000000000..edce480326 --- /dev/null +++ b/c/src/lib/libbsp/i960/cvme961/timer/timerisr.S @@ -0,0 +1,65 @@ +/* timer_isr() + * + * This routine initializes the Z8536 timer on the SQSIO4 SQUALL + * board for the CVME961 board. The timer is setup to provide a + * tick every 0x10000 / 2 milliseconds. This is used to time + * executing code. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include "asm.h" + +.set PORT_A, 0xc00000a8 # port A +.set PORT_B, 0xc00000a4 # port B +.set PORT_C, 0xc00000a0 # port C +.set CTL_PORT, 0xc00000ac # control port + +.set T1CSR, 0x0a # T1 command/status reg +.set RELOAD, 0x24 # clr IP & IUS,allow countdown + +/* + * Duplicating this symbol is stupid but eliminates + * toolset variation problems. + */ + PUBLIC(timerisr) + PUBLIC(_timerisr) +SYM (timerisr): +SYM (_timerisr): + #ldconst 1,r4 + #modpc 0,r4,r4 # enable tracing + + ld _Ttimer_val,r6 # r6 = test timer + + ldconst T1CSR,r4 # r4 = T1 control status reg + stob r4,CTL_PORT # select T1CSR + ldconst RELOAD,r5 # r5 = reset value + stob r5,CTL_PORT # reset countdown + addo 1,r6,r6 + st r6,_Ttimer_val # increment test timer +loop_til_cleared: + clrbit 4,sf0,sf0 + bbs 4,sf0,loop_til_cleared +leaf: ret + + .leafproc _flush_reg, flush_reg.lf + .globl _flush_reg, flush_reg.lf +_flush_reg: + lda leaf,g14 # g14 = exit address +flush_reg.lf: + flushreg + mov g14,g0 # g0 = exit address + ldconst 0,g14 # set g14 for non-leaf + bx (g0) diff --git a/c/src/lib/libbsp/i960/cvme961/timer/timerisr.s b/c/src/lib/libbsp/i960/cvme961/timer/timerisr.s deleted file mode 100644 index edce480326..0000000000 --- a/c/src/lib/libbsp/i960/cvme961/timer/timerisr.s +++ /dev/null @@ -1,65 +0,0 @@ -/* timer_isr() - * - * This routine initializes the Z8536 timer on the SQSIO4 SQUALL - * board for the CVME961 board. The timer is setup to provide a - * tick every 0x10000 / 2 milliseconds. This is used to time - * executing code. - * - * Input parameters: NONE - * - * Output parameters: NONE - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include "asm.h" - -.set PORT_A, 0xc00000a8 # port A -.set PORT_B, 0xc00000a4 # port B -.set PORT_C, 0xc00000a0 # port C -.set CTL_PORT, 0xc00000ac # control port - -.set T1CSR, 0x0a # T1 command/status reg -.set RELOAD, 0x24 # clr IP & IUS,allow countdown - -/* - * Duplicating this symbol is stupid but eliminates - * toolset variation problems. - */ - PUBLIC(timerisr) - PUBLIC(_timerisr) -SYM (timerisr): -SYM (_timerisr): - #ldconst 1,r4 - #modpc 0,r4,r4 # enable tracing - - ld _Ttimer_val,r6 # r6 = test timer - - ldconst T1CSR,r4 # r4 = T1 control status reg - stob r4,CTL_PORT # select T1CSR - ldconst RELOAD,r5 # r5 = reset value - stob r5,CTL_PORT # reset countdown - addo 1,r6,r6 - st r6,_Ttimer_val # increment test timer -loop_til_cleared: - clrbit 4,sf0,sf0 - bbs 4,sf0,loop_til_cleared -leaf: ret - - .leafproc _flush_reg, flush_reg.lf - .globl _flush_reg, flush_reg.lf -_flush_reg: - lda leaf,g14 # g14 = exit address -flush_reg.lf: - flushreg - mov g14,g0 # g0 = exit address - ldconst 0,g14 # set g14 for non-leaf - bx (g0) diff --git a/c/src/lib/libbsp/i960/cvme961/wrapup/Makefile.in b/c/src/lib/libbsp/i960/cvme961/wrapup/Makefile.in index 11ca32d8c7..3ff8a45a12 100644 --- a/c/src/lib/libbsp/i960/cvme961/wrapup/Makefile.in +++ b/c/src/lib/libbsp/i960/cvme961/wrapup/Makefile.in @@ -8,17 +8,22 @@ VPATH = @srcdir@ RTEMS_ROOT = @top_srcdir@ PROJECT_ROOT = @PROJECT_ROOT@ -BSP_PIECES=startup clock console shmsupp timer -GENERIC_PIECES=shmdr +BSP_PIECES=startup clock console timer +GENERIC_PIECES= + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/lib.cfg + +ifeq ($(HAS_MP),yes) +GENERIC_PIECES += shmdr +BSP_PIECES += shmsupp +endif # bummer; have to use $foreach since % pattern subst rules only replace 1x OBJS=$(foreach piece, $(BSP_PIECES), ../$(piece)/$(ARCH)/$(piece).rel) \ $(foreach piece, $(GENERIC_PIECES), ../../../$(piece)/$(ARCH)/$(piece).rel) LIB=$(ARCH)/libbsp.a -include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg -include $(RTEMS_ROOT)/make/lib.cfg - # # (OPTIONAL) Add local stuff here using += # diff --git a/c/src/lib/libbsp/m68k/dmv152/timer/Makefile.in b/c/src/lib/libbsp/m68k/dmv152/timer/Makefile.in index 24809cbed8..21ca9675e7 100644 --- a/c/src/lib/libbsp/m68k/dmv152/timer/Makefile.in +++ b/c/src/lib/libbsp/m68k/dmv152/timer/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=timerisr -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/m68k/dmv152/timer/timerisr.S b/c/src/lib/libbsp/m68k/dmv152/timer/timerisr.S new file mode 100644 index 0000000000..ef0ed8d212 --- /dev/null +++ b/c/src/lib/libbsp/m68k/dmv152/timer/timerisr.S @@ -0,0 +1,38 @@ +/* timer_isr() + * + * This routine provides the ISR for the Z8536 timer on the DMV152 + * board. The timer is set up to generate an interrupt at maximum + * intervals. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include "asm.h" + +BEGIN_CODE + +.set TIMER, 0x0c000007 | port A +.set CT1_CMD_STATUS, 0x0a | command status register +.set RELOAD, 0x26 | clr IP & IUS,allow countdown + + PUBLIC(timerisr) +SYM (timerisr): + movb #CT1_CMD_STATUS,TIMER | set pointer to cmd status reg + movb #RELOAD,TIMER | reload countdown + addql #1, SYM (Ttimer_val) | increment timer value + rte + +END_CODE +END diff --git a/c/src/lib/libbsp/m68k/dmv152/timer/timerisr.s b/c/src/lib/libbsp/m68k/dmv152/timer/timerisr.s deleted file mode 100644 index ef0ed8d212..0000000000 --- a/c/src/lib/libbsp/m68k/dmv152/timer/timerisr.s +++ /dev/null @@ -1,38 +0,0 @@ -/* timer_isr() - * - * This routine provides the ISR for the Z8536 timer on the DMV152 - * board. The timer is set up to generate an interrupt at maximum - * intervals. - * - * Input parameters: NONE - * - * Output parameters: NONE - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include "asm.h" - -BEGIN_CODE - -.set TIMER, 0x0c000007 | port A -.set CT1_CMD_STATUS, 0x0a | command status register -.set RELOAD, 0x26 | clr IP & IUS,allow countdown - - PUBLIC(timerisr) -SYM (timerisr): - movb #CT1_CMD_STATUS,TIMER | set pointer to cmd status reg - movb #RELOAD,TIMER | reload countdown - addql #1, SYM (Ttimer_val) | increment timer value - rte - -END_CODE -END diff --git a/c/src/lib/libbsp/m68k/gen68302/start/Makefile.in b/c/src/lib/libbsp/m68k/gen68302/start/Makefile.in index d96348b19d..b89be869e6 100644 --- a/c/src/lib/libbsp/m68k/gen68302/start/Makefile.in +++ b/c/src/lib/libbsp/m68k/gen68302/start/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=start302 -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/m68k/gen68302/start/start.S b/c/src/lib/libbsp/m68k/gen68302/start/start.S new file mode 100644 index 0000000000..2a7c652c87 --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68302/start/start.S @@ -0,0 +1,267 @@ +/* entry.s + * + * This file contains the entry point for the application. + * The name of this entry point is compiler dependent. + * It jumps to the BSP which is responsible for performing + * all initialization. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include "asm.h" + + .set BAR, 0xF2 | Base Address Register location + .set SCR, 0xF4 | System Control Register location + .set BAR_VAL, 0x0f7f | BAR value + .set SCR_VAL, 0x00080f00 | SCR value + .set GIMR_VAL, 0x8780 |Global Interrupt Mode Register. (MUST BE WRITTEN). + .set BaseAddr,(BAR_VAL&0x0fff)<<12 | MC68302 internal base address + + .set oSYSRAM, 0x000 | 576 bytes of internal system RAM + + .set oGIMR, 0x812 + + .set oCS0_Base, 0x830 | 16 bits, Chip Sel 0 Base Reg + .set oCS0_Option, 0x832 | 16 bits, Chip Sel 0 Option Reg + .set oCS1_Base, 0x834 | 16 bits, Chip Sel 1 Base Reg + .set oCS1_Option, 0x836 | 16 bits, Chip Sel 1 Option Reg + .set oCS2_Base, 0x838 | 16 bits, Chip Sel 2 Base Reg + .set oCS2_Option, 0x83a | 16 bits, Chip Sel 2 Option Reg + .set oCS3_Base, 0x83c | 16 bits, Chip Sel 3 Base Reg + .set oCS3_Option, 0x83e | 16 bits, Chip Sel 3 Option Reg + + .set tmpSRAM_BASE, 0x400000 | start of temporary SRAM + .set FLASH_BASE, 0xc00000 | start of FLASH''s normal location + + +BEGIN_CODE + PUBLIC (M68Kvec) | Vector Table +SYM (M68Kvec): | standard location for vectors +V___ISSP: .long 0x00001000 |00 0 Reset: Initial SSP +V____IPC: .long SYM(start)-V___ISSP |04 1 Reset: Initial PC +V_BUSERR: .long Bad-V___ISSP |08 2 Bus Error +V_ADRERR: .long Bad-V___ISSP |0c 3 Address Error + .space 240 | reserve space for reset of vectors + +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) +SYM (lowintstack): + .space 4092 | reserve for interrupt stack +SYM (hiintstack): + .space 4 | end of interrupt stack +#endif + + PUBLIC (start) | Default entry point for GNU +SYM (start): + move.w #0x2700,sr | Disable all interrupts + move.w #BAR_VAL,BAR | Set Base Address Register + move.l #SCR_VAL,SCR | Set System Control Register + lea BaseAddr,a5 + move.w #GIMR_VAL,a5@(oGIMR) | Set Global Interrupt Mode Register + +| +| Set up chip select registers for the remapping process. +| + +| +| 0 X x x x x +| 0 000 0 0-- - --- ---- ---- ---- +| x xxx x xxx x xx +| + move.w #0xc001,a5@(oCS0_Base) | Expand CS0 to full size (FLASH) + move.w #0x1f82,a5@(oCS0_Option) | 000000-03ffff, R, 0 WS + +| +| X x x x x x +| 0 100 0 0-- - --- ---- ---- ---- +| x xxx x xxx x xx +| + move.w #0xa801,a5@(oCS1_Base) | Set up and enable CS1 (SRAM) + move.w #0x1f80,a5@(oCS1_Option) | 400000-43ffff, RW, 0 WS + +| +| Copy the initial boot FLASH area to the temporary SRAM location. +| + moveq #0,d0 + movea.l d0,a0 | a0 -> start of FLASH + lea tmpSRAM_BASE,a1 | a1 -> start of tmp SRAM +| moveq #(endPreBoot-V___ISSP)/4,d0 | # longs to copy + moveq #127,d0 +cpy_flash: move.l (a0)+,(a1)+ | copy + subq.l #1,d0 + bne cpy_flash + +| +| Copy remap code to 68302''s internal system RAM. +| + movea.w #begRemap-V___ISSP,a0 | a0 -> remap code + lea a5@(oSYSRAM),a1 | a1 -> internal system RAM +| moveq #(endRemap-begRemap)/2-1,d0 | d0 = # words to copy + moveq #11,d0 +cpy_remap: move.w (a0)+,(a1)+ | copy + dbra d0,cpy_remap + +| +| Jump to the remap code in the 68302''s internal system RAM. +| + jmp a5@(oSYSRAM) | (effectively a jmp begRemap) + +| +| This remap code, when executed from the 68302''s internal system RAM +| will 1) remap CS1 so that SRAM is at 0 +| 2) remap CS0 so that FLASH is at FLASH_BASE +| and 3) jump to executable code in the remapped FLASH. +| +begRemap: move.w #0xa001,a5@(oCS1_Base) | Move CS1 (SRAM) + move.w #0xd801,a5@(oCS0_Base) | Move CS0 (FLASH) + lea FLASH_BASE,a0 + jmp a0@(endRemap-V___ISSP.w) | Jump back to FLASH +endRemap: +| +| Now set up the remaining chip select registers. +| + +| +| 4 0 x x x x +| 1 000 1 111 0 000 0--- ---- ---- +| x xxx x xxx x xx +| + move.w #0xb1e1,a5@(oCS2_Base) | Set up and enable CS2 (dpRAM) + move.w #0x1ff0,a5@(oCS2_Option) | 8f0000-8f07ff, RW, 0 WS + +| +| 8 X x x x x +| 1 000 0 0-- - --- ---- ---- ---- +| x xxx x xxx x xx +| + move.w #0xd001,a5@(oCS3_Base) | Set up and enable CS3 (IO) + move.w #0x1f80,a5@(oCS3_Option) | 800000-83ffff, RW, 0 WS + +endPreBoot: + + move.b #0x30,0x800001 | set status LED amber + + .set oPIOB_Ctrl, 0x824 + .set oPIOB_DDR, 0x826 + .set oPIOB_Data, 0x828 + + .set oPIOA_Ctrl, 0x81e + .set oPIOA_DDR, 0x820 + .set oPIOA_Data, 0x822 + + move.w #0x0ff8,a5@(oPIOB_Data) | Make output follow resistors. + move.w #0x00ff,a5@(oPIOB_DDR) | Set up PB7-PB0 for output. + move.w #0x0080,a5@(oPIOB_Ctrl) | Set up WDOG* as dedicated + | peripheral pins. + + move.w #0x1fff,a5@(oPIOA_Data) | Make output follow resistors. + move.w #0xea2a,a5@(oPIOA_DDR) | Set up PA15-PA0 for in/output. + move.w #0x0003,a5@(oPIOA_Ctrl) | Set up TXD2/RXD2 as dedicated + | peripheral pins. + +| +| Place "Bad" in all vectors from 010 thru 0ec. Vectors 0f0 and 0f4 +| are not set because they are the 68302''s BAR and SCR. +| + movea.w #0x010,a0 + moveq #(0x0f0-0x010)/4-1,d0 + move.l #Bad,d1 +cpy_Bad: move.l d1,(a0)+ + dbra d0,cpy_Bad + + .set vbase, 0x0200 + + lea vbase,a0 + moveq #31,d0 +cpy_Bad1: move.l d1,(a0)+ + dbra d0,cpy_Bad1 + +| +| Fill in special locations to configure OS +| + move.l #Bad,0x008 | Bus Error + move.l #Bad,0x00c | Address Error + move.l #Bad,0x024 | Trace +| move.l #KE_IRET,$0b4 | pSOS+ RET_I Call + +| move.l #_cnsl_isr,vbase+0x028 | SCC2 + move.l #timerisr,vbase+0x018 | Timer ISR + + | + | zero out uninitialized data area + | +zerobss: + moveal # SYM (end),a0 | find end of .bss + moveal # SYM (bss_start),a1 | find beginning of .bss + moveq #0,d0 + +loop: movel d0,a1@+ | to zero out uninitialized + cmpal a0,a1 + jlt loop | loop until _end reached + + movel # SYM (end),d0 | d0 = end of bss/start of heap + addl # SYM (heap_size),d0 | d0 = end of heap + movel d0, SYM (stack_start) | Save for brk() routine + addl # SYM (stack_size),d0 | make room for stack + andl #0xffffffc0,d0 | align it on 16 byte boundary + movw #0x3700,sr | SUPV MODE,INTERRUPTS OFF!!! + movel d0,a7 | set master stack pointer + movel d0,a6 | set base pointer + + /* + * RTEMS should maintain a separate interrupt stack on CPUs + * without one in hardware. This is currently not supported + * on versions of the m68k without a HW intr stack. + */ + +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) + lea SYM (hiintstack),a0 | a0 = high end of intr stack + movec a0,isp | set interrupt stack +#endif + + move.l #0,a7@- | environp + move.l #0,a7@- | argv + move.l #0,a7@- | argc + jsr SYM (boot_card) + + nop +Bad: bra Bad + + nop +END_CODE + + +BEGIN_DATA + + PUBLIC (start_frame) +SYM (start_frame): + .space 4,0 + + PUBLIC (stack_start) +SYM (stack_start): + .space 4,0 +END_DATA + +BEGIN_BSS + + PUBLIC (environ) + .align 2 +SYM (environ): + .long 0 + + PUBLIC (heap_size) + .set SYM (heap_size),0x2000 + + PUBLIC (stack_size) + .set SYM (stack_size),0x1000 + + +END_DATA +END diff --git a/c/src/lib/libbsp/m68k/gen68302/start/start302.s b/c/src/lib/libbsp/m68k/gen68302/start/start302.s deleted file mode 100644 index 2a7c652c87..0000000000 --- a/c/src/lib/libbsp/m68k/gen68302/start/start302.s +++ /dev/null @@ -1,267 +0,0 @@ -/* entry.s - * - * This file contains the entry point for the application. - * The name of this entry point is compiler dependent. - * It jumps to the BSP which is responsible for performing - * all initialization. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include "asm.h" - - .set BAR, 0xF2 | Base Address Register location - .set SCR, 0xF4 | System Control Register location - .set BAR_VAL, 0x0f7f | BAR value - .set SCR_VAL, 0x00080f00 | SCR value - .set GIMR_VAL, 0x8780 |Global Interrupt Mode Register. (MUST BE WRITTEN). - .set BaseAddr,(BAR_VAL&0x0fff)<<12 | MC68302 internal base address - - .set oSYSRAM, 0x000 | 576 bytes of internal system RAM - - .set oGIMR, 0x812 - - .set oCS0_Base, 0x830 | 16 bits, Chip Sel 0 Base Reg - .set oCS0_Option, 0x832 | 16 bits, Chip Sel 0 Option Reg - .set oCS1_Base, 0x834 | 16 bits, Chip Sel 1 Base Reg - .set oCS1_Option, 0x836 | 16 bits, Chip Sel 1 Option Reg - .set oCS2_Base, 0x838 | 16 bits, Chip Sel 2 Base Reg - .set oCS2_Option, 0x83a | 16 bits, Chip Sel 2 Option Reg - .set oCS3_Base, 0x83c | 16 bits, Chip Sel 3 Base Reg - .set oCS3_Option, 0x83e | 16 bits, Chip Sel 3 Option Reg - - .set tmpSRAM_BASE, 0x400000 | start of temporary SRAM - .set FLASH_BASE, 0xc00000 | start of FLASH''s normal location - - -BEGIN_CODE - PUBLIC (M68Kvec) | Vector Table -SYM (M68Kvec): | standard location for vectors -V___ISSP: .long 0x00001000 |00 0 Reset: Initial SSP -V____IPC: .long SYM(start)-V___ISSP |04 1 Reset: Initial PC -V_BUSERR: .long Bad-V___ISSP |08 2 Bus Error -V_ADRERR: .long Bad-V___ISSP |0c 3 Address Error - .space 240 | reserve space for reset of vectors - -#if ( M68K_HAS_SEPARATE_STACKS == 1 ) -SYM (lowintstack): - .space 4092 | reserve for interrupt stack -SYM (hiintstack): - .space 4 | end of interrupt stack -#endif - - PUBLIC (start) | Default entry point for GNU -SYM (start): - move.w #0x2700,sr | Disable all interrupts - move.w #BAR_VAL,BAR | Set Base Address Register - move.l #SCR_VAL,SCR | Set System Control Register - lea BaseAddr,a5 - move.w #GIMR_VAL,a5@(oGIMR) | Set Global Interrupt Mode Register - -| -| Set up chip select registers for the remapping process. -| - -| -| 0 X x x x x -| 0 000 0 0-- - --- ---- ---- ---- -| x xxx x xxx x xx -| - move.w #0xc001,a5@(oCS0_Base) | Expand CS0 to full size (FLASH) - move.w #0x1f82,a5@(oCS0_Option) | 000000-03ffff, R, 0 WS - -| -| X x x x x x -| 0 100 0 0-- - --- ---- ---- ---- -| x xxx x xxx x xx -| - move.w #0xa801,a5@(oCS1_Base) | Set up and enable CS1 (SRAM) - move.w #0x1f80,a5@(oCS1_Option) | 400000-43ffff, RW, 0 WS - -| -| Copy the initial boot FLASH area to the temporary SRAM location. -| - moveq #0,d0 - movea.l d0,a0 | a0 -> start of FLASH - lea tmpSRAM_BASE,a1 | a1 -> start of tmp SRAM -| moveq #(endPreBoot-V___ISSP)/4,d0 | # longs to copy - moveq #127,d0 -cpy_flash: move.l (a0)+,(a1)+ | copy - subq.l #1,d0 - bne cpy_flash - -| -| Copy remap code to 68302''s internal system RAM. -| - movea.w #begRemap-V___ISSP,a0 | a0 -> remap code - lea a5@(oSYSRAM),a1 | a1 -> internal system RAM -| moveq #(endRemap-begRemap)/2-1,d0 | d0 = # words to copy - moveq #11,d0 -cpy_remap: move.w (a0)+,(a1)+ | copy - dbra d0,cpy_remap - -| -| Jump to the remap code in the 68302''s internal system RAM. -| - jmp a5@(oSYSRAM) | (effectively a jmp begRemap) - -| -| This remap code, when executed from the 68302''s internal system RAM -| will 1) remap CS1 so that SRAM is at 0 -| 2) remap CS0 so that FLASH is at FLASH_BASE -| and 3) jump to executable code in the remapped FLASH. -| -begRemap: move.w #0xa001,a5@(oCS1_Base) | Move CS1 (SRAM) - move.w #0xd801,a5@(oCS0_Base) | Move CS0 (FLASH) - lea FLASH_BASE,a0 - jmp a0@(endRemap-V___ISSP.w) | Jump back to FLASH -endRemap: -| -| Now set up the remaining chip select registers. -| - -| -| 4 0 x x x x -| 1 000 1 111 0 000 0--- ---- ---- -| x xxx x xxx x xx -| - move.w #0xb1e1,a5@(oCS2_Base) | Set up and enable CS2 (dpRAM) - move.w #0x1ff0,a5@(oCS2_Option) | 8f0000-8f07ff, RW, 0 WS - -| -| 8 X x x x x -| 1 000 0 0-- - --- ---- ---- ---- -| x xxx x xxx x xx -| - move.w #0xd001,a5@(oCS3_Base) | Set up and enable CS3 (IO) - move.w #0x1f80,a5@(oCS3_Option) | 800000-83ffff, RW, 0 WS - -endPreBoot: - - move.b #0x30,0x800001 | set status LED amber - - .set oPIOB_Ctrl, 0x824 - .set oPIOB_DDR, 0x826 - .set oPIOB_Data, 0x828 - - .set oPIOA_Ctrl, 0x81e - .set oPIOA_DDR, 0x820 - .set oPIOA_Data, 0x822 - - move.w #0x0ff8,a5@(oPIOB_Data) | Make output follow resistors. - move.w #0x00ff,a5@(oPIOB_DDR) | Set up PB7-PB0 for output. - move.w #0x0080,a5@(oPIOB_Ctrl) | Set up WDOG* as dedicated - | peripheral pins. - - move.w #0x1fff,a5@(oPIOA_Data) | Make output follow resistors. - move.w #0xea2a,a5@(oPIOA_DDR) | Set up PA15-PA0 for in/output. - move.w #0x0003,a5@(oPIOA_Ctrl) | Set up TXD2/RXD2 as dedicated - | peripheral pins. - -| -| Place "Bad" in all vectors from 010 thru 0ec. Vectors 0f0 and 0f4 -| are not set because they are the 68302''s BAR and SCR. -| - movea.w #0x010,a0 - moveq #(0x0f0-0x010)/4-1,d0 - move.l #Bad,d1 -cpy_Bad: move.l d1,(a0)+ - dbra d0,cpy_Bad - - .set vbase, 0x0200 - - lea vbase,a0 - moveq #31,d0 -cpy_Bad1: move.l d1,(a0)+ - dbra d0,cpy_Bad1 - -| -| Fill in special locations to configure OS -| - move.l #Bad,0x008 | Bus Error - move.l #Bad,0x00c | Address Error - move.l #Bad,0x024 | Trace -| move.l #KE_IRET,$0b4 | pSOS+ RET_I Call - -| move.l #_cnsl_isr,vbase+0x028 | SCC2 - move.l #timerisr,vbase+0x018 | Timer ISR - - | - | zero out uninitialized data area - | -zerobss: - moveal # SYM (end),a0 | find end of .bss - moveal # SYM (bss_start),a1 | find beginning of .bss - moveq #0,d0 - -loop: movel d0,a1@+ | to zero out uninitialized - cmpal a0,a1 - jlt loop | loop until _end reached - - movel # SYM (end),d0 | d0 = end of bss/start of heap - addl # SYM (heap_size),d0 | d0 = end of heap - movel d0, SYM (stack_start) | Save for brk() routine - addl # SYM (stack_size),d0 | make room for stack - andl #0xffffffc0,d0 | align it on 16 byte boundary - movw #0x3700,sr | SUPV MODE,INTERRUPTS OFF!!! - movel d0,a7 | set master stack pointer - movel d0,a6 | set base pointer - - /* - * RTEMS should maintain a separate interrupt stack on CPUs - * without one in hardware. This is currently not supported - * on versions of the m68k without a HW intr stack. - */ - -#if ( M68K_HAS_SEPARATE_STACKS == 1 ) - lea SYM (hiintstack),a0 | a0 = high end of intr stack - movec a0,isp | set interrupt stack -#endif - - move.l #0,a7@- | environp - move.l #0,a7@- | argv - move.l #0,a7@- | argc - jsr SYM (boot_card) - - nop -Bad: bra Bad - - nop -END_CODE - - -BEGIN_DATA - - PUBLIC (start_frame) -SYM (start_frame): - .space 4,0 - - PUBLIC (stack_start) -SYM (stack_start): - .space 4,0 -END_DATA - -BEGIN_BSS - - PUBLIC (environ) - .align 2 -SYM (environ): - .long 0 - - PUBLIC (heap_size) - .set SYM (heap_size),0x2000 - - PUBLIC (stack_size) - .set SYM (stack_size),0x1000 - - -END_DATA -END diff --git a/c/src/lib/libbsp/m68k/gen68302/start302/Makefile.in b/c/src/lib/libbsp/m68k/gen68302/start302/Makefile.in index d96348b19d..b89be869e6 100644 --- a/c/src/lib/libbsp/m68k/gen68302/start302/Makefile.in +++ b/c/src/lib/libbsp/m68k/gen68302/start302/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=start302 -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/m68k/gen68302/start302/start302.S b/c/src/lib/libbsp/m68k/gen68302/start302/start302.S new file mode 100644 index 0000000000..2a7c652c87 --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68302/start302/start302.S @@ -0,0 +1,267 @@ +/* entry.s + * + * This file contains the entry point for the application. + * The name of this entry point is compiler dependent. + * It jumps to the BSP which is responsible for performing + * all initialization. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include "asm.h" + + .set BAR, 0xF2 | Base Address Register location + .set SCR, 0xF4 | System Control Register location + .set BAR_VAL, 0x0f7f | BAR value + .set SCR_VAL, 0x00080f00 | SCR value + .set GIMR_VAL, 0x8780 |Global Interrupt Mode Register. (MUST BE WRITTEN). + .set BaseAddr,(BAR_VAL&0x0fff)<<12 | MC68302 internal base address + + .set oSYSRAM, 0x000 | 576 bytes of internal system RAM + + .set oGIMR, 0x812 + + .set oCS0_Base, 0x830 | 16 bits, Chip Sel 0 Base Reg + .set oCS0_Option, 0x832 | 16 bits, Chip Sel 0 Option Reg + .set oCS1_Base, 0x834 | 16 bits, Chip Sel 1 Base Reg + .set oCS1_Option, 0x836 | 16 bits, Chip Sel 1 Option Reg + .set oCS2_Base, 0x838 | 16 bits, Chip Sel 2 Base Reg + .set oCS2_Option, 0x83a | 16 bits, Chip Sel 2 Option Reg + .set oCS3_Base, 0x83c | 16 bits, Chip Sel 3 Base Reg + .set oCS3_Option, 0x83e | 16 bits, Chip Sel 3 Option Reg + + .set tmpSRAM_BASE, 0x400000 | start of temporary SRAM + .set FLASH_BASE, 0xc00000 | start of FLASH''s normal location + + +BEGIN_CODE + PUBLIC (M68Kvec) | Vector Table +SYM (M68Kvec): | standard location for vectors +V___ISSP: .long 0x00001000 |00 0 Reset: Initial SSP +V____IPC: .long SYM(start)-V___ISSP |04 1 Reset: Initial PC +V_BUSERR: .long Bad-V___ISSP |08 2 Bus Error +V_ADRERR: .long Bad-V___ISSP |0c 3 Address Error + .space 240 | reserve space for reset of vectors + +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) +SYM (lowintstack): + .space 4092 | reserve for interrupt stack +SYM (hiintstack): + .space 4 | end of interrupt stack +#endif + + PUBLIC (start) | Default entry point for GNU +SYM (start): + move.w #0x2700,sr | Disable all interrupts + move.w #BAR_VAL,BAR | Set Base Address Register + move.l #SCR_VAL,SCR | Set System Control Register + lea BaseAddr,a5 + move.w #GIMR_VAL,a5@(oGIMR) | Set Global Interrupt Mode Register + +| +| Set up chip select registers for the remapping process. +| + +| +| 0 X x x x x +| 0 000 0 0-- - --- ---- ---- ---- +| x xxx x xxx x xx +| + move.w #0xc001,a5@(oCS0_Base) | Expand CS0 to full size (FLASH) + move.w #0x1f82,a5@(oCS0_Option) | 000000-03ffff, R, 0 WS + +| +| X x x x x x +| 0 100 0 0-- - --- ---- ---- ---- +| x xxx x xxx x xx +| + move.w #0xa801,a5@(oCS1_Base) | Set up and enable CS1 (SRAM) + move.w #0x1f80,a5@(oCS1_Option) | 400000-43ffff, RW, 0 WS + +| +| Copy the initial boot FLASH area to the temporary SRAM location. +| + moveq #0,d0 + movea.l d0,a0 | a0 -> start of FLASH + lea tmpSRAM_BASE,a1 | a1 -> start of tmp SRAM +| moveq #(endPreBoot-V___ISSP)/4,d0 | # longs to copy + moveq #127,d0 +cpy_flash: move.l (a0)+,(a1)+ | copy + subq.l #1,d0 + bne cpy_flash + +| +| Copy remap code to 68302''s internal system RAM. +| + movea.w #begRemap-V___ISSP,a0 | a0 -> remap code + lea a5@(oSYSRAM),a1 | a1 -> internal system RAM +| moveq #(endRemap-begRemap)/2-1,d0 | d0 = # words to copy + moveq #11,d0 +cpy_remap: move.w (a0)+,(a1)+ | copy + dbra d0,cpy_remap + +| +| Jump to the remap code in the 68302''s internal system RAM. +| + jmp a5@(oSYSRAM) | (effectively a jmp begRemap) + +| +| This remap code, when executed from the 68302''s internal system RAM +| will 1) remap CS1 so that SRAM is at 0 +| 2) remap CS0 so that FLASH is at FLASH_BASE +| and 3) jump to executable code in the remapped FLASH. +| +begRemap: move.w #0xa001,a5@(oCS1_Base) | Move CS1 (SRAM) + move.w #0xd801,a5@(oCS0_Base) | Move CS0 (FLASH) + lea FLASH_BASE,a0 + jmp a0@(endRemap-V___ISSP.w) | Jump back to FLASH +endRemap: +| +| Now set up the remaining chip select registers. +| + +| +| 4 0 x x x x +| 1 000 1 111 0 000 0--- ---- ---- +| x xxx x xxx x xx +| + move.w #0xb1e1,a5@(oCS2_Base) | Set up and enable CS2 (dpRAM) + move.w #0x1ff0,a5@(oCS2_Option) | 8f0000-8f07ff, RW, 0 WS + +| +| 8 X x x x x +| 1 000 0 0-- - --- ---- ---- ---- +| x xxx x xxx x xx +| + move.w #0xd001,a5@(oCS3_Base) | Set up and enable CS3 (IO) + move.w #0x1f80,a5@(oCS3_Option) | 800000-83ffff, RW, 0 WS + +endPreBoot: + + move.b #0x30,0x800001 | set status LED amber + + .set oPIOB_Ctrl, 0x824 + .set oPIOB_DDR, 0x826 + .set oPIOB_Data, 0x828 + + .set oPIOA_Ctrl, 0x81e + .set oPIOA_DDR, 0x820 + .set oPIOA_Data, 0x822 + + move.w #0x0ff8,a5@(oPIOB_Data) | Make output follow resistors. + move.w #0x00ff,a5@(oPIOB_DDR) | Set up PB7-PB0 for output. + move.w #0x0080,a5@(oPIOB_Ctrl) | Set up WDOG* as dedicated + | peripheral pins. + + move.w #0x1fff,a5@(oPIOA_Data) | Make output follow resistors. + move.w #0xea2a,a5@(oPIOA_DDR) | Set up PA15-PA0 for in/output. + move.w #0x0003,a5@(oPIOA_Ctrl) | Set up TXD2/RXD2 as dedicated + | peripheral pins. + +| +| Place "Bad" in all vectors from 010 thru 0ec. Vectors 0f0 and 0f4 +| are not set because they are the 68302''s BAR and SCR. +| + movea.w #0x010,a0 + moveq #(0x0f0-0x010)/4-1,d0 + move.l #Bad,d1 +cpy_Bad: move.l d1,(a0)+ + dbra d0,cpy_Bad + + .set vbase, 0x0200 + + lea vbase,a0 + moveq #31,d0 +cpy_Bad1: move.l d1,(a0)+ + dbra d0,cpy_Bad1 + +| +| Fill in special locations to configure OS +| + move.l #Bad,0x008 | Bus Error + move.l #Bad,0x00c | Address Error + move.l #Bad,0x024 | Trace +| move.l #KE_IRET,$0b4 | pSOS+ RET_I Call + +| move.l #_cnsl_isr,vbase+0x028 | SCC2 + move.l #timerisr,vbase+0x018 | Timer ISR + + | + | zero out uninitialized data area + | +zerobss: + moveal # SYM (end),a0 | find end of .bss + moveal # SYM (bss_start),a1 | find beginning of .bss + moveq #0,d0 + +loop: movel d0,a1@+ | to zero out uninitialized + cmpal a0,a1 + jlt loop | loop until _end reached + + movel # SYM (end),d0 | d0 = end of bss/start of heap + addl # SYM (heap_size),d0 | d0 = end of heap + movel d0, SYM (stack_start) | Save for brk() routine + addl # SYM (stack_size),d0 | make room for stack + andl #0xffffffc0,d0 | align it on 16 byte boundary + movw #0x3700,sr | SUPV MODE,INTERRUPTS OFF!!! + movel d0,a7 | set master stack pointer + movel d0,a6 | set base pointer + + /* + * RTEMS should maintain a separate interrupt stack on CPUs + * without one in hardware. This is currently not supported + * on versions of the m68k without a HW intr stack. + */ + +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) + lea SYM (hiintstack),a0 | a0 = high end of intr stack + movec a0,isp | set interrupt stack +#endif + + move.l #0,a7@- | environp + move.l #0,a7@- | argv + move.l #0,a7@- | argc + jsr SYM (boot_card) + + nop +Bad: bra Bad + + nop +END_CODE + + +BEGIN_DATA + + PUBLIC (start_frame) +SYM (start_frame): + .space 4,0 + + PUBLIC (stack_start) +SYM (stack_start): + .space 4,0 +END_DATA + +BEGIN_BSS + + PUBLIC (environ) + .align 2 +SYM (environ): + .long 0 + + PUBLIC (heap_size) + .set SYM (heap_size),0x2000 + + PUBLIC (stack_size) + .set SYM (stack_size),0x1000 + + +END_DATA +END diff --git a/c/src/lib/libbsp/m68k/gen68302/start302/start302.s b/c/src/lib/libbsp/m68k/gen68302/start302/start302.s deleted file mode 100644 index 2a7c652c87..0000000000 --- a/c/src/lib/libbsp/m68k/gen68302/start302/start302.s +++ /dev/null @@ -1,267 +0,0 @@ -/* entry.s - * - * This file contains the entry point for the application. - * The name of this entry point is compiler dependent. - * It jumps to the BSP which is responsible for performing - * all initialization. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include "asm.h" - - .set BAR, 0xF2 | Base Address Register location - .set SCR, 0xF4 | System Control Register location - .set BAR_VAL, 0x0f7f | BAR value - .set SCR_VAL, 0x00080f00 | SCR value - .set GIMR_VAL, 0x8780 |Global Interrupt Mode Register. (MUST BE WRITTEN). - .set BaseAddr,(BAR_VAL&0x0fff)<<12 | MC68302 internal base address - - .set oSYSRAM, 0x000 | 576 bytes of internal system RAM - - .set oGIMR, 0x812 - - .set oCS0_Base, 0x830 | 16 bits, Chip Sel 0 Base Reg - .set oCS0_Option, 0x832 | 16 bits, Chip Sel 0 Option Reg - .set oCS1_Base, 0x834 | 16 bits, Chip Sel 1 Base Reg - .set oCS1_Option, 0x836 | 16 bits, Chip Sel 1 Option Reg - .set oCS2_Base, 0x838 | 16 bits, Chip Sel 2 Base Reg - .set oCS2_Option, 0x83a | 16 bits, Chip Sel 2 Option Reg - .set oCS3_Base, 0x83c | 16 bits, Chip Sel 3 Base Reg - .set oCS3_Option, 0x83e | 16 bits, Chip Sel 3 Option Reg - - .set tmpSRAM_BASE, 0x400000 | start of temporary SRAM - .set FLASH_BASE, 0xc00000 | start of FLASH''s normal location - - -BEGIN_CODE - PUBLIC (M68Kvec) | Vector Table -SYM (M68Kvec): | standard location for vectors -V___ISSP: .long 0x00001000 |00 0 Reset: Initial SSP -V____IPC: .long SYM(start)-V___ISSP |04 1 Reset: Initial PC -V_BUSERR: .long Bad-V___ISSP |08 2 Bus Error -V_ADRERR: .long Bad-V___ISSP |0c 3 Address Error - .space 240 | reserve space for reset of vectors - -#if ( M68K_HAS_SEPARATE_STACKS == 1 ) -SYM (lowintstack): - .space 4092 | reserve for interrupt stack -SYM (hiintstack): - .space 4 | end of interrupt stack -#endif - - PUBLIC (start) | Default entry point for GNU -SYM (start): - move.w #0x2700,sr | Disable all interrupts - move.w #BAR_VAL,BAR | Set Base Address Register - move.l #SCR_VAL,SCR | Set System Control Register - lea BaseAddr,a5 - move.w #GIMR_VAL,a5@(oGIMR) | Set Global Interrupt Mode Register - -| -| Set up chip select registers for the remapping process. -| - -| -| 0 X x x x x -| 0 000 0 0-- - --- ---- ---- ---- -| x xxx x xxx x xx -| - move.w #0xc001,a5@(oCS0_Base) | Expand CS0 to full size (FLASH) - move.w #0x1f82,a5@(oCS0_Option) | 000000-03ffff, R, 0 WS - -| -| X x x x x x -| 0 100 0 0-- - --- ---- ---- ---- -| x xxx x xxx x xx -| - move.w #0xa801,a5@(oCS1_Base) | Set up and enable CS1 (SRAM) - move.w #0x1f80,a5@(oCS1_Option) | 400000-43ffff, RW, 0 WS - -| -| Copy the initial boot FLASH area to the temporary SRAM location. -| - moveq #0,d0 - movea.l d0,a0 | a0 -> start of FLASH - lea tmpSRAM_BASE,a1 | a1 -> start of tmp SRAM -| moveq #(endPreBoot-V___ISSP)/4,d0 | # longs to copy - moveq #127,d0 -cpy_flash: move.l (a0)+,(a1)+ | copy - subq.l #1,d0 - bne cpy_flash - -| -| Copy remap code to 68302''s internal system RAM. -| - movea.w #begRemap-V___ISSP,a0 | a0 -> remap code - lea a5@(oSYSRAM),a1 | a1 -> internal system RAM -| moveq #(endRemap-begRemap)/2-1,d0 | d0 = # words to copy - moveq #11,d0 -cpy_remap: move.w (a0)+,(a1)+ | copy - dbra d0,cpy_remap - -| -| Jump to the remap code in the 68302''s internal system RAM. -| - jmp a5@(oSYSRAM) | (effectively a jmp begRemap) - -| -| This remap code, when executed from the 68302''s internal system RAM -| will 1) remap CS1 so that SRAM is at 0 -| 2) remap CS0 so that FLASH is at FLASH_BASE -| and 3) jump to executable code in the remapped FLASH. -| -begRemap: move.w #0xa001,a5@(oCS1_Base) | Move CS1 (SRAM) - move.w #0xd801,a5@(oCS0_Base) | Move CS0 (FLASH) - lea FLASH_BASE,a0 - jmp a0@(endRemap-V___ISSP.w) | Jump back to FLASH -endRemap: -| -| Now set up the remaining chip select registers. -| - -| -| 4 0 x x x x -| 1 000 1 111 0 000 0--- ---- ---- -| x xxx x xxx x xx -| - move.w #0xb1e1,a5@(oCS2_Base) | Set up and enable CS2 (dpRAM) - move.w #0x1ff0,a5@(oCS2_Option) | 8f0000-8f07ff, RW, 0 WS - -| -| 8 X x x x x -| 1 000 0 0-- - --- ---- ---- ---- -| x xxx x xxx x xx -| - move.w #0xd001,a5@(oCS3_Base) | Set up and enable CS3 (IO) - move.w #0x1f80,a5@(oCS3_Option) | 800000-83ffff, RW, 0 WS - -endPreBoot: - - move.b #0x30,0x800001 | set status LED amber - - .set oPIOB_Ctrl, 0x824 - .set oPIOB_DDR, 0x826 - .set oPIOB_Data, 0x828 - - .set oPIOA_Ctrl, 0x81e - .set oPIOA_DDR, 0x820 - .set oPIOA_Data, 0x822 - - move.w #0x0ff8,a5@(oPIOB_Data) | Make output follow resistors. - move.w #0x00ff,a5@(oPIOB_DDR) | Set up PB7-PB0 for output. - move.w #0x0080,a5@(oPIOB_Ctrl) | Set up WDOG* as dedicated - | peripheral pins. - - move.w #0x1fff,a5@(oPIOA_Data) | Make output follow resistors. - move.w #0xea2a,a5@(oPIOA_DDR) | Set up PA15-PA0 for in/output. - move.w #0x0003,a5@(oPIOA_Ctrl) | Set up TXD2/RXD2 as dedicated - | peripheral pins. - -| -| Place "Bad" in all vectors from 010 thru 0ec. Vectors 0f0 and 0f4 -| are not set because they are the 68302''s BAR and SCR. -| - movea.w #0x010,a0 - moveq #(0x0f0-0x010)/4-1,d0 - move.l #Bad,d1 -cpy_Bad: move.l d1,(a0)+ - dbra d0,cpy_Bad - - .set vbase, 0x0200 - - lea vbase,a0 - moveq #31,d0 -cpy_Bad1: move.l d1,(a0)+ - dbra d0,cpy_Bad1 - -| -| Fill in special locations to configure OS -| - move.l #Bad,0x008 | Bus Error - move.l #Bad,0x00c | Address Error - move.l #Bad,0x024 | Trace -| move.l #KE_IRET,$0b4 | pSOS+ RET_I Call - -| move.l #_cnsl_isr,vbase+0x028 | SCC2 - move.l #timerisr,vbase+0x018 | Timer ISR - - | - | zero out uninitialized data area - | -zerobss: - moveal # SYM (end),a0 | find end of .bss - moveal # SYM (bss_start),a1 | find beginning of .bss - moveq #0,d0 - -loop: movel d0,a1@+ | to zero out uninitialized - cmpal a0,a1 - jlt loop | loop until _end reached - - movel # SYM (end),d0 | d0 = end of bss/start of heap - addl # SYM (heap_size),d0 | d0 = end of heap - movel d0, SYM (stack_start) | Save for brk() routine - addl # SYM (stack_size),d0 | make room for stack - andl #0xffffffc0,d0 | align it on 16 byte boundary - movw #0x3700,sr | SUPV MODE,INTERRUPTS OFF!!! - movel d0,a7 | set master stack pointer - movel d0,a6 | set base pointer - - /* - * RTEMS should maintain a separate interrupt stack on CPUs - * without one in hardware. This is currently not supported - * on versions of the m68k without a HW intr stack. - */ - -#if ( M68K_HAS_SEPARATE_STACKS == 1 ) - lea SYM (hiintstack),a0 | a0 = high end of intr stack - movec a0,isp | set interrupt stack -#endif - - move.l #0,a7@- | environp - move.l #0,a7@- | argv - move.l #0,a7@- | argc - jsr SYM (boot_card) - - nop -Bad: bra Bad - - nop -END_CODE - - -BEGIN_DATA - - PUBLIC (start_frame) -SYM (start_frame): - .space 4,0 - - PUBLIC (stack_start) -SYM (stack_start): - .space 4,0 -END_DATA - -BEGIN_BSS - - PUBLIC (environ) - .align 2 -SYM (environ): - .long 0 - - PUBLIC (heap_size) - .set SYM (heap_size),0x2000 - - PUBLIC (stack_size) - .set SYM (stack_size),0x1000 - - -END_DATA -END diff --git a/c/src/lib/libbsp/m68k/gen68302/timer/Makefile.in b/c/src/lib/libbsp/m68k/gen68302/timer/Makefile.in index 24809cbed8..21ca9675e7 100644 --- a/c/src/lib/libbsp/m68k/gen68302/timer/Makefile.in +++ b/c/src/lib/libbsp/m68k/gen68302/timer/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=timerisr -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/m68k/gen68302/timer/timerisr.S b/c/src/lib/libbsp/m68k/gen68302/timer/timerisr.S new file mode 100644 index 0000000000..c804b9dfa6 --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68302/timer/timerisr.S @@ -0,0 +1,28 @@ +/* + * Handle 68302 TIMER2 interrupts. + * + * All code in this routine is pure overhead which can perturb the + * accuracy of RTEMS' timing test suite. + * + * See also: Read_timer() + * + * To reduce overhead this is best to be the "rawest" hardware interupt + * handler you can write. This should be the only interrupt which can + * occur during the measured time period. + * + * An external counter, Timer_interrupts, is incremented. + * + * $Id$ + */ + +#include "asm.h" + +BEGIN_CODE + PUBLIC(timerisr) +SYM(timerisr): + move.w #0x0040,SYM(m302)+2072 | clear interrupt in-service bit + move.b #3,SYM(m302)+2137 | clear timer interrupt event register + addq.l #1,SYM(Timer_interrupts) | increment timer value + rte +END_CODE +END diff --git a/c/src/lib/libbsp/m68k/gen68302/timer/timerisr.s b/c/src/lib/libbsp/m68k/gen68302/timer/timerisr.s deleted file mode 100644 index c804b9dfa6..0000000000 --- a/c/src/lib/libbsp/m68k/gen68302/timer/timerisr.s +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Handle 68302 TIMER2 interrupts. - * - * All code in this routine is pure overhead which can perturb the - * accuracy of RTEMS' timing test suite. - * - * See also: Read_timer() - * - * To reduce overhead this is best to be the "rawest" hardware interupt - * handler you can write. This should be the only interrupt which can - * occur during the measured time period. - * - * An external counter, Timer_interrupts, is incremented. - * - * $Id$ - */ - -#include "asm.h" - -BEGIN_CODE - PUBLIC(timerisr) -SYM(timerisr): - move.w #0x0040,SYM(m302)+2072 | clear interrupt in-service bit - move.b #3,SYM(m302)+2137 | clear timer interrupt event register - addq.l #1,SYM(Timer_interrupts) | increment timer value - rte -END_CODE -END diff --git a/c/src/lib/libbsp/m68k/gen68340/console/Makefile.in b/c/src/lib/libbsp/m68k/gen68340/console/Makefile.in index 62a52b15e6..c26ac13b81 100644 --- a/c/src/lib/libbsp/m68k/gen68340/console/Makefile.in +++ b/c/src/lib/libbsp/m68k/gen68340/console/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=Modif_cpu_asm -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/m68k/gen68340/console/Modif_cpu_asm.S b/c/src/lib/libbsp/m68k/gen68340/console/Modif_cpu_asm.S new file mode 100644 index 0000000000..0da5865fb3 --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68340/console/Modif_cpu_asm.S @@ -0,0 +1,184 @@ +/* cpu_asm.s + * + * This file contains all assembly code for the MC68020 implementation + * of RTEMS. + * + * ATTENTION: Modified for benchmarks + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + + +#include + + .text + +/*PAGE + * void _Debug_ISR_Handler_Console() + * + * This routine provides the RTEMS interrupt management. + * + * NOTE: + * Upon entry, the master stack will contain an interrupt stack frame + * back to the interrupted thread and the interrupt stack will contain + * a throwaway interrupt stack frame. If dispatching is enabled, this + * is the outer most interrupt, and (a context switch is necessary or + * the current thread has signals), then set up the master stack to + * transfer control to the interrupt dispatcher. + * NOTE: + * USED TO MESURE THE TIME SPENT IN THE INTERRUPT SUBROUTINE + * CS5 - CS8 are linked to an oscilloscope so that you can mesure + * RTEMS overhead (BTW it's very short :) ) + */ + +/* + * With this approach, lower priority interrupts may + * execute twice if a higher priority interrupt is + * acknowledged before _Thread_Dispatch_disable is + * increamented and the higher priority interrupt + * preforms a context switch after executing. The lower + * priority intterrupt will execute (1) at the end of the + * higher priority interrupt in the new context if + * permitted by the new interrupt level mask, and (2) when + * the original context regains the cpu. + */ + +#if ( M68K_HAS_VBR == 1) +.set SR_OFFSET, 0 | Status register offset +.set PC_OFFSET, 2 | Program Counter offset +.set FVO_OFFSET, 6 | Format/vector offset +#else +.set SR_OFFSET, 2 | Status register offset +.set PC_OFFSET, 4 | Program Counter offset +.set FVO_OFFSET, 0 | Format/vector offset placed in the stack +#endif /* M68K_HAS_VBR */ + +.set SAVED, 16 | space for saved registers + + .align 4 + .global SYM (_Debug_ISR_Handler_Console) + +SYM (_Debug_ISR_Handler_Console): + + | + tst.w 0x14000000 | ALLUME CS5 + | + + addql #1,SYM (_Thread_Dispatch_disable_level) | disable multitasking + moveml d0-d1/a0-a1,a7@- | save d0-d1,a0-a1 + movew a7@(SAVED+FVO_OFFSET),d0 | d0 = F/VO + andl #0x0fff,d0 | d0 = vector offset in vbr + + +#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 ) + movew sr,d1 | Save status register + oriw #0x700,sr | Disable interrupts + tstl SYM (_ISR_Nest_level) | Interrupting an interrupt handler? + bne 1f | Yes, just skip over stack switch code + movel SYM(_CPU_Interrupt_stack_high),a0 | End of interrupt stack + movel a7,a0@- | Save task stack pointer + movel a0,a7 | Switch to interrupt stack +1: + addql #1,SYM(_ISR_Nest_level) | one nest level deeper + movew d1,sr | Restore status register +#else + addql #1,SYM (_ISR_Nest_level) | one nest level deeper +#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */ + +#if ( M68K_HAS_PREINDEXING == 1 ) + movel @( SYM (_ISR_Vector_table),d0:w:1),a0| fetch the ISR +#else + movel # SYM (_ISR_Vector_table),a0 | a0 = base of RTEMS table + addal d0,a0 | a0 = address of vector + movel (a0),a0 | a0 = address of user routine +#endif + + lsrl #2,d0 | d0 = vector number + movel d0,a7@- | push vector number + + | + tst.w 0x18000000 | ALLUME CS6 + | + + jbsr a0@ | invoke the user ISR + + | + tst.w 0x18000000 | ALLUME CS6 + | + + addql #4,a7 | remove vector number + +#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 ) + movew sr,d0 | Save status register + oriw #0x700,sr | Disable interrupts + subql #1,SYM(_ISR_Nest_level) | Reduce interrupt-nesting count + bne 1f | Skip if return to interrupt + movel (a7),a7 | Restore task stack pointer +1: + movew d0,sr | Restore status register +#else + subql #1,SYM (_ISR_Nest_level) | one less nest level +#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */ + + subql #1,SYM (_Thread_Dispatch_disable_level) + | unnest multitasking + bne Debug_exit | If dispatch disabled, Debug_exit + +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) + movew #0xf000,d0 | isolate format nibble + andw a7@(SAVED+FVO_OFFSET),d0 | get F/VO + cmpiw #0x1000,d0 | is it a throwaway isf? + bne Debug_exit | NOT outer level, so branch +#endif + + tstl SYM (_Context_Switch_necessary) + | Is thread switch necessary? + bne bframe | Yes, invoke dispatcher + + tstl SYM (_ISR_Signals_to_thread_executing) + | signals sent to Run_thread + | while in interrupt handler? + beq Debug_exit | No, then Debug_exit + + +bframe: clrl SYM (_ISR_Signals_to_thread_executing) + | If sent, will be processed +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) + movec msp,a0 | a0 = master stack pointer + movew #0,a0@- | push format word + movel # SYM (_ISR_Dispatch),a0@- | push return addr + | filter out the trace bit to stop single step debugging breaking + movew a0@(6+SR_OFFSET),d0 + andw #0x7FFF,d0 + movew d0,a0@- | push thread sr + movec a0,msp | set master stack pointer +#else + + | filter out the trace bit to stop single step debugging breaking + movew a7@(16+SR_OFFSET),d0 + andw #0x7FFF,d0 + movew d0,sr + jsr SYM (_Thread_Dispatch) +#endif + +Debug_exit: moveml a7@+,d0-d1/a0-a1 | restore d0-d1,a0-a1 +#if ( M68K_HAS_VBR == 0 ) + addql #2,a7 | pop format/id +#endif /* M68K_HAS_VBR */ + + | + tst.w 0x1C000000 | ALLUME CS7 + | + + rte | return to thread + | OR _Isr_dispatch + + diff --git a/c/src/lib/libbsp/m68k/gen68340/console/Modif_cpu_asm.s b/c/src/lib/libbsp/m68k/gen68340/console/Modif_cpu_asm.s deleted file mode 100644 index 0da5865fb3..0000000000 --- a/c/src/lib/libbsp/m68k/gen68340/console/Modif_cpu_asm.s +++ /dev/null @@ -1,184 +0,0 @@ -/* cpu_asm.s - * - * This file contains all assembly code for the MC68020 implementation - * of RTEMS. - * - * ATTENTION: Modified for benchmarks - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - - -#include - - .text - -/*PAGE - * void _Debug_ISR_Handler_Console() - * - * This routine provides the RTEMS interrupt management. - * - * NOTE: - * Upon entry, the master stack will contain an interrupt stack frame - * back to the interrupted thread and the interrupt stack will contain - * a throwaway interrupt stack frame. If dispatching is enabled, this - * is the outer most interrupt, and (a context switch is necessary or - * the current thread has signals), then set up the master stack to - * transfer control to the interrupt dispatcher. - * NOTE: - * USED TO MESURE THE TIME SPENT IN THE INTERRUPT SUBROUTINE - * CS5 - CS8 are linked to an oscilloscope so that you can mesure - * RTEMS overhead (BTW it's very short :) ) - */ - -/* - * With this approach, lower priority interrupts may - * execute twice if a higher priority interrupt is - * acknowledged before _Thread_Dispatch_disable is - * increamented and the higher priority interrupt - * preforms a context switch after executing. The lower - * priority intterrupt will execute (1) at the end of the - * higher priority interrupt in the new context if - * permitted by the new interrupt level mask, and (2) when - * the original context regains the cpu. - */ - -#if ( M68K_HAS_VBR == 1) -.set SR_OFFSET, 0 | Status register offset -.set PC_OFFSET, 2 | Program Counter offset -.set FVO_OFFSET, 6 | Format/vector offset -#else -.set SR_OFFSET, 2 | Status register offset -.set PC_OFFSET, 4 | Program Counter offset -.set FVO_OFFSET, 0 | Format/vector offset placed in the stack -#endif /* M68K_HAS_VBR */ - -.set SAVED, 16 | space for saved registers - - .align 4 - .global SYM (_Debug_ISR_Handler_Console) - -SYM (_Debug_ISR_Handler_Console): - - | - tst.w 0x14000000 | ALLUME CS5 - | - - addql #1,SYM (_Thread_Dispatch_disable_level) | disable multitasking - moveml d0-d1/a0-a1,a7@- | save d0-d1,a0-a1 - movew a7@(SAVED+FVO_OFFSET),d0 | d0 = F/VO - andl #0x0fff,d0 | d0 = vector offset in vbr - - -#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 ) - movew sr,d1 | Save status register - oriw #0x700,sr | Disable interrupts - tstl SYM (_ISR_Nest_level) | Interrupting an interrupt handler? - bne 1f | Yes, just skip over stack switch code - movel SYM(_CPU_Interrupt_stack_high),a0 | End of interrupt stack - movel a7,a0@- | Save task stack pointer - movel a0,a7 | Switch to interrupt stack -1: - addql #1,SYM(_ISR_Nest_level) | one nest level deeper - movew d1,sr | Restore status register -#else - addql #1,SYM (_ISR_Nest_level) | one nest level deeper -#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */ - -#if ( M68K_HAS_PREINDEXING == 1 ) - movel @( SYM (_ISR_Vector_table),d0:w:1),a0| fetch the ISR -#else - movel # SYM (_ISR_Vector_table),a0 | a0 = base of RTEMS table - addal d0,a0 | a0 = address of vector - movel (a0),a0 | a0 = address of user routine -#endif - - lsrl #2,d0 | d0 = vector number - movel d0,a7@- | push vector number - - | - tst.w 0x18000000 | ALLUME CS6 - | - - jbsr a0@ | invoke the user ISR - - | - tst.w 0x18000000 | ALLUME CS6 - | - - addql #4,a7 | remove vector number - -#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 ) - movew sr,d0 | Save status register - oriw #0x700,sr | Disable interrupts - subql #1,SYM(_ISR_Nest_level) | Reduce interrupt-nesting count - bne 1f | Skip if return to interrupt - movel (a7),a7 | Restore task stack pointer -1: - movew d0,sr | Restore status register -#else - subql #1,SYM (_ISR_Nest_level) | one less nest level -#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */ - - subql #1,SYM (_Thread_Dispatch_disable_level) - | unnest multitasking - bne Debug_exit | If dispatch disabled, Debug_exit - -#if ( M68K_HAS_SEPARATE_STACKS == 1 ) - movew #0xf000,d0 | isolate format nibble - andw a7@(SAVED+FVO_OFFSET),d0 | get F/VO - cmpiw #0x1000,d0 | is it a throwaway isf? - bne Debug_exit | NOT outer level, so branch -#endif - - tstl SYM (_Context_Switch_necessary) - | Is thread switch necessary? - bne bframe | Yes, invoke dispatcher - - tstl SYM (_ISR_Signals_to_thread_executing) - | signals sent to Run_thread - | while in interrupt handler? - beq Debug_exit | No, then Debug_exit - - -bframe: clrl SYM (_ISR_Signals_to_thread_executing) - | If sent, will be processed -#if ( M68K_HAS_SEPARATE_STACKS == 1 ) - movec msp,a0 | a0 = master stack pointer - movew #0,a0@- | push format word - movel # SYM (_ISR_Dispatch),a0@- | push return addr - | filter out the trace bit to stop single step debugging breaking - movew a0@(6+SR_OFFSET),d0 - andw #0x7FFF,d0 - movew d0,a0@- | push thread sr - movec a0,msp | set master stack pointer -#else - - | filter out the trace bit to stop single step debugging breaking - movew a7@(16+SR_OFFSET),d0 - andw #0x7FFF,d0 - movew d0,sr - jsr SYM (_Thread_Dispatch) -#endif - -Debug_exit: moveml a7@+,d0-d1/a0-a1 | restore d0-d1,a0-a1 -#if ( M68K_HAS_VBR == 0 ) - addql #2,a7 | pop format/id -#endif /* M68K_HAS_VBR */ - - | - tst.w 0x1C000000 | ALLUME CS7 - | - - rte | return to thread - | OR _Isr_dispatch - - diff --git a/c/src/lib/libbsp/m68k/gen68340/start/Makefile.in b/c/src/lib/libbsp/m68k/gen68340/start/Makefile.in index ce91b95e3b..4dfebd249f 100644 --- a/c/src/lib/libbsp/m68k/gen68340/start/Makefile.in +++ b/c/src/lib/libbsp/m68k/gen68340/start/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=start340 -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/m68k/gen68340/start/start.S b/c/src/lib/libbsp/m68k/gen68340/start/start.S new file mode 100644 index 0000000000..58ea0c92d0 --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68340/start/start.S @@ -0,0 +1,874 @@ +/* + * This file contains the entry point for the application. + * The name of this entry point is compiler dependent. + * It jumps to the BSP which is responsible for performing + * all initialization. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * Based on the `gen68360' board support package, and covered by the + * original distribution terms. + * + * Geoffroy Montel + * France Telecom - CNET/DSM/TAM/CAT + * 4, rue du Clos Courtel + * 35512 CESSON-SEVIGNE + * FRANCE + * + * e-mail: g_montel@yahoo.com + * + * $Id$ + */ + +#include "asm.h" +#include + +#define _OLD_ASTECC 1 /* old addresses for AST68340 only, undefine for AST68349 */ + +BEGIN_CODE + /* + * Step 1: Decide on Reset Stack Pointer and Initial Program Counter + */ +Entry: + .long SYM(m340)+1024 | 0: Initial SSP + .long start | 1: Initial PC + .long SYM(_uhoh) | 2: Bus error + .long SYM(_uhoh) | 3: Address error + .long SYM(_uhoh) | 4: Illegal instruction + .long SYM(_uhoh) | 5: Zero division + .long SYM(_uhoh) | 6: CHK, CHK2 instruction + .long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions + .long SYM(_uhoh) | 8: Privilege violation + .long SYM(_uhoh) | 9: Trace + .long SYM(_uhoh) | 10: Line 1010 emulator + .long SYM(_uhoh) | 11: Line 1111 emulator + .long SYM(_uhoh) | 12: Hardware breakpoint + .long SYM(_uhoh) | 13: Reserved for coprocessor violation + .long SYM(_uhoh) | 14: Format error + .long SYM(_uhoh) | 15: Uninitialized interrupt + .long SYM(_uhoh) | 16: Unassigned, reserved + .long SYM(_uhoh) | 17: + .long SYM(_uhoh) | 18: + .long SYM(_uhoh) | 19: + .long SYM(_uhoh) | 20: + .long SYM(_uhoh) | 21: + .long SYM(_uhoh) | 22: + .long SYM(_uhoh) | 23: + .long SYM(_spuriousInterrupt) | 24: Spurious interrupt + .long SYM(_uhoh) | 25: Level 1 interrupt autovector + .long SYM(_uhoh) | 26: Level 2 interrupt autovector + .long SYM(_uhoh) | 27: Level 3 interrupt autovector + .long SYM(_uhoh) | 28: Level 4 interrupt autovector + .long SYM(_uhoh) | 29: Level 5 interrupt autovector + .long SYM(_uhoh) | 30: Level 6 interrupt autovector + .long SYM(_uhoh) | 31: Level 7 interrupt autovector + .long SYM(_uhoh) | 32: Trap instruction (0-15) + .long SYM(_uhoh) | 33: + .long SYM(_uhoh) | 34: + .long SYM(_uhoh) | 35: + .long SYM(_uhoh) | 36: + .long SYM(_uhoh) | 37: + .long SYM(_uhoh) | 38: + .long SYM(_uhoh) | 39: + .long SYM(_uhoh) | 40: + .long SYM(_uhoh) | 41: + .long SYM(_uhoh) | 42: + .long SYM(_uhoh) | 43: + .long SYM(_uhoh) | 44: + .long SYM(_uhoh) | 45: + .long SYM(_uhoh) | 46: + .long SYM(_uhoh) | 47: + .long SYM(_uhoh) | 48: Reserved for coprocessor + .long SYM(_uhoh) | 49: + .long SYM(_uhoh) | 50: + .long SYM(_uhoh) | 51: + .long SYM(_uhoh) | 52: + .long SYM(_uhoh) | 53: + .long SYM(_uhoh) | 54: + .long SYM(_uhoh) | 55: + .long SYM(_uhoh) | 56: + .long SYM(_uhoh) | 57: + .long SYM(_uhoh) | 58: + .long SYM(_uhoh) | 59: Unassigned, reserved + .long SYM(_uhoh) | 60: + .long SYM(_uhoh) | 61: + .long SYM(_uhoh) | 62: + .long SYM(_uhoh) | 63: + .long SYM(_uhoh) | 64: User defined vectors (192) + .long SYM(_uhoh) | 65: + .long SYM(_uhoh) | 66: + .long SYM(_uhoh) | 67: + .long SYM(_uhoh) | 68: + .long SYM(_uhoh) | 69: + .long SYM(_uhoh) | 70: + .long SYM(_uhoh) | 71: + .long SYM(_uhoh) | 72: + .long SYM(_uhoh) | 73: + .long SYM(_uhoh) | 74: + .long SYM(_uhoh) | 75: + .long SYM(_uhoh) | 76: + .long SYM(_uhoh) | 77: + .long SYM(_uhoh) | 78: + .long SYM(_uhoh) | 79: + .long SYM(_uhoh) | 80: + .long SYM(_uhoh) | 81: + .long SYM(_uhoh) | 82: + .long SYM(_uhoh) | 83: + .long SYM(_uhoh) | 84: + .long SYM(_uhoh) | 85: + .long SYM(_uhoh) | 86: + .long SYM(_uhoh) | 87: + .long SYM(_uhoh) | 88: + .long SYM(_uhoh) | 89: + .long SYM(_uhoh) | 90: + .long SYM(_uhoh) | 91: + .long SYM(_uhoh) | 92: + .long SYM(_uhoh) | 93: + .long SYM(_uhoh) | 94: + .long SYM(_uhoh) | 95: + .long SYM(_uhoh) | 96: + .long SYM(_uhoh) | 97: + .long SYM(_uhoh) | 98: + .long SYM(_uhoh) | 99: + .long SYM(_uhoh) | 100: + .long SYM(_uhoh) | 101: + .long SYM(_uhoh) | 102: + .long SYM(_uhoh) | 103: + .long SYM(_uhoh) | 104: + .long SYM(_uhoh) | 105: + .long SYM(_uhoh) | 106: + .long SYM(_uhoh) | 107: + .long SYM(_uhoh) | 108: + .long SYM(_uhoh) | 109: + .long SYM(_uhoh) | 110: + .long SYM(_uhoh) | 111: + .long SYM(_uhoh) | 112: + .long SYM(_uhoh) | 113: + .long SYM(_uhoh) | 114: + .long SYM(_uhoh) | 115: + .long SYM(_uhoh) | 116: + .long SYM(_uhoh) | 117: + .long SYM(_uhoh) | 118: + .long SYM(_uhoh) | 119: + .long SYM(_uhoh) | 120: + .long SYM(_uhoh) | 121: + .long SYM(_uhoh) | 122: + .long SYM(_uhoh) | 123: + .long SYM(_uhoh) | 124: + .long SYM(_uhoh) | 125: + .long SYM(_uhoh) | 126: + .long SYM(_uhoh) | 127: + .long SYM(_uhoh) | 128: + .long SYM(_uhoh) | 129: + .long SYM(_uhoh) | 130: + .long SYM(_uhoh) | 131: + .long SYM(_uhoh) | 132: + .long SYM(_uhoh) | 133: + .long SYM(_uhoh) | 134: + .long SYM(_uhoh) | 135: + .long SYM(_uhoh) | 136: + .long SYM(_uhoh) | 137: + .long SYM(_uhoh) | 138: + .long SYM(_uhoh) | 139: + .long SYM(_uhoh) | 140: + .long SYM(_uhoh) | 141: + .long SYM(_uhoh) | 142: + .long SYM(_uhoh) | 143: + .long SYM(_uhoh) | 144: + .long SYM(_uhoh) | 145: + .long SYM(_uhoh) | 146: + .long SYM(_uhoh) | 147: + .long SYM(_uhoh) | 148: + .long SYM(_uhoh) | 149: + .long SYM(_uhoh) | 150: + .long SYM(_uhoh) | 151: + .long SYM(_uhoh) | 152: + .long SYM(_uhoh) | 153: + .long SYM(_uhoh) | 154: + .long SYM(_uhoh) | 155: + .long SYM(_uhoh) | 156: + .long SYM(_uhoh) | 157: + .long SYM(_uhoh) | 158: + .long SYM(_uhoh) | 159: + .long SYM(_uhoh) | 160: + .long SYM(_uhoh) | 161: + .long SYM(_uhoh) | 162: + .long SYM(_uhoh) | 163: + .long SYM(_uhoh) | 164: + .long SYM(_uhoh) | 165: + .long SYM(_uhoh) | 166: + .long SYM(_uhoh) | 167: + .long SYM(_uhoh) | 168: + .long SYM(_uhoh) | 169: + .long SYM(_uhoh) | 170: + .long SYM(_uhoh) | 171: + .long SYM(_uhoh) | 172: + .long SYM(_uhoh) | 173: + .long SYM(_uhoh) | 174: + .long SYM(_uhoh) | 175: + .long SYM(_uhoh) | 176: + .long SYM(_uhoh) | 177: + .long SYM(_uhoh) | 178: + .long SYM(_uhoh) | 179: + .long SYM(_uhoh) | 180: + .long SYM(_uhoh) | 181: + .long SYM(_uhoh) | 182: + .long SYM(_uhoh) | 183: + .long SYM(_uhoh) | 184: + .long SYM(_uhoh) | 185: + .long SYM(_uhoh) | 186: + .long SYM(_uhoh) | 187: + .long SYM(_uhoh) | 188: + .long SYM(_uhoh) | 189: + .long SYM(_uhoh) | 190: + .long SYM(_uhoh) | 191: + .long SYM(_uhoh) | 192: + .long SYM(_uhoh) | 193: + .long SYM(_uhoh) | 194: + .long SYM(_uhoh) | 195: + .long SYM(_uhoh) | 196: + .long SYM(_uhoh) | 197: + .long SYM(_uhoh) | 198: + .long SYM(_uhoh) | 199: + .long SYM(_uhoh) | 200: + .long SYM(_uhoh) | 201: + .long SYM(_uhoh) | 202: + .long SYM(_uhoh) | 203: + .long SYM(_uhoh) | 204: + .long SYM(_uhoh) | 205: + .long SYM(_uhoh) | 206: + .long SYM(_uhoh) | 207: + .long SYM(_uhoh) | 208: + .long SYM(_uhoh) | 209: + .long SYM(_uhoh) | 210: + .long SYM(_uhoh) | 211: + .long SYM(_uhoh) | 212: + .long SYM(_uhoh) | 213: + .long SYM(_uhoh) | 214: + .long SYM(_uhoh) | 215: + .long SYM(_uhoh) | 216: + .long SYM(_uhoh) | 217: + .long SYM(_uhoh) | 218: + .long SYM(_uhoh) | 219: + .long SYM(_uhoh) | 220: + .long SYM(_uhoh) | 221: + .long SYM(_uhoh) | 222: + .long SYM(_uhoh) | 223: + .long SYM(_uhoh) | 224: + .long SYM(_uhoh) | 225: + .long SYM(_uhoh) | 226: + .long SYM(_uhoh) | 227: + .long SYM(_uhoh) | 228: + .long SYM(_uhoh) | 229: + .long SYM(_uhoh) | 230: + .long SYM(_uhoh) | 231: + .long SYM(_uhoh) | 232: + .long SYM(_uhoh) | 233: + .long SYM(_uhoh) | 234: + .long SYM(_uhoh) | 235: + .long SYM(_uhoh) | 236: + .long SYM(_uhoh) | 237: + .long SYM(_uhoh) | 238: + .long SYM(_uhoh) | 239: + .long SYM(_uhoh) | 240: + .long SYM(_uhoh) | 241: + .long SYM(_uhoh) | 242: + .long SYM(_uhoh) | 243: + .long SYM(_uhoh) | 244: + .long SYM(_uhoh) | 245: + .long SYM(_uhoh) | 246: + .long SYM(_uhoh) | 247: + .long SYM(_uhoh) | 248: + .long SYM(_uhoh) | 249: + .long SYM(_uhoh) | 250: + .long SYM(_uhoh) | 251: + .long SYM(_uhoh) | 252: + .long SYM(_uhoh) | 253: + .long SYM(_uhoh) | 254: + .long SYM(_uhoh) | 255: + +/* + * Default trap handler + * With an oscilloscope you can see AS* stop + */ + PUBLIC (_uhoh) +SYM(_uhoh): nop | Leave spot for breakpoint +/* stop #0x2700 | Stop with interrupts disabled */ + move.w #0x2700,sr + move.w (a7),_boot_panic_registers+4 | SR + move.l 2(a7),_boot_panic_registers | PC + move.w 6(a7),_boot_panic_registers+6 | format & vector + movem.l d0-d7/a0-a7, _boot_panic_registers+8 + movec sfc, d0 + movem.l d0, _boot_panic_registers+72 + movec dfc, d0 + movem.l d0, _boot_panic_registers+76 + movec vbr, d0 + movem.l d0, _boot_panic_registers+80 + jmp SYM(_dbug_dumpanic) + bra.s _crt0_cold_start + +/* + * Log, but otherwise ignore, spurious interrupts + */ + PUBLIC (_spuriousInterrupt) +SYM(_spuriousInterrupt): + addql #1,SYM(_M68kSpuriousInterruptCount) + rte + +/* + * Place the low-order 3 octets of the board's ethernet address at + * a `well-known' fixed location relative to the startup location. + */ + .align 2 + .word 0 | Padding +ethernet_address_buffer: + .word 0x08F3 | Default address + .word 0xDEAD + .word 0xCAFE + +BEGIN_DATA + +/* equates */ + +.equ _CPU340, 0x0 +.equ _CPU349, 0x31 + +#ifdef _OLD_ASTECC /* old addresses for AST68340 only */ +.equ _EPLD_CS_BASE, 0x1 +.equ _PROM_Start, 0x01000000 /* CS0 */ +.equ _FLEX_Start, 0x08000000 /* CS2 */ +.equ _I2C_Start, 0x0c000000 /* CS3 */ + +.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */ +.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */ + +.equ _ExtRam_Start, 0x10000000 /* SRAM */ +.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */ + +.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */ +.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */ + +#else /* new addresses for AST68349 and 68340 */ + +.equ _EPLD_CS_BASE, 0x5 +.equ _PROM_Start, 0x50000000 /* CS0 */ +.equ _FLEX_Start, 0x08000000 /* CS2 */ +.equ _I2C_Start, 0x0c000000 /* CS3 */ + +.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */ +.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */ + +.equ _ExtRam_Start, 0x80000000 /* DRAM */ +.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */ + +.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */ +.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */ +#endif + +.equ _SPEED349, 0xD680 /* 24 Mhz */ +.equ _SPEED340, 0xD700 /* 25 Mhz */ +/* .equ _SPEED340, 0xCE00 16 Mhz */ + +#define crt0_boot_type d0 /* cold/warm start (must be D0) */ +#define crt0_temp d1 +#define crt0_cpu_type d2 +#define crt0_csswitch d3 +#define crt0_buswidth d4 +#define crt0_pdcs d5 +#define crt0_spare6 d6 +#define crt0_spare7 d7 +#define crt0_sim_base a0 +#define crt0_glue a1 +#define crt0_dram a2 +#define crt0_ptr3 a3 +#define crt0_ptr4 a4 +#define crt0_ptr5 a5 +#define crt0_ptr6 a6 + +/* -- PDCS buffer equates -- */ +.equ pdcs_mask, 0x1F /* DRAM configuration */ +.equ pdcs_sw12, 7 /* switch 12 */ +.equ pdcs_sw11, 6 /* switch 11 */ +.equ pdcs_sw14, 5 /* switch 14 */ + +.equ bit_cache, pdcs_sw12 /* enable cache if on */ +.equ bit_meminit, pdcs_sw11 /* init memory if on */ + +/* -- Initialization stack and vars -- */ + +_AsteccBusWidth: ds.b 1 +_AsteccCsSwitch: ds.b 1 +_AsteccCpuName: ds.l 1 + +.align 4 + +_crt0_init_stack: + ds.l 500 +_crt0_init_stktop: + +/* -- Initialization code -- */ +BEGIN_CODE + +.align 4 + dc.l _crt0_init_stktop /* reset SP */ + dc.l _crt0_cold_start /* reset PC */ + dc.l _crt0_warm_start + + .ascii "BOOT XHM68K/Spectra for ASTECC 68349 and 68340 boards" + dc.w 0 +.align 4 + +.globl start +start: + +_crt0_cold_start: + moveq.l #0,crt0_boot_type | signal cold reset + bra.s _crt0_common_start + +_crt0_warm_start: + moveq.l #1,crt0_boot_type | signal warm reset + +_crt0_common_start: + move.w #0x2700,sr | disable interrupts and switch to interrupt mode + movea.l #_crt0_init_stktop,sp | set up initialization stack + + move.l #Entry,crt0_temp | VBR initialization + movec.l crt0_temp,vbr | + moveq.l #0x07,crt0_temp + movec.l crt0_temp,dfc | prepare access in CPU space + move.l #(BASE_SIM+0x111),crt0_temp | mask CPU, RESERVED USER SPACES + moves.l crt0_temp,BASE_REG | base initialization (must be MOVES, PCC-130795) + + movea.l #BASE_SIM,crt0_sim_base + + /* -- disable Bus Monitor -- */ + move.b #0,SIM_SYPCR(crt0_sim_base) | system protection control register + + /* -- enable A31-A24 -- */ + clr.b SIM_PPRA1(crt0_sim_base) + + /* -- show cycles, user acces to SIM, 4 /CS & 4 /IT -- */ + move.w #0x427F,SIM_MCR(crt0_sim_base) + + /* -- enable /IRQ3, 5, 6, 7 -- */ + move.b #0xE8,SIM_PPRB(crt0_sim_base) + + /* -- enable autovector on /IRQ7 -- */ + move.b #0x80,SIM_AVR(crt0_sim_base) + + /* -- test CPU type -- */ + cmp.b #_CPU349,SIM_IDR(crt0_sim_base) + bne cpu_is_68340 + +/*-------------------------------------------------------------------------------------------*/ +cpu_is_68349: + + /* -- set cpu clock -- */ + move.w #_SPEED349,SIM_SYNCR(crt0_sim_base) | clock + +sync_wait349: + btst.b #3,(SIM_SYNCR+1)(crt0_sim_base) + beq sync_wait349 + + /* to allow access to the EPLD internal registers, it is necessary + to disable the global chip-select /CS0 (which decodes every external + cycles). To do that, we initialize the 68349 internal RAM, + copy a part of the initialization code in it, and jump there. + from that moment, /CS0 is not used, therefore it can be initialized + with its default value. Its width may be incorrect, but it will be + adjusted later. The goal is to avoid any conflict with + the accesses to the EPLD registers. + When this is done, we read the RESET parameters (boot prom width + and chip-select switch) and proceed with the initialization + when all is done, we jump back to the boot prom now + decoded with a properly configured /CS0 */ + + /*-------------------------------------*/ + /* -- configure internal SRAM banks -- */ + + move.l #0x00000000,QDMM_MCR(crt0_sim_base) + move.l #_FastRam_Start+0x0005,QDMM_QBAR0(crt0_sim_base) + move.l #_FastRam_Start+0x0405,QDMM_QBAR1(crt0_sim_base) + move.l #_FastRam_Start+0x0805,QDMM_QBAR2(crt0_sim_base) + move.l #_FastRam_Start+0x0c05,QDMM_QBAR3(crt0_sim_base) + + /*--------------------------------------------------------*/ + /* -- copy to address of the 68349 initialization code -- */ + + lea.l _copy_start(%pc),crt0_ptr3 + lea.l _copy_end(%pc),crt0_ptr4 + move.l crt0_ptr4,crt0_temp + sub.l crt0_ptr3,crt0_temp + add.l #3,crt0_temp | adjust to next long word + lsr.l #2,crt0_temp + + move.l #_FastRam_Start,crt0_ptr4 +_copy_loop: + move.l (crt0_ptr3)+,(crt0_ptr4)+ + subq.l #1,crt0_temp + bne.s _copy_loop + bra.l _FastRam_Start | jump to code in internal RAM + + /*------------------------------------*/ + /* -- start of initialization code -- */ + +_copy_start: + bra.l _begin_68349_init + + /*----------------------------------------------------------*/ + /* Astecc 68349 board : chip-select initialization values */ + +_table_csepld: + dc.b (_EPLD_CS_BASE&0x0F)+0x80 | 16 bits, 0ws + dc.b 0x80 | 16 bits, 0 ws + dc.b 0x90 | 16 bits, ext /dsack + dc.b 0x90 | 16 bits, ext /dsack + +_table_cs349: + dc.l 0x003FFFF4 | Mask CS0 (4Mbytes PROM, 32bits, 1WS) + dc.l (_PROM_Start&0xFFFFFF00)+0x00000003 | Base CS0 + dc.l 0x003FFFF1 | MASK CS1 (4Mbytes RAM, 16bits, 0WS) + dc.l (_BCCram_Start&0xFFFFFF00)+0x00000003 | Base CS1 + dc.l 0x000000FF | MASK CS2 (FLEX, ext DTACK, 256 bytes) + dc.l (_FLEX_Start&0xFFFFFF00)+0x00000003 | Base CS2 + dc.l 0x000000FF | Mask CS3 (I2C, ext DTACK, 256 bytes) + dc.l (_I2C_Start&0xFFFFFF00)+0x00000003 | Base CS3 + + /*-------------------------------------------------*/ +_begin_68349_init: + + /*-------------------------------------------------*/ + /* 68349 chip select initialization + + at this stage, the width of /CS0 may be incorrect + it will be corrected later + */ + +_cs68349_init: + lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 + lea.l _table_cs349(%pc),crt0_ptr3 + + moveq.l #0x07,crt0_temp +_cs349_init2: + move.l (crt0_ptr3)+,(crt0_ptr4)+ + dbra crt0_temp,_cs349_init2 + + /*-----------------------------------------------*/ + /* -- prepare access to the internal registers --*/ + moveq.l #EPLD_SPACE,crt0_temp + movec.l crt0_temp,dfc + movec.l crt0_temp,sfc + move.l #GLUE_EPLD,crt0_glue + move.l #DRAM_EPLD,crt0_dram + + /*-------------------------------------------*/ + /* EPLD generated /CS[3..0] must be disabled */ + +_csepld_clear: + move.l crt0_glue,crt0_ptr4 + move.w #3,crt0_spare6 + clr.b crt0_temp + +_csepld_clear1: + moves.b crt0_temp,(crt0_ptr4)+ + dbra crt0_spare6,_csepld_clear1 + + /*---------------------------------------------------------*/ + /* -- get width of boot PROM, and active chip-select set --*/ + moves.b REG_BUSWIDTH(crt0_dram),crt0_csswitch + move.b crt0_csswitch,crt0_buswidth + + /* state of CS_SWITCH : sel == 0 => CPU chip_selects (/CS[3..0]) + : sel == 1 => EPLD chip_selects (/CS[3..0]) */ + and.b #1,crt0_csswitch + + /* bus width of /CS0 during reset bw[1..0] : 0 1 2 3 + bus width : 32 16 8 ext./dsackx */ + rol.b #2,crt0_buswidth + and.b #3,crt0_buswidth + + /*----------------------------------------------------*/ + /* -- configure chip select 0 with boot prom width -- */ + lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 + lea.l _table_cs349(%pc),crt0_ptr3 + move.l (crt0_ptr3)+,crt0_temp + and.b #0xFC,crt0_temp | clear PS0 & PS1 + or.b crt0_buswidth,crt0_temp | set boot PROM bus width + move.l crt0_temp,(crt0_ptr4)+ + + /*------------------------*/ + /* -- read PDCS buffer -- */ + moves.b REG_PDCS(crt0_glue),crt0_pdcs +/* move.b #0x3F,crt0_pdcs pour test */ + + + /*---------------------------------------*/ + /* -- EPLD chip-select initialization -- */ + /*---------------------------------------*/ + btst.b #0,crt0_csswitch + beq _cs_init_end + + /*--------------------------------------------*/ + /* 68349 generated /CS[3..0] must be disabled */ + lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 + lea.l _table_cs349(%pc),crt0_ptr3 + moveq.l #0x03,crt0_temp +_cs349_clear: + move.l (crt0_ptr3)+,(crt0_ptr4)+ + move.l (crt0_ptr3)+,crt0_spare6 + and.b #0xFE,crt0_spare6 | disable chip-select + move.l crt0_spare6,(crt0_ptr4)+ + dbra crt0_temp,_cs349_clear + + /*---------------------------------------------*/ + /* EPLD generated /CS[3..0] must be configured */ +_csepld_init: + move.l crt0_glue,crt0_ptr4 + lea.l _table_csepld(%pc),crt0_ptr3 + + move.b (crt0_ptr3)+,crt0_temp + or.b #0x20,crt0_temp | default width is 32 bits + tst.b crt0_buswidth | is boot PROM bus width 32 bits ? + beq _csepld1 | if not + and.b #0xDF,crt0_temp | set width to 16 bits +_csepld1: + moves.b crt0_temp,(crt0_ptr4)+ + + moveq.l #0x02,crt0_spare6 +_csepld2: + move.b (crt0_ptr3)+,crt0_temp + moves.b crt0_temp,(crt0_ptr4)+ + dbra crt0_spare6,_csepld2 + +_cs_init_end: + + /*--------------------------------------*/ + /* -- DRAM controller initialization -- */ +_dram_init: + move.w #15,crt0_temp + move.l #_ExtRam_Start,crt0_ptr3 + +_dram_init1: + clr.l (crt0_ptr3)+ | must access DRAM + dbra crt0_temp,_dram_init1 | prior to init refresh + +_dram_init2: + move.b #3,crt0_temp + moves.b crt0_temp,REG_WS(crt0_dram) | set 3 wait-states + + move.b #0x81,crt0_temp + moves.b crt0_temp,REG_REFRESH(crt0_dram) | refresh every 10µs + + move.b #0,crt0_temp + moves.b crt0_temp,REG_CONFIG(crt0_dram) | default size = 4Mbytes + + /*-----------------------*/ + /* -- configure cache -- */ +_init_cache: + move.l #0x000001E0,CACHE_MCR(crt0_sim_base) + btst.b #bit_cache,crt0_pdcs + bne _init_cache_end + or.l #0x00000001,CACHE_MCR(crt0_sim_base) + +_init_cache_end: + + /*-----------------------------*/ + /* -- timers initialization -- */ + + clr.b crt0_temp + moves.b crt0_temp,REG_TIMER1(crt0_glue) | disable timer 1 + moves.b crt0_temp,REG_TIMER2(crt0_glue) | disable timer 2 + + /*--------------------------*/ + /* -- I2C initialization -- */ + move.b #3,crt0_temp + moves.b crt0_temp,REG_I2C(crt0_glue) | tri-states I2C ports + + /*-----------------------------------------*/ + /* -- baudrate generator initialization -- */ + move.b #2,crt0_temp + moves.b crt0_temp,REG_BAUDRATE(crt0_glue) | baudrate = 38400 + + /*-------------------------------*/ + /* -- IO port initialization -- */ + clr.b crt0_temp + moves.b crt0_temp,REG_IO(crt0_glue) | set port as input + + /* -- */ + + move.l #68349,crt0_cpu_type + + + /* -- jump back to PROM -- */ + + jmp.l (_fill_test) | must be absolute long + +_copy_end: + +/*------------------------------------------------- + initialization code for the 68340 board + -------------------------------------------------*/ + + /* Astecc 68340 board : chip-select initialization values */ +_table_cs340: + dc.l 0x003FFFF0 /* Mask CS0 (4Mbytes PROM, 32bits, 0WS) */ + dc.l ((_PROM_Start&0xFFFFFF00)+0x00000003) /* Base CS0 */ + dc.l 0x0000FFFD /* MASK CS1 (RAMBCC340, 0WS, FTE) */ + dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000003) /* Base CS1 */ + dc.l 0x000000FF /* MASK CS2 (FLEX, ext DTACK, 256 bytes) */ + dc.l ((_FLEX_Start&0xFFFFFF00)+0x00000003) /* Base CS2 */ + dc.l 0x000000FF /* Mask CS3 (I2C, ext DTACK, 256 bytes) */ + dc.l ((_I2C_Start&0xFFFFFF00)+0x00000003) /* Base CS3 */ + +cpu_is_68340: + + /* -- set cpu clock -- */ + move.w #_SPEED340,SIM_SYNCR(crt0_sim_base) | clock +sync_wait340: + btst.b #3,(SIM_SYNCR+1)(crt0_sim_base) + beq sync_wait340 + + /* -- chip select initialization -- */ + lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 + lea.l _table_cs340(%pc),crt0_ptr3 + moveq.l #0x07,crt0_temp +_b_cs340: + move.l (crt0_ptr3)+,crt0_ptr5 + move.l crt0_ptr5,(crt0_ptr4)+ | pour test + dbra crt0_temp,_b_cs340 + + move.l #68340,crt0_cpu_type + move.b #0,crt0_csswitch | CPU + move.b #1,crt0_buswidth | 16 bits + + + /*------------------------------------------------- + fill RAM if COLDSTART + -------------------------------------------------*/ +_fill_test: + + tst.l crt0_boot_type + bne _dont_fill + + cmp.b #_CPU349,SIM_IDR(crt0_sim_base) + bne _fill + btst.b #bit_meminit,crt0_pdcs + bne _dont_fill + + /* fill main memory */ +_fill: + move.l #_crt0_init_stack,crt0_ptr3 | skip Astecc vars + move.l #_ExtRam_Start,crt0_temp + sub.l #_crt0_init_stack,crt0_temp + add.l #_ExtRam_Size,crt0_temp | get size + lsr.l #2,crt0_temp | ajust for long word +_fill_loop: + clr.l (crt0_ptr3)+ + subq.l #1,crt0_temp + bne _fill_loop + + cmp.b #_CPU349,SIM_IDR(crt0_sim_base) + bne _fill_bccram + + /* fill QDMM memory */ + movea.l #_FastRam_Start,crt0_ptr3 | get start + move.l #_FastRam_Size,crt0_temp | get size + lsr.l #2,crt0_temp | ajust for long word + +_QDMMfill_loop: + clr.l (crt0_ptr3)+ + subq.l #1,crt0_temp + bne _QDMMfill_loop + bra _dont_fill + + /* fill BCC memory */ +_fill_bccram: + movea.l #_BCCram_Start,crt0_ptr3 | get start + move.l #_BCCram_Size,crt0_temp | get size + lsr.l #2,crt0_temp | ajust for long word +_BCCfill_loop: + clr.l (crt0_ptr3)+ + subq.l #1,crt0_temp + bne _BCCfill_loop + + *-------------------------------------------------*/ +_dont_fill: + move.b crt0_csswitch,_AsteccCsSwitch + move.b crt0_buswidth,_AsteccBusWidth + move.l crt0_cpu_type,_AsteccCpuName + + jmp SYM(_Init68340) | Start C code (which never returns) + +/* + * Copy DATA segment, clear BSS segment, set up real stack, + * initialize heap, start C program. + * Assume that DATA and BSS sizes are multiples of 4. + */ + PUBLIC (_CopyDataClearBSSAndStart) +SYM(_CopyDataClearBSSAndStart): + lea copy_start,a0 | Get start of DATA in RAM + lea SYM(etext),a2 | Get start of DATA in ROM + cmpl a0,a2 | Are they the same? + beq.s NOCOPY | Yes, no copy necessary + lea copy_end,a1 | Get end of DATA in RAM + bra.s COPYLOOPTEST | Branch into copy loop +COPYLOOP: + movel a2@+,a0@+ | Copy word from ROM to RAM +COPYLOOPTEST: + cmpl a1,a0 | Done? + bcs.s COPYLOOP | No, skip +NOCOPY: + + lea clear_start,a0 | Get start of BSS + lea clear_end,a1 | Get end of BSS + clrl d0 | Value to set + bra.s ZEROLOOPTEST | Branch into clear loop +ZEROLOOP: + movel d0,a0@+ | Clear a word +ZEROLOOPTEST: + cmpl a1,a0 | Done? + bcs.s ZEROLOOP | No, skip + + movel #stack_init,a7 | set master stack pointer + movel d0,a7@- | environp + movel d0,a7@- | argv + movel d0,a7@- | argc + jsr SYM(boot_card) | Call C main + + PUBLIC (_mainDone) +SYM(_mainDone): + nop | Leave spot for breakpoint + movew #1,a7 | Force a double bus error + movel d0,a7@- | This should cause a RESET +/* stop #0x2700 | Stop with interrupts disabled */ + move.w #0x2700,sr + bra.s SYM(_mainDone) | Stuck forever + + .align 2 + PUBLIC (_HeapSize) +SYM (_HeapSize): + .long HeapSize + PUBLIC (_StackSize) +SYM (_StackSize): + .long StackSize +END_CODE + +BEGIN_DATA_DCL + .align 2 + PUBLIC (environ) +SYM (environ): + .long 0 + PUBLIC (_M68kSpuriousInterruptCount) +SYM (_M68kSpuriousInterruptCount): + .long 0 +END_DATA_DCL + +END + diff --git a/c/src/lib/libbsp/m68k/gen68340/start/start340.s b/c/src/lib/libbsp/m68k/gen68340/start/start340.s deleted file mode 100644 index 58ea0c92d0..0000000000 --- a/c/src/lib/libbsp/m68k/gen68340/start/start340.s +++ /dev/null @@ -1,874 +0,0 @@ -/* - * This file contains the entry point for the application. - * The name of this entry point is compiler dependent. - * It jumps to the BSP which is responsible for performing - * all initialization. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may in - * the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * Based on the `gen68360' board support package, and covered by the - * original distribution terms. - * - * Geoffroy Montel - * France Telecom - CNET/DSM/TAM/CAT - * 4, rue du Clos Courtel - * 35512 CESSON-SEVIGNE - * FRANCE - * - * e-mail: g_montel@yahoo.com - * - * $Id$ - */ - -#include "asm.h" -#include - -#define _OLD_ASTECC 1 /* old addresses for AST68340 only, undefine for AST68349 */ - -BEGIN_CODE - /* - * Step 1: Decide on Reset Stack Pointer and Initial Program Counter - */ -Entry: - .long SYM(m340)+1024 | 0: Initial SSP - .long start | 1: Initial PC - .long SYM(_uhoh) | 2: Bus error - .long SYM(_uhoh) | 3: Address error - .long SYM(_uhoh) | 4: Illegal instruction - .long SYM(_uhoh) | 5: Zero division - .long SYM(_uhoh) | 6: CHK, CHK2 instruction - .long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions - .long SYM(_uhoh) | 8: Privilege violation - .long SYM(_uhoh) | 9: Trace - .long SYM(_uhoh) | 10: Line 1010 emulator - .long SYM(_uhoh) | 11: Line 1111 emulator - .long SYM(_uhoh) | 12: Hardware breakpoint - .long SYM(_uhoh) | 13: Reserved for coprocessor violation - .long SYM(_uhoh) | 14: Format error - .long SYM(_uhoh) | 15: Uninitialized interrupt - .long SYM(_uhoh) | 16: Unassigned, reserved - .long SYM(_uhoh) | 17: - .long SYM(_uhoh) | 18: - .long SYM(_uhoh) | 19: - .long SYM(_uhoh) | 20: - .long SYM(_uhoh) | 21: - .long SYM(_uhoh) | 22: - .long SYM(_uhoh) | 23: - .long SYM(_spuriousInterrupt) | 24: Spurious interrupt - .long SYM(_uhoh) | 25: Level 1 interrupt autovector - .long SYM(_uhoh) | 26: Level 2 interrupt autovector - .long SYM(_uhoh) | 27: Level 3 interrupt autovector - .long SYM(_uhoh) | 28: Level 4 interrupt autovector - .long SYM(_uhoh) | 29: Level 5 interrupt autovector - .long SYM(_uhoh) | 30: Level 6 interrupt autovector - .long SYM(_uhoh) | 31: Level 7 interrupt autovector - .long SYM(_uhoh) | 32: Trap instruction (0-15) - .long SYM(_uhoh) | 33: - .long SYM(_uhoh) | 34: - .long SYM(_uhoh) | 35: - .long SYM(_uhoh) | 36: - .long SYM(_uhoh) | 37: - .long SYM(_uhoh) | 38: - .long SYM(_uhoh) | 39: - .long SYM(_uhoh) | 40: - .long SYM(_uhoh) | 41: - .long SYM(_uhoh) | 42: - .long SYM(_uhoh) | 43: - .long SYM(_uhoh) | 44: - .long SYM(_uhoh) | 45: - .long SYM(_uhoh) | 46: - .long SYM(_uhoh) | 47: - .long SYM(_uhoh) | 48: Reserved for coprocessor - .long SYM(_uhoh) | 49: - .long SYM(_uhoh) | 50: - .long SYM(_uhoh) | 51: - .long SYM(_uhoh) | 52: - .long SYM(_uhoh) | 53: - .long SYM(_uhoh) | 54: - .long SYM(_uhoh) | 55: - .long SYM(_uhoh) | 56: - .long SYM(_uhoh) | 57: - .long SYM(_uhoh) | 58: - .long SYM(_uhoh) | 59: Unassigned, reserved - .long SYM(_uhoh) | 60: - .long SYM(_uhoh) | 61: - .long SYM(_uhoh) | 62: - .long SYM(_uhoh) | 63: - .long SYM(_uhoh) | 64: User defined vectors (192) - .long SYM(_uhoh) | 65: - .long SYM(_uhoh) | 66: - .long SYM(_uhoh) | 67: - .long SYM(_uhoh) | 68: - .long SYM(_uhoh) | 69: - .long SYM(_uhoh) | 70: - .long SYM(_uhoh) | 71: - .long SYM(_uhoh) | 72: - .long SYM(_uhoh) | 73: - .long SYM(_uhoh) | 74: - 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152: - .long SYM(_uhoh) | 153: - .long SYM(_uhoh) | 154: - .long SYM(_uhoh) | 155: - .long SYM(_uhoh) | 156: - .long SYM(_uhoh) | 157: - .long SYM(_uhoh) | 158: - .long SYM(_uhoh) | 159: - .long SYM(_uhoh) | 160: - .long SYM(_uhoh) | 161: - .long SYM(_uhoh) | 162: - .long SYM(_uhoh) | 163: - .long SYM(_uhoh) | 164: - .long SYM(_uhoh) | 165: - .long SYM(_uhoh) | 166: - .long SYM(_uhoh) | 167: - .long SYM(_uhoh) | 168: - .long SYM(_uhoh) | 169: - .long SYM(_uhoh) | 170: - .long SYM(_uhoh) | 171: - .long SYM(_uhoh) | 172: - .long SYM(_uhoh) | 173: - .long SYM(_uhoh) | 174: - .long SYM(_uhoh) | 175: - .long SYM(_uhoh) | 176: - .long SYM(_uhoh) | 177: - .long SYM(_uhoh) | 178: - .long SYM(_uhoh) | 179: - .long SYM(_uhoh) | 180: - .long SYM(_uhoh) | 181: - .long SYM(_uhoh) | 182: - .long SYM(_uhoh) | 183: - .long SYM(_uhoh) | 184: - .long SYM(_uhoh) | 185: - .long SYM(_uhoh) | 186: - .long SYM(_uhoh) | 187: - .long SYM(_uhoh) | 188: - .long SYM(_uhoh) | 189: - .long SYM(_uhoh) | 190: - .long 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229: - .long SYM(_uhoh) | 230: - .long SYM(_uhoh) | 231: - .long SYM(_uhoh) | 232: - .long SYM(_uhoh) | 233: - .long SYM(_uhoh) | 234: - .long SYM(_uhoh) | 235: - .long SYM(_uhoh) | 236: - .long SYM(_uhoh) | 237: - .long SYM(_uhoh) | 238: - .long SYM(_uhoh) | 239: - .long SYM(_uhoh) | 240: - .long SYM(_uhoh) | 241: - .long SYM(_uhoh) | 242: - .long SYM(_uhoh) | 243: - .long SYM(_uhoh) | 244: - .long SYM(_uhoh) | 245: - .long SYM(_uhoh) | 246: - .long SYM(_uhoh) | 247: - .long SYM(_uhoh) | 248: - .long SYM(_uhoh) | 249: - .long SYM(_uhoh) | 250: - .long SYM(_uhoh) | 251: - .long SYM(_uhoh) | 252: - .long SYM(_uhoh) | 253: - .long SYM(_uhoh) | 254: - .long SYM(_uhoh) | 255: - -/* - * Default trap handler - * With an oscilloscope you can see AS* stop - */ - PUBLIC (_uhoh) -SYM(_uhoh): nop | Leave spot for breakpoint -/* stop #0x2700 | Stop with interrupts disabled */ - move.w #0x2700,sr - move.w (a7),_boot_panic_registers+4 | SR - move.l 2(a7),_boot_panic_registers | PC - move.w 6(a7),_boot_panic_registers+6 | format & vector - movem.l d0-d7/a0-a7, _boot_panic_registers+8 - movec sfc, d0 - movem.l d0, _boot_panic_registers+72 - movec dfc, d0 - movem.l d0, _boot_panic_registers+76 - movec vbr, d0 - movem.l d0, _boot_panic_registers+80 - jmp SYM(_dbug_dumpanic) - bra.s _crt0_cold_start - -/* - * Log, but otherwise ignore, spurious interrupts - */ - PUBLIC (_spuriousInterrupt) -SYM(_spuriousInterrupt): - addql #1,SYM(_M68kSpuriousInterruptCount) - rte - -/* - * Place the low-order 3 octets of the board's ethernet address at - * a `well-known' fixed location relative to the startup location. - */ - .align 2 - .word 0 | Padding -ethernet_address_buffer: - .word 0x08F3 | Default address - .word 0xDEAD - .word 0xCAFE - -BEGIN_DATA - -/* equates */ - -.equ _CPU340, 0x0 -.equ _CPU349, 0x31 - -#ifdef _OLD_ASTECC /* old addresses for AST68340 only */ -.equ _EPLD_CS_BASE, 0x1 -.equ _PROM_Start, 0x01000000 /* CS0 */ -.equ _FLEX_Start, 0x08000000 /* CS2 */ -.equ _I2C_Start, 0x0c000000 /* CS3 */ - -.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */ -.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */ - -.equ _ExtRam_Start, 0x10000000 /* SRAM */ -.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */ - -.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */ -.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */ - -#else /* new addresses for AST68349 and 68340 */ - -.equ _EPLD_CS_BASE, 0x5 -.equ _PROM_Start, 0x50000000 /* CS0 */ -.equ _FLEX_Start, 0x08000000 /* CS2 */ -.equ _I2C_Start, 0x0c000000 /* CS3 */ - -.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */ -.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */ - -.equ _ExtRam_Start, 0x80000000 /* DRAM */ -.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */ - -.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */ -.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */ -#endif - -.equ _SPEED349, 0xD680 /* 24 Mhz */ -.equ _SPEED340, 0xD700 /* 25 Mhz */ -/* .equ _SPEED340, 0xCE00 16 Mhz */ - -#define crt0_boot_type d0 /* cold/warm start (must be D0) */ -#define crt0_temp d1 -#define crt0_cpu_type d2 -#define crt0_csswitch d3 -#define crt0_buswidth d4 -#define crt0_pdcs d5 -#define crt0_spare6 d6 -#define crt0_spare7 d7 -#define crt0_sim_base a0 -#define crt0_glue a1 -#define crt0_dram a2 -#define crt0_ptr3 a3 -#define crt0_ptr4 a4 -#define crt0_ptr5 a5 -#define crt0_ptr6 a6 - -/* -- PDCS buffer equates -- */ -.equ pdcs_mask, 0x1F /* DRAM configuration */ -.equ pdcs_sw12, 7 /* switch 12 */ -.equ pdcs_sw11, 6 /* switch 11 */ -.equ pdcs_sw14, 5 /* switch 14 */ - -.equ bit_cache, pdcs_sw12 /* enable cache if on */ -.equ bit_meminit, pdcs_sw11 /* init memory if on */ - -/* -- Initialization stack and vars -- */ - -_AsteccBusWidth: ds.b 1 -_AsteccCsSwitch: ds.b 1 -_AsteccCpuName: ds.l 1 - -.align 4 - -_crt0_init_stack: - ds.l 500 -_crt0_init_stktop: - -/* -- Initialization code -- */ -BEGIN_CODE - -.align 4 - dc.l _crt0_init_stktop /* reset SP */ - dc.l _crt0_cold_start /* reset PC */ - dc.l _crt0_warm_start - - .ascii "BOOT XHM68K/Spectra for ASTECC 68349 and 68340 boards" - dc.w 0 -.align 4 - -.globl start -start: - -_crt0_cold_start: - moveq.l #0,crt0_boot_type | signal cold reset - bra.s _crt0_common_start - -_crt0_warm_start: - moveq.l #1,crt0_boot_type | signal warm reset - -_crt0_common_start: - move.w #0x2700,sr | disable interrupts and switch to interrupt mode - movea.l #_crt0_init_stktop,sp | set up initialization stack - - move.l #Entry,crt0_temp | VBR initialization - movec.l crt0_temp,vbr | - moveq.l #0x07,crt0_temp - movec.l crt0_temp,dfc | prepare access in CPU space - move.l #(BASE_SIM+0x111),crt0_temp | mask CPU, RESERVED USER SPACES - moves.l crt0_temp,BASE_REG | base initialization (must be MOVES, PCC-130795) - - movea.l #BASE_SIM,crt0_sim_base - - /* -- disable Bus Monitor -- */ - move.b #0,SIM_SYPCR(crt0_sim_base) | system protection control register - - /* -- enable A31-A24 -- */ - clr.b SIM_PPRA1(crt0_sim_base) - - /* -- show cycles, user acces to SIM, 4 /CS & 4 /IT -- */ - move.w #0x427F,SIM_MCR(crt0_sim_base) - - /* -- enable /IRQ3, 5, 6, 7 -- */ - move.b #0xE8,SIM_PPRB(crt0_sim_base) - - /* -- enable autovector on /IRQ7 -- */ - move.b #0x80,SIM_AVR(crt0_sim_base) - - /* -- test CPU type -- */ - cmp.b #_CPU349,SIM_IDR(crt0_sim_base) - bne cpu_is_68340 - -/*-------------------------------------------------------------------------------------------*/ -cpu_is_68349: - - /* -- set cpu clock -- */ - move.w #_SPEED349,SIM_SYNCR(crt0_sim_base) | clock - -sync_wait349: - btst.b #3,(SIM_SYNCR+1)(crt0_sim_base) - beq sync_wait349 - - /* to allow access to the EPLD internal registers, it is necessary - to disable the global chip-select /CS0 (which decodes every external - cycles). To do that, we initialize the 68349 internal RAM, - copy a part of the initialization code in it, and jump there. - from that moment, /CS0 is not used, therefore it can be initialized - with its default value. Its width may be incorrect, but it will be - adjusted later. The goal is to avoid any conflict with - the accesses to the EPLD registers. - When this is done, we read the RESET parameters (boot prom width - and chip-select switch) and proceed with the initialization - when all is done, we jump back to the boot prom now - decoded with a properly configured /CS0 */ - - /*-------------------------------------*/ - /* -- configure internal SRAM banks -- */ - - move.l #0x00000000,QDMM_MCR(crt0_sim_base) - move.l #_FastRam_Start+0x0005,QDMM_QBAR0(crt0_sim_base) - move.l #_FastRam_Start+0x0405,QDMM_QBAR1(crt0_sim_base) - move.l #_FastRam_Start+0x0805,QDMM_QBAR2(crt0_sim_base) - move.l #_FastRam_Start+0x0c05,QDMM_QBAR3(crt0_sim_base) - - /*--------------------------------------------------------*/ - /* -- copy to address of the 68349 initialization code -- */ - - lea.l _copy_start(%pc),crt0_ptr3 - lea.l _copy_end(%pc),crt0_ptr4 - move.l crt0_ptr4,crt0_temp - sub.l crt0_ptr3,crt0_temp - add.l #3,crt0_temp | adjust to next long word - lsr.l #2,crt0_temp - - move.l #_FastRam_Start,crt0_ptr4 -_copy_loop: - move.l (crt0_ptr3)+,(crt0_ptr4)+ - subq.l #1,crt0_temp - bne.s _copy_loop - bra.l _FastRam_Start | jump to code in internal RAM - - /*------------------------------------*/ - /* -- start of initialization code -- */ - -_copy_start: - bra.l _begin_68349_init - - /*----------------------------------------------------------*/ - /* Astecc 68349 board : chip-select initialization values */ - -_table_csepld: - dc.b (_EPLD_CS_BASE&0x0F)+0x80 | 16 bits, 0ws - dc.b 0x80 | 16 bits, 0 ws - dc.b 0x90 | 16 bits, ext /dsack - dc.b 0x90 | 16 bits, ext /dsack - -_table_cs349: - dc.l 0x003FFFF4 | Mask CS0 (4Mbytes PROM, 32bits, 1WS) - dc.l (_PROM_Start&0xFFFFFF00)+0x00000003 | Base CS0 - dc.l 0x003FFFF1 | MASK CS1 (4Mbytes RAM, 16bits, 0WS) - dc.l (_BCCram_Start&0xFFFFFF00)+0x00000003 | Base CS1 - dc.l 0x000000FF | MASK CS2 (FLEX, ext DTACK, 256 bytes) - dc.l (_FLEX_Start&0xFFFFFF00)+0x00000003 | Base CS2 - dc.l 0x000000FF | Mask CS3 (I2C, ext DTACK, 256 bytes) - dc.l (_I2C_Start&0xFFFFFF00)+0x00000003 | Base CS3 - - /*-------------------------------------------------*/ -_begin_68349_init: - - /*-------------------------------------------------*/ - /* 68349 chip select initialization - - at this stage, the width of /CS0 may be incorrect - it will be corrected later - */ - -_cs68349_init: - lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 - lea.l _table_cs349(%pc),crt0_ptr3 - - moveq.l #0x07,crt0_temp -_cs349_init2: - move.l (crt0_ptr3)+,(crt0_ptr4)+ - dbra crt0_temp,_cs349_init2 - - /*-----------------------------------------------*/ - /* -- prepare access to the internal registers --*/ - moveq.l #EPLD_SPACE,crt0_temp - movec.l crt0_temp,dfc - movec.l crt0_temp,sfc - move.l #GLUE_EPLD,crt0_glue - move.l #DRAM_EPLD,crt0_dram - - /*-------------------------------------------*/ - /* EPLD generated /CS[3..0] must be disabled */ - -_csepld_clear: - move.l crt0_glue,crt0_ptr4 - move.w #3,crt0_spare6 - clr.b crt0_temp - -_csepld_clear1: - moves.b crt0_temp,(crt0_ptr4)+ - dbra crt0_spare6,_csepld_clear1 - - /*---------------------------------------------------------*/ - /* -- get width of boot PROM, and active chip-select set --*/ - moves.b REG_BUSWIDTH(crt0_dram),crt0_csswitch - move.b crt0_csswitch,crt0_buswidth - - /* state of CS_SWITCH : sel == 0 => CPU chip_selects (/CS[3..0]) - : sel == 1 => EPLD chip_selects (/CS[3..0]) */ - and.b #1,crt0_csswitch - - /* bus width of /CS0 during reset bw[1..0] : 0 1 2 3 - bus width : 32 16 8 ext./dsackx */ - rol.b #2,crt0_buswidth - and.b #3,crt0_buswidth - - /*----------------------------------------------------*/ - /* -- configure chip select 0 with boot prom width -- */ - lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 - lea.l _table_cs349(%pc),crt0_ptr3 - move.l (crt0_ptr3)+,crt0_temp - and.b #0xFC,crt0_temp | clear PS0 & PS1 - or.b crt0_buswidth,crt0_temp | set boot PROM bus width - move.l crt0_temp,(crt0_ptr4)+ - - /*------------------------*/ - /* -- read PDCS buffer -- */ - moves.b REG_PDCS(crt0_glue),crt0_pdcs -/* move.b #0x3F,crt0_pdcs pour test */ - - - /*---------------------------------------*/ - /* -- EPLD chip-select initialization -- */ - /*---------------------------------------*/ - btst.b #0,crt0_csswitch - beq _cs_init_end - - /*--------------------------------------------*/ - /* 68349 generated /CS[3..0] must be disabled */ - lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 - lea.l _table_cs349(%pc),crt0_ptr3 - moveq.l #0x03,crt0_temp -_cs349_clear: - move.l (crt0_ptr3)+,(crt0_ptr4)+ - move.l (crt0_ptr3)+,crt0_spare6 - and.b #0xFE,crt0_spare6 | disable chip-select - move.l crt0_spare6,(crt0_ptr4)+ - dbra crt0_temp,_cs349_clear - - /*---------------------------------------------*/ - /* EPLD generated /CS[3..0] must be configured */ -_csepld_init: - move.l crt0_glue,crt0_ptr4 - lea.l _table_csepld(%pc),crt0_ptr3 - - move.b (crt0_ptr3)+,crt0_temp - or.b #0x20,crt0_temp | default width is 32 bits - tst.b crt0_buswidth | is boot PROM bus width 32 bits ? - beq _csepld1 | if not - and.b #0xDF,crt0_temp | set width to 16 bits -_csepld1: - moves.b crt0_temp,(crt0_ptr4)+ - - moveq.l #0x02,crt0_spare6 -_csepld2: - move.b (crt0_ptr3)+,crt0_temp - moves.b crt0_temp,(crt0_ptr4)+ - dbra crt0_spare6,_csepld2 - -_cs_init_end: - - /*--------------------------------------*/ - /* -- DRAM controller initialization -- */ -_dram_init: - move.w #15,crt0_temp - move.l #_ExtRam_Start,crt0_ptr3 - -_dram_init1: - clr.l (crt0_ptr3)+ | must access DRAM - dbra crt0_temp,_dram_init1 | prior to init refresh - -_dram_init2: - move.b #3,crt0_temp - moves.b crt0_temp,REG_WS(crt0_dram) | set 3 wait-states - - move.b #0x81,crt0_temp - moves.b crt0_temp,REG_REFRESH(crt0_dram) | refresh every 10µs - - move.b #0,crt0_temp - moves.b crt0_temp,REG_CONFIG(crt0_dram) | default size = 4Mbytes - - /*-----------------------*/ - /* -- configure cache -- */ -_init_cache: - move.l #0x000001E0,CACHE_MCR(crt0_sim_base) - btst.b #bit_cache,crt0_pdcs - bne _init_cache_end - or.l #0x00000001,CACHE_MCR(crt0_sim_base) - -_init_cache_end: - - /*-----------------------------*/ - /* -- timers initialization -- */ - - clr.b crt0_temp - moves.b crt0_temp,REG_TIMER1(crt0_glue) | disable timer 1 - moves.b crt0_temp,REG_TIMER2(crt0_glue) | disable timer 2 - - /*--------------------------*/ - /* -- I2C initialization -- */ - move.b #3,crt0_temp - moves.b crt0_temp,REG_I2C(crt0_glue) | tri-states I2C ports - - /*-----------------------------------------*/ - /* -- baudrate generator initialization -- */ - move.b #2,crt0_temp - moves.b crt0_temp,REG_BAUDRATE(crt0_glue) | baudrate = 38400 - - /*-------------------------------*/ - /* -- IO port initialization -- */ - clr.b crt0_temp - moves.b crt0_temp,REG_IO(crt0_glue) | set port as input - - /* -- */ - - move.l #68349,crt0_cpu_type - - - /* -- jump back to PROM -- */ - - jmp.l (_fill_test) | must be absolute long - -_copy_end: - -/*------------------------------------------------- - initialization code for the 68340 board - -------------------------------------------------*/ - - /* Astecc 68340 board : chip-select initialization values */ -_table_cs340: - dc.l 0x003FFFF0 /* Mask CS0 (4Mbytes PROM, 32bits, 0WS) */ - dc.l ((_PROM_Start&0xFFFFFF00)+0x00000003) /* Base CS0 */ - dc.l 0x0000FFFD /* MASK CS1 (RAMBCC340, 0WS, FTE) */ - dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000003) /* Base CS1 */ - dc.l 0x000000FF /* MASK CS2 (FLEX, ext DTACK, 256 bytes) */ - dc.l ((_FLEX_Start&0xFFFFFF00)+0x00000003) /* Base CS2 */ - dc.l 0x000000FF /* Mask CS3 (I2C, ext DTACK, 256 bytes) */ - dc.l ((_I2C_Start&0xFFFFFF00)+0x00000003) /* Base CS3 */ - -cpu_is_68340: - - /* -- set cpu clock -- */ - move.w #_SPEED340,SIM_SYNCR(crt0_sim_base) | clock -sync_wait340: - btst.b #3,(SIM_SYNCR+1)(crt0_sim_base) - beq sync_wait340 - - /* -- chip select initialization -- */ - lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 - lea.l _table_cs340(%pc),crt0_ptr3 - moveq.l #0x07,crt0_temp -_b_cs340: - move.l (crt0_ptr3)+,crt0_ptr5 - move.l crt0_ptr5,(crt0_ptr4)+ | pour test - dbra crt0_temp,_b_cs340 - - move.l #68340,crt0_cpu_type - move.b #0,crt0_csswitch | CPU - move.b #1,crt0_buswidth | 16 bits - - - /*------------------------------------------------- - fill RAM if COLDSTART - -------------------------------------------------*/ -_fill_test: - - tst.l crt0_boot_type - bne _dont_fill - - cmp.b #_CPU349,SIM_IDR(crt0_sim_base) - bne _fill - btst.b #bit_meminit,crt0_pdcs - bne _dont_fill - - /* fill main memory */ -_fill: - move.l #_crt0_init_stack,crt0_ptr3 | skip Astecc vars - move.l #_ExtRam_Start,crt0_temp - sub.l #_crt0_init_stack,crt0_temp - add.l #_ExtRam_Size,crt0_temp | get size - lsr.l #2,crt0_temp | ajust for long word -_fill_loop: - clr.l (crt0_ptr3)+ - subq.l #1,crt0_temp - bne _fill_loop - - cmp.b #_CPU349,SIM_IDR(crt0_sim_base) - bne _fill_bccram - - /* fill QDMM memory */ - movea.l #_FastRam_Start,crt0_ptr3 | get start - move.l #_FastRam_Size,crt0_temp | get size - lsr.l #2,crt0_temp | ajust for long word - -_QDMMfill_loop: - clr.l (crt0_ptr3)+ - subq.l #1,crt0_temp - bne _QDMMfill_loop - bra _dont_fill - - /* fill BCC memory */ -_fill_bccram: - movea.l #_BCCram_Start,crt0_ptr3 | get start - move.l #_BCCram_Size,crt0_temp | get size - lsr.l #2,crt0_temp | ajust for long word -_BCCfill_loop: - clr.l (crt0_ptr3)+ - subq.l #1,crt0_temp - bne _BCCfill_loop - - *-------------------------------------------------*/ -_dont_fill: - move.b crt0_csswitch,_AsteccCsSwitch - move.b crt0_buswidth,_AsteccBusWidth - move.l crt0_cpu_type,_AsteccCpuName - - jmp SYM(_Init68340) | Start C code (which never returns) - -/* - * Copy DATA segment, clear BSS segment, set up real stack, - * initialize heap, start C program. - * Assume that DATA and BSS sizes are multiples of 4. - */ - PUBLIC (_CopyDataClearBSSAndStart) -SYM(_CopyDataClearBSSAndStart): - lea copy_start,a0 | Get start of DATA in RAM - lea SYM(etext),a2 | Get start of DATA in ROM - cmpl a0,a2 | Are they the same? - beq.s NOCOPY | Yes, no copy necessary - lea copy_end,a1 | Get end of DATA in RAM - bra.s COPYLOOPTEST | Branch into copy loop -COPYLOOP: - movel a2@+,a0@+ | Copy word from ROM to RAM -COPYLOOPTEST: - cmpl a1,a0 | Done? - bcs.s COPYLOOP | No, skip -NOCOPY: - - lea clear_start,a0 | Get start of BSS - lea clear_end,a1 | Get end of BSS - clrl d0 | Value to set - bra.s ZEROLOOPTEST | Branch into clear loop -ZEROLOOP: - movel d0,a0@+ | Clear a word -ZEROLOOPTEST: - cmpl a1,a0 | Done? - bcs.s ZEROLOOP | No, skip - - movel #stack_init,a7 | set master stack pointer - movel d0,a7@- | environp - movel d0,a7@- | argv - movel d0,a7@- | argc - jsr SYM(boot_card) | Call C main - - PUBLIC (_mainDone) -SYM(_mainDone): - nop | Leave spot for breakpoint - movew #1,a7 | Force a double bus error - movel d0,a7@- | This should cause a RESET -/* stop #0x2700 | Stop with interrupts disabled */ - move.w #0x2700,sr - bra.s SYM(_mainDone) | Stuck forever - - .align 2 - PUBLIC (_HeapSize) -SYM (_HeapSize): - .long HeapSize - PUBLIC (_StackSize) -SYM (_StackSize): - .long StackSize -END_CODE - -BEGIN_DATA_DCL - .align 2 - PUBLIC (environ) -SYM (environ): - .long 0 - PUBLIC (_M68kSpuriousInterruptCount) -SYM (_M68kSpuriousInterruptCount): - .long 0 -END_DATA_DCL - -END - diff --git a/c/src/lib/libbsp/m68k/gen68340/start/startfor340only.S b/c/src/lib/libbsp/m68k/gen68340/start/startfor340only.S new file mode 100644 index 0000000000..930694f02e --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68340/start/startfor340only.S @@ -0,0 +1,499 @@ +/* + * This file contains the entry point for the application. + * The name of this entry point is compiler dependent. + * It jumps to the BSP which is responsible for performing + * all initialization. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * Based on the `gen68360' board support package, and covered by the + * original distribution terms. + * + * Geoffroy Montel + * France Telecom - CNET/DSM/TAM/CAT + * 4, rue du Clos Courtel + * 35512 CESSON-SEVIGNE + * FRANCE + * + * e-mail: g_montel@yahoo.com + * + * $Id$ + */ + +#include "asm.h" +#include + +BEGIN_CODE + /* + * Step 1: Decide on Reset Stack Pointer and Initial Program Counter + */ +Entry: + .long SYM(m340)+1024 | 0: Initial SSP + .long start | 1: Initial PC + .long SYM(_uhoh) | 2: Bus error + .long SYM(_uhoh) | 3: Address error + .long SYM(_uhoh) | 4: Illegal instruction + .long SYM(_uhoh) | 5: Zero division + .long SYM(_uhoh) | 6: CHK, CHK2 instruction + .long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions + .long SYM(_uhoh) | 8: Privilege violation + .long SYM(_uhoh) | 9: Trace + .long SYM(_uhoh) | 10: Line 1010 emulator + .long SYM(_uhoh) | 11: Line 1111 emulator + .long SYM(_uhoh) | 12: Hardware breakpoint + .long SYM(_uhoh) | 13: Reserved for coprocessor violation + .long SYM(_uhoh) | 14: Format error + .long SYM(_uhoh) | 15: Uninitialized interrupt + .long SYM(_uhoh) | 16: Unassigned, reserved + .long SYM(_uhoh) | 17: + .long SYM(_uhoh) | 18: + .long SYM(_uhoh) | 19: + .long SYM(_uhoh) | 20: + .long SYM(_uhoh) | 21: + .long SYM(_uhoh) | 22: + .long SYM(_uhoh) | 23: + .long SYM(_spuriousInterrupt) | 24: Spurious interrupt + .long SYM(_uhoh) | 25: Level 1 interrupt autovector + .long SYM(_uhoh) | 26: Level 2 interrupt autovector + .long SYM(_uhoh) | 27: Level 3 interrupt autovector + .long SYM(_uhoh) | 28: Level 4 interrupt autovector + .long SYM(_uhoh) | 29: Level 5 interrupt autovector + .long SYM(_uhoh) | 30: Level 6 interrupt autovector + .long SYM(_uhoh) | 31: Level 7 interrupt autovector + .long SYM(_uhoh) | 32: Trap instruction (0-15) + .long SYM(_uhoh) | 33: + .long SYM(_uhoh) | 34: + .long SYM(_uhoh) | 35: + .long SYM(_uhoh) | 36: + .long SYM(_uhoh) | 37: + .long SYM(_uhoh) | 38: + .long SYM(_uhoh) | 39: + .long SYM(_uhoh) | 40: + .long SYM(_uhoh) | 41: + .long SYM(_uhoh) | 42: + .long SYM(_uhoh) | 43: + .long SYM(_uhoh) | 44: + .long SYM(_uhoh) | 45: + .long SYM(_uhoh) | 46: + .long SYM(_uhoh) | 47: + .long SYM(_uhoh) | 48: Reserved for coprocessor + .long SYM(_uhoh) | 49: + .long SYM(_uhoh) | 50: + .long SYM(_uhoh) | 51: + .long SYM(_uhoh) | 52: + .long SYM(_uhoh) | 53: + .long SYM(_uhoh) | 54: + .long SYM(_uhoh) | 55: + .long SYM(_uhoh) | 56: + .long SYM(_uhoh) | 57: + .long SYM(_uhoh) | 58: + .long SYM(_uhoh) | 59: Unassigned, reserved + .long SYM(_uhoh) | 60: + .long SYM(_uhoh) | 61: + .long SYM(_uhoh) | 62: + .long SYM(_uhoh) | 63: + .long SYM(_uhoh) | 64: User defined vectors (192) + .long SYM(_uhoh) | 65: + .long SYM(_uhoh) | 66: + .long SYM(_uhoh) | 67: + .long SYM(_uhoh) | 68: + .long SYM(_uhoh) | 69: + .long SYM(_uhoh) | 70: + .long SYM(_uhoh) | 71: + .long SYM(_uhoh) | 72: + .long SYM(_uhoh) | 73: + .long SYM(_uhoh) | 74: + .long SYM(_uhoh) | 75: + .long SYM(_uhoh) | 76: + .long SYM(_uhoh) | 77: + .long SYM(_uhoh) | 78: + .long SYM(_uhoh) | 79: + .long SYM(_uhoh) | 80: + .long SYM(_uhoh) | 81: + .long SYM(_uhoh) | 82: + .long SYM(_uhoh) | 83: + .long SYM(_uhoh) | 84: + .long SYM(_uhoh) | 85: + .long SYM(_uhoh) | 86: + .long SYM(_uhoh) | 87: + .long SYM(_uhoh) | 88: + .long SYM(_uhoh) | 89: + .long SYM(_uhoh) | 90: + .long SYM(_uhoh) | 91: + .long SYM(_uhoh) | 92: + .long SYM(_uhoh) | 93: + .long SYM(_uhoh) | 94: + .long SYM(_uhoh) | 95: + .long SYM(_uhoh) | 96: + .long SYM(_uhoh) | 97: + .long SYM(_uhoh) | 98: + .long SYM(_uhoh) | 99: + .long SYM(_uhoh) | 100: + .long SYM(_uhoh) | 101: + .long SYM(_uhoh) | 102: + .long SYM(_uhoh) | 103: + .long SYM(_uhoh) | 104: + .long SYM(_uhoh) | 105: + .long SYM(_uhoh) | 106: + .long SYM(_uhoh) | 107: + .long SYM(_uhoh) | 108: + .long SYM(_uhoh) | 109: + .long SYM(_uhoh) | 110: + .long SYM(_uhoh) | 111: + .long SYM(_uhoh) | 112: + .long SYM(_uhoh) | 113: + .long SYM(_uhoh) | 114: + .long SYM(_uhoh) | 115: + .long SYM(_uhoh) | 116: + .long SYM(_uhoh) | 117: + .long SYM(_uhoh) | 118: + .long SYM(_uhoh) | 119: + .long SYM(_uhoh) | 120: + .long SYM(_uhoh) | 121: + .long SYM(_uhoh) | 122: + .long SYM(_uhoh) | 123: + .long SYM(_uhoh) | 124: + .long SYM(_uhoh) | 125: + .long SYM(_uhoh) | 126: + .long SYM(_uhoh) | 127: + .long SYM(_uhoh) | 128: + .long SYM(_uhoh) | 129: + .long SYM(_uhoh) | 130: + .long SYM(_uhoh) | 131: + .long SYM(_uhoh) | 132: + .long SYM(_uhoh) | 133: + .long SYM(_uhoh) | 134: + .long SYM(_uhoh) | 135: + .long SYM(_uhoh) | 136: + .long SYM(_uhoh) | 137: + .long SYM(_uhoh) | 138: + .long SYM(_uhoh) | 139: + .long SYM(_uhoh) | 140: + .long SYM(_uhoh) | 141: + .long SYM(_uhoh) | 142: + .long SYM(_uhoh) | 143: + .long SYM(_uhoh) | 144: + .long SYM(_uhoh) | 145: + .long SYM(_uhoh) | 146: + .long SYM(_uhoh) | 147: + .long SYM(_uhoh) | 148: + .long SYM(_uhoh) | 149: + .long SYM(_uhoh) | 150: + .long SYM(_uhoh) | 151: + .long SYM(_uhoh) | 152: + .long SYM(_uhoh) | 153: + .long SYM(_uhoh) | 154: + .long SYM(_uhoh) | 155: + .long SYM(_uhoh) | 156: + .long SYM(_uhoh) | 157: + .long SYM(_uhoh) | 158: + .long SYM(_uhoh) | 159: + .long SYM(_uhoh) | 160: + .long SYM(_uhoh) | 161: + .long SYM(_uhoh) | 162: + .long SYM(_uhoh) | 163: + .long SYM(_uhoh) | 164: + .long SYM(_uhoh) | 165: + .long SYM(_uhoh) | 166: + .long SYM(_uhoh) | 167: + .long SYM(_uhoh) | 168: + .long SYM(_uhoh) | 169: + .long SYM(_uhoh) | 170: + .long SYM(_uhoh) | 171: + .long SYM(_uhoh) | 172: + .long SYM(_uhoh) | 173: + .long SYM(_uhoh) | 174: + .long SYM(_uhoh) | 175: + .long SYM(_uhoh) | 176: + .long SYM(_uhoh) | 177: + .long SYM(_uhoh) | 178: + .long SYM(_uhoh) | 179: + .long SYM(_uhoh) | 180: + .long SYM(_uhoh) | 181: + .long SYM(_uhoh) | 182: + .long SYM(_uhoh) | 183: + .long SYM(_uhoh) | 184: + .long SYM(_uhoh) | 185: + .long SYM(_uhoh) | 186: + .long SYM(_uhoh) | 187: + .long SYM(_uhoh) | 188: + .long SYM(_uhoh) | 189: + .long SYM(_uhoh) | 190: + .long SYM(_uhoh) | 191: + .long SYM(_uhoh) | 192: + .long SYM(_uhoh) | 193: + .long SYM(_uhoh) | 194: + .long SYM(_uhoh) | 195: + .long SYM(_uhoh) | 196: + .long SYM(_uhoh) | 197: + .long SYM(_uhoh) | 198: + .long SYM(_uhoh) | 199: + .long SYM(_uhoh) | 200: + .long SYM(_uhoh) | 201: + .long SYM(_uhoh) | 202: + .long SYM(_uhoh) | 203: + .long SYM(_uhoh) | 204: + .long SYM(_uhoh) | 205: + .long SYM(_uhoh) | 206: + .long SYM(_uhoh) | 207: + .long SYM(_uhoh) | 208: + .long SYM(_uhoh) | 209: + .long SYM(_uhoh) | 210: + .long SYM(_uhoh) | 211: + .long SYM(_uhoh) | 212: + .long SYM(_uhoh) | 213: + .long SYM(_uhoh) | 214: + .long SYM(_uhoh) | 215: + .long SYM(_uhoh) | 216: + .long SYM(_uhoh) | 217: + .long SYM(_uhoh) | 218: + .long SYM(_uhoh) | 219: + .long SYM(_uhoh) | 220: + .long SYM(_uhoh) | 221: + .long SYM(_uhoh) | 222: + .long SYM(_uhoh) | 223: + .long SYM(_uhoh) | 224: + .long SYM(_uhoh) | 225: + .long SYM(_uhoh) | 226: + .long SYM(_uhoh) | 227: + .long SYM(_uhoh) | 228: + .long SYM(_uhoh) | 229: + .long SYM(_uhoh) | 230: + .long SYM(_uhoh) | 231: + .long SYM(_uhoh) | 232: + .long SYM(_uhoh) | 233: + .long SYM(_uhoh) | 234: + .long SYM(_uhoh) | 235: + .long SYM(_uhoh) | 236: + .long SYM(_uhoh) | 237: + .long SYM(_uhoh) | 238: + .long SYM(_uhoh) | 239: + .long SYM(_uhoh) | 240: + .long SYM(_uhoh) | 241: + .long SYM(_uhoh) | 242: + .long SYM(_uhoh) | 243: + .long SYM(_uhoh) | 244: + .long SYM(_uhoh) | 245: + .long SYM(_uhoh) | 246: + .long SYM(_uhoh) | 247: + .long SYM(_uhoh) | 248: + .long SYM(_uhoh) | 249: + .long SYM(_uhoh) | 250: + .long SYM(_uhoh) | 251: + .long SYM(_uhoh) | 252: + .long SYM(_uhoh) | 253: + .long SYM(_uhoh) | 254: + .long SYM(_uhoh) | 255: + +/* + * Default trap handler + * With an oscilloscope you can see AS* stop + */ + PUBLIC (_uhoh) +SYM(_uhoh): nop | Leave spot for breakpoint + stop #0x2700 | Stop with interrupts disabled + bra.s SYM(_uhoh) | Stuck forever + +/* + * Log, but otherwise ignore, spurious interrupts + */ + PUBLIC (_spuriousInterrupt) +SYM(_spuriousInterrupt): + addql #1,SYM(_M68kSpuriousInterruptCount) + rte + +/* + * Place the low-order 3 octets of the board's ethernet address at + * a `well-known' fixed location relative to the startup location. + */ + .align 2 + .word 0 | Padding +ethernet_address_buffer: + .word 0x08F3 | Default address + .word 0xDEAD + .word 0xCAFE + +/* -- equates -- */ +.equ _PROM_Start, 0x01000000 /* CS0 */ +.equ _BCCram_Start, 0x00000000 /* CS1 */ +.equ _FLEX_Start, 0x08000000 /* CS2 */ +.equ _I2C_Start, 0x02000000 /* CS3 */ +.equ _EXTram_Start, 0x10000000 /* CS4 */ +.equ _EXTram_Size, 0x000400000 /* 4 Mbytes */ +.equ _SPEED, 0xD780 /* 25 Mhz CPU349 */ +/* .equ _SPEED, 0xD700 25 Mhz */ +/* .equ _SPEED, 0xCE00 16 Mhz */ + +BEGIN_DATA + +_crt0_init_stack: + ds.l 0x1000 +_crt0_init_stktop: + + +BEGIN_CODE + dc.l _crt0_init_stktop /* reset SP */ + dc.l _crt0_cold_start /* reset PC */ + dc.l _crt0_warm_start + + .ascii "RTEMS" + dc.w 0 + +.align 2 + +_table_cs: + /* carte Astecc - 68340 */ + dc.l 0x003FFFF0 /* Mask CS0 (4Mbytes PROM, 32bits, 0WS) */ +/* dc.l 0x003FFFFD Mask CS0 (4Mbytes PROM, 16bits, 3WS) */ + dc.l ((_PROM_Start&0xFFFFFF00)+0x00000003) /* Base CS0 */ +/* dc.l 0x0000FFF1 MASK CS1 (RAMBCC340, 0WS, FTE) */ + dc.l 0x0000FFFD /* MASK CS1 (RAMBCC340, 0WS, FTE) */ +/* dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000007) Base CS1 */ + dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000003) /* Base CS1 */ + dc.l 0x000000FF /* MASK CS2 (FLEX, ext DTACK, 256 bytes) */ + dc.l ((_FLEX_Start&0xFFFFFF00)+0x00000003) /* Base CS2 */ + dc.l 0x000000FF /* Mask CS3 (I2C, ext DTACK, 256 bytes) */ + dc.l ((_I2C_Start&0xFFFFFF00)+0x00000003) /* Base CS3 */ + +/* + * Initial PC + */ +.globl start +start: + +_crt0_cold_start: + moveq.l #0,d0 /* signal cold reset */ + bra.s _crt0_common_start + +_crt0_warm_start: + moveq.l #1,d0 /* signal warm reset */ + +_crt0_common_start: + move.w #0x2700,sr /* disable interrupts and switch to interrupt mode */ + movea.l #_crt0_init_stktop,sp /* set up initialization stack */ + + lea Entry,a0 /* Get base of vector table */ + movec a0,vbr /* Set up the VBR */ + + moveq.l #0x07,d1 + movec.l d1,dfc /* prepare access in CPU space */ + move.l #(BASE_SIM+1),d1 + moves.l d1,BASE_REG /* base initialization (must be MOVES, PCC-130795) */ + moveq.l #0x05,d1 + movec.l d1,dfc + + movea.l #BASE_SIM,a0 + + /* -- disable Bus Monitor -- */ + move.b #0,SIM_SYPCR(a0) /* system protection control register */ + + /* -- set frequency to 25.16 Mhz -- */ + move.w #_SPEED,SIM_SYNCR(a0) /* clock */ + +sync_wait: + btst.b #3,(SIM_SYNCR+1)(a0) + beq sync_wait + + /* -- enable A31-A24 -- */ + clr.b SIM_PPRA1(a0) + + /* -- show cycles, user acces to SIM, 4 /CS & 4 /IT -- */ + move.w #0x427F,SIM_MCR(a0) + + /* -- chip select initialization -- */ + lea.l SIM_MASKH0(a0),a2 + lea.l _table_cs(%pc),a1 + + moveq.l #0x07,d1 + +_b_cs: + move.l (a1)+, (a2)+ + dbra d1,_b_cs + + /* fill RAM if COLDSTART */ + tst.l d0 + bne _dont_fill + + movea.l #_EXTram_Start,a0 /* get start */ + move.l #_EXTram_Size,d1 /* get size */ + lsr.l #2,d1 /* ajust for long word */ + +_fill_loop: + clr.l (a0)+ + subq.l #1,d1 + bne _fill_loop + +_dont_fill: + jmp SYM(_Init68340) | Start C code (which never returns) + +/* + * Copy DATA segment, clear BSS segment, set up real stack, + * initialize heap, start C program. + * Assume that DATA and BSS sizes are multiples of 4. + */ + PUBLIC (_CopyDataClearBSSAndStart) +SYM(_CopyDataClearBSSAndStart): + lea copy_start,a0 | Get start of DATA in RAM + lea SYM(etext),a2 | Get start of DATA in ROM + cmpl a0,a2 | Are they the same? + beq.s NOCOPY | Yes, no copy necessary + lea copy_end,a1 | Get end of DATA in RAM + bra.s COPYLOOPTEST | Branch into copy loop +COPYLOOP: + movel a2@+,a0@+ | Copy word from ROM to RAM +COPYLOOPTEST: + cmpl a1,a0 | Done? + bcs.s COPYLOOP | No, skip +NOCOPY: + + lea clear_start,a0 | Get start of BSS + lea clear_end,a1 | Get end of BSS + clrl d0 | Value to set + bra.s ZEROLOOPTEST | Branch into clear loop +ZEROLOOP: + movel d0,a0@+ | Clear a word +ZEROLOOPTEST: + cmpl a1,a0 | Done? + bcs.s ZEROLOOP | No, skip + + movel #stack_init,a7 | set master stack pointer + movel d0,a7@- | environp + movel d0,a7@- | argv + movel d0,a7@- | argc + jsr SYM(boot_card) | Call C main + + PUBLIC (_mainDone) +SYM(_mainDone): + nop | Leave spot for breakpoint + movew #1,a7 | Force a double bus error + movel d0,a7@- | This should cause a RESET + stop #0x2700 | Stop with interrupts disabled + bra.s SYM(_mainDone) | Stuck forever + + .align 2 + PUBLIC (_HeapSize) +SYM (_HeapSize): + .long HeapSize + PUBLIC (_StackSize) +SYM (_StackSize): + .long StackSize +END_CODE + +BEGIN_DATA_DCL + .align 2 + PUBLIC (environ) +SYM (environ): + .long 0 + PUBLIC (_M68kSpuriousInterruptCount) +SYM (_M68kSpuriousInterruptCount): + .long 0 +END_DATA_DCL + +END + diff --git a/c/src/lib/libbsp/m68k/gen68340/start/startfor340only.s b/c/src/lib/libbsp/m68k/gen68340/start/startfor340only.s deleted file mode 100644 index 930694f02e..0000000000 --- a/c/src/lib/libbsp/m68k/gen68340/start/startfor340only.s +++ /dev/null @@ -1,499 +0,0 @@ -/* - * This file contains the entry point for the application. - * The name of this entry point is compiler dependent. - * It jumps to the BSP which is responsible for performing - * all initialization. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may in - * the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * Based on the `gen68360' board support package, and covered by the - * original distribution terms. - * - * Geoffroy Montel - * France Telecom - CNET/DSM/TAM/CAT - * 4, rue du Clos Courtel - * 35512 CESSON-SEVIGNE - * FRANCE - * - * e-mail: g_montel@yahoo.com - * - * $Id$ - */ - -#include "asm.h" -#include - -BEGIN_CODE - /* - * Step 1: Decide on Reset Stack Pointer and Initial Program Counter - */ -Entry: - .long SYM(m340)+1024 | 0: Initial SSP - .long start | 1: Initial PC - .long SYM(_uhoh) | 2: Bus error - .long SYM(_uhoh) | 3: Address error - .long SYM(_uhoh) | 4: Illegal instruction - .long SYM(_uhoh) | 5: Zero division - .long SYM(_uhoh) | 6: CHK, CHK2 instruction - .long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions - .long SYM(_uhoh) | 8: Privilege violation - .long SYM(_uhoh) | 9: Trace - .long SYM(_uhoh) | 10: Line 1010 emulator - .long SYM(_uhoh) | 11: Line 1111 emulator - .long SYM(_uhoh) | 12: Hardware breakpoint - .long SYM(_uhoh) | 13: Reserved for coprocessor violation - .long SYM(_uhoh) | 14: Format error - .long SYM(_uhoh) | 15: Uninitialized interrupt - .long SYM(_uhoh) | 16: Unassigned, reserved - .long SYM(_uhoh) | 17: - .long SYM(_uhoh) | 18: - .long SYM(_uhoh) | 19: - .long SYM(_uhoh) | 20: - .long SYM(_uhoh) | 21: - .long SYM(_uhoh) | 22: - .long SYM(_uhoh) | 23: - .long SYM(_spuriousInterrupt) | 24: Spurious interrupt - .long SYM(_uhoh) | 25: Level 1 interrupt autovector - .long SYM(_uhoh) | 26: Level 2 interrupt autovector - .long SYM(_uhoh) | 27: Level 3 interrupt autovector - .long SYM(_uhoh) | 28: Level 4 interrupt autovector - .long SYM(_uhoh) | 29: Level 5 interrupt autovector - .long SYM(_uhoh) | 30: Level 6 interrupt autovector - .long SYM(_uhoh) | 31: Level 7 interrupt autovector - .long SYM(_uhoh) | 32: Trap instruction (0-15) - .long SYM(_uhoh) | 33: - .long SYM(_uhoh) | 34: - .long SYM(_uhoh) | 35: - .long SYM(_uhoh) | 36: - .long SYM(_uhoh) | 37: - .long SYM(_uhoh) | 38: - .long SYM(_uhoh) | 39: - .long SYM(_uhoh) | 40: - .long SYM(_uhoh) | 41: - .long SYM(_uhoh) | 42: - .long SYM(_uhoh) | 43: - .long SYM(_uhoh) | 44: - .long SYM(_uhoh) | 45: - .long SYM(_uhoh) | 46: - .long SYM(_uhoh) | 47: - .long SYM(_uhoh) | 48: Reserved for coprocessor - .long SYM(_uhoh) | 49: - .long SYM(_uhoh) | 50: - .long SYM(_uhoh) | 51: - .long SYM(_uhoh) | 52: - .long SYM(_uhoh) | 53: - .long SYM(_uhoh) | 54: - .long SYM(_uhoh) | 55: - .long SYM(_uhoh) | 56: - .long SYM(_uhoh) | 57: - .long SYM(_uhoh) | 58: - .long SYM(_uhoh) | 59: Unassigned, reserved - .long SYM(_uhoh) | 60: - .long SYM(_uhoh) | 61: - .long SYM(_uhoh) | 62: - .long SYM(_uhoh) | 63: - .long SYM(_uhoh) | 64: User defined vectors (192) - .long SYM(_uhoh) | 65: - .long SYM(_uhoh) | 66: - .long SYM(_uhoh) | 67: - .long SYM(_uhoh) | 68: - .long SYM(_uhoh) | 69: - .long SYM(_uhoh) | 70: - .long SYM(_uhoh) | 71: - .long SYM(_uhoh) | 72: - .long SYM(_uhoh) | 73: - .long SYM(_uhoh) | 74: - .long SYM(_uhoh) | 75: - .long SYM(_uhoh) | 76: - .long SYM(_uhoh) | 77: - .long SYM(_uhoh) | 78: - .long SYM(_uhoh) | 79: - .long SYM(_uhoh) | 80: - .long SYM(_uhoh) | 81: - .long SYM(_uhoh) | 82: - .long SYM(_uhoh) | 83: - .long SYM(_uhoh) | 84: - .long SYM(_uhoh) | 85: - .long SYM(_uhoh) | 86: - .long SYM(_uhoh) | 87: - .long SYM(_uhoh) | 88: - .long SYM(_uhoh) | 89: - .long SYM(_uhoh) | 90: - .long SYM(_uhoh) | 91: - .long SYM(_uhoh) | 92: - .long SYM(_uhoh) | 93: - .long SYM(_uhoh) | 94: - .long SYM(_uhoh) | 95: - .long SYM(_uhoh) | 96: - .long SYM(_uhoh) | 97: - .long SYM(_uhoh) | 98: - .long SYM(_uhoh) | 99: - .long SYM(_uhoh) | 100: - .long SYM(_uhoh) | 101: - .long SYM(_uhoh) | 102: - .long SYM(_uhoh) | 103: - .long SYM(_uhoh) | 104: - .long SYM(_uhoh) | 105: - .long SYM(_uhoh) | 106: - .long SYM(_uhoh) | 107: - .long SYM(_uhoh) | 108: - .long SYM(_uhoh) | 109: - .long SYM(_uhoh) | 110: - .long SYM(_uhoh) | 111: - .long SYM(_uhoh) | 112: - .long SYM(_uhoh) | 113: - .long SYM(_uhoh) | 114: - .long SYM(_uhoh) | 115: - .long SYM(_uhoh) | 116: - .long SYM(_uhoh) | 117: - .long SYM(_uhoh) | 118: - .long SYM(_uhoh) | 119: - .long SYM(_uhoh) | 120: - .long SYM(_uhoh) | 121: - .long SYM(_uhoh) | 122: - .long SYM(_uhoh) | 123: - .long SYM(_uhoh) | 124: - .long SYM(_uhoh) | 125: - .long SYM(_uhoh) | 126: - .long SYM(_uhoh) | 127: - .long SYM(_uhoh) | 128: - .long SYM(_uhoh) | 129: - .long SYM(_uhoh) | 130: - .long SYM(_uhoh) | 131: - .long SYM(_uhoh) | 132: - .long SYM(_uhoh) | 133: - .long SYM(_uhoh) | 134: - .long SYM(_uhoh) | 135: - .long SYM(_uhoh) | 136: - .long SYM(_uhoh) | 137: - .long SYM(_uhoh) | 138: - .long SYM(_uhoh) | 139: - .long SYM(_uhoh) | 140: - .long SYM(_uhoh) | 141: - .long SYM(_uhoh) | 142: - .long SYM(_uhoh) | 143: - .long SYM(_uhoh) | 144: - .long SYM(_uhoh) | 145: - .long SYM(_uhoh) | 146: - .long SYM(_uhoh) | 147: - .long SYM(_uhoh) | 148: - .long SYM(_uhoh) | 149: - .long SYM(_uhoh) | 150: - .long SYM(_uhoh) | 151: - .long SYM(_uhoh) | 152: - .long SYM(_uhoh) | 153: - .long SYM(_uhoh) | 154: - .long SYM(_uhoh) | 155: - .long SYM(_uhoh) | 156: - .long SYM(_uhoh) | 157: - .long SYM(_uhoh) | 158: - .long SYM(_uhoh) | 159: - .long SYM(_uhoh) | 160: - .long SYM(_uhoh) | 161: - .long SYM(_uhoh) | 162: - .long SYM(_uhoh) | 163: - .long SYM(_uhoh) | 164: - .long SYM(_uhoh) | 165: - .long SYM(_uhoh) | 166: - .long SYM(_uhoh) | 167: - .long SYM(_uhoh) | 168: - .long SYM(_uhoh) | 169: - .long SYM(_uhoh) | 170: - .long SYM(_uhoh) | 171: - .long SYM(_uhoh) | 172: - .long SYM(_uhoh) | 173: - .long SYM(_uhoh) | 174: - .long SYM(_uhoh) | 175: - .long SYM(_uhoh) | 176: - .long SYM(_uhoh) | 177: - .long SYM(_uhoh) | 178: - .long SYM(_uhoh) | 179: - .long SYM(_uhoh) | 180: - .long SYM(_uhoh) | 181: - .long SYM(_uhoh) | 182: - .long SYM(_uhoh) | 183: - .long SYM(_uhoh) | 184: - .long SYM(_uhoh) | 185: - .long SYM(_uhoh) | 186: - .long SYM(_uhoh) | 187: - .long SYM(_uhoh) | 188: - .long SYM(_uhoh) | 189: - .long SYM(_uhoh) | 190: - .long SYM(_uhoh) | 191: - .long SYM(_uhoh) | 192: - .long SYM(_uhoh) | 193: - .long SYM(_uhoh) | 194: - .long SYM(_uhoh) | 195: - .long SYM(_uhoh) | 196: - .long SYM(_uhoh) | 197: - .long SYM(_uhoh) | 198: - .long SYM(_uhoh) | 199: - .long SYM(_uhoh) | 200: - .long SYM(_uhoh) | 201: - .long SYM(_uhoh) | 202: - .long SYM(_uhoh) | 203: - .long SYM(_uhoh) | 204: - .long SYM(_uhoh) | 205: - .long SYM(_uhoh) | 206: - .long SYM(_uhoh) | 207: - .long SYM(_uhoh) | 208: - .long SYM(_uhoh) | 209: - .long SYM(_uhoh) | 210: - .long SYM(_uhoh) | 211: - .long SYM(_uhoh) | 212: - .long SYM(_uhoh) | 213: - .long SYM(_uhoh) | 214: - .long SYM(_uhoh) | 215: - .long SYM(_uhoh) | 216: - .long SYM(_uhoh) | 217: - .long SYM(_uhoh) | 218: - .long SYM(_uhoh) | 219: - .long SYM(_uhoh) | 220: - .long SYM(_uhoh) | 221: - .long SYM(_uhoh) | 222: - .long SYM(_uhoh) | 223: - .long SYM(_uhoh) | 224: - .long SYM(_uhoh) | 225: - .long SYM(_uhoh) | 226: - .long SYM(_uhoh) | 227: - .long SYM(_uhoh) | 228: - .long SYM(_uhoh) | 229: - .long SYM(_uhoh) | 230: - .long SYM(_uhoh) | 231: - .long SYM(_uhoh) | 232: - .long SYM(_uhoh) | 233: - .long SYM(_uhoh) | 234: - .long SYM(_uhoh) | 235: - .long SYM(_uhoh) | 236: - .long SYM(_uhoh) | 237: - .long SYM(_uhoh) | 238: - .long SYM(_uhoh) | 239: - .long SYM(_uhoh) | 240: - .long SYM(_uhoh) | 241: - .long SYM(_uhoh) | 242: - .long SYM(_uhoh) | 243: - .long SYM(_uhoh) | 244: - .long SYM(_uhoh) | 245: - .long SYM(_uhoh) | 246: - .long SYM(_uhoh) | 247: - .long SYM(_uhoh) | 248: - .long SYM(_uhoh) | 249: - .long SYM(_uhoh) | 250: - .long SYM(_uhoh) | 251: - .long SYM(_uhoh) | 252: - .long SYM(_uhoh) | 253: - .long SYM(_uhoh) | 254: - .long SYM(_uhoh) | 255: - -/* - * Default trap handler - * With an oscilloscope you can see AS* stop - */ - PUBLIC (_uhoh) -SYM(_uhoh): nop | Leave spot for breakpoint - stop #0x2700 | Stop with interrupts disabled - bra.s SYM(_uhoh) | Stuck forever - -/* - * Log, but otherwise ignore, spurious interrupts - */ - PUBLIC (_spuriousInterrupt) -SYM(_spuriousInterrupt): - addql #1,SYM(_M68kSpuriousInterruptCount) - rte - -/* - * Place the low-order 3 octets of the board's ethernet address at - * a `well-known' fixed location relative to the startup location. - */ - .align 2 - .word 0 | Padding -ethernet_address_buffer: - .word 0x08F3 | Default address - .word 0xDEAD - .word 0xCAFE - -/* -- equates -- */ -.equ _PROM_Start, 0x01000000 /* CS0 */ -.equ _BCCram_Start, 0x00000000 /* CS1 */ -.equ _FLEX_Start, 0x08000000 /* CS2 */ -.equ _I2C_Start, 0x02000000 /* CS3 */ -.equ _EXTram_Start, 0x10000000 /* CS4 */ -.equ _EXTram_Size, 0x000400000 /* 4 Mbytes */ -.equ _SPEED, 0xD780 /* 25 Mhz CPU349 */ -/* .equ _SPEED, 0xD700 25 Mhz */ -/* .equ _SPEED, 0xCE00 16 Mhz */ - -BEGIN_DATA - -_crt0_init_stack: - ds.l 0x1000 -_crt0_init_stktop: - - -BEGIN_CODE - dc.l _crt0_init_stktop /* reset SP */ - dc.l _crt0_cold_start /* reset PC */ - dc.l _crt0_warm_start - - .ascii "RTEMS" - dc.w 0 - -.align 2 - -_table_cs: - /* carte Astecc - 68340 */ - dc.l 0x003FFFF0 /* Mask CS0 (4Mbytes PROM, 32bits, 0WS) */ -/* dc.l 0x003FFFFD Mask CS0 (4Mbytes PROM, 16bits, 3WS) */ - dc.l ((_PROM_Start&0xFFFFFF00)+0x00000003) /* Base CS0 */ -/* dc.l 0x0000FFF1 MASK CS1 (RAMBCC340, 0WS, FTE) */ - dc.l 0x0000FFFD /* MASK CS1 (RAMBCC340, 0WS, FTE) */ -/* dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000007) Base CS1 */ - dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000003) /* Base CS1 */ - dc.l 0x000000FF /* MASK CS2 (FLEX, ext DTACK, 256 bytes) */ - dc.l ((_FLEX_Start&0xFFFFFF00)+0x00000003) /* Base CS2 */ - dc.l 0x000000FF /* Mask CS3 (I2C, ext DTACK, 256 bytes) */ - dc.l ((_I2C_Start&0xFFFFFF00)+0x00000003) /* Base CS3 */ - -/* - * Initial PC - */ -.globl start -start: - -_crt0_cold_start: - moveq.l #0,d0 /* signal cold reset */ - bra.s _crt0_common_start - -_crt0_warm_start: - moveq.l #1,d0 /* signal warm reset */ - -_crt0_common_start: - move.w #0x2700,sr /* disable interrupts and switch to interrupt mode */ - movea.l #_crt0_init_stktop,sp /* set up initialization stack */ - - lea Entry,a0 /* Get base of vector table */ - movec a0,vbr /* Set up the VBR */ - - moveq.l #0x07,d1 - movec.l d1,dfc /* prepare access in CPU space */ - move.l #(BASE_SIM+1),d1 - moves.l d1,BASE_REG /* base initialization (must be MOVES, PCC-130795) */ - moveq.l #0x05,d1 - movec.l d1,dfc - - movea.l #BASE_SIM,a0 - - /* -- disable Bus Monitor -- */ - move.b #0,SIM_SYPCR(a0) /* system protection control register */ - - /* -- set frequency to 25.16 Mhz -- */ - move.w #_SPEED,SIM_SYNCR(a0) /* clock */ - -sync_wait: - btst.b #3,(SIM_SYNCR+1)(a0) - beq sync_wait - - /* -- enable A31-A24 -- */ - clr.b SIM_PPRA1(a0) - - /* -- show cycles, user acces to SIM, 4 /CS & 4 /IT -- */ - move.w #0x427F,SIM_MCR(a0) - - /* -- chip select initialization -- */ - lea.l SIM_MASKH0(a0),a2 - lea.l _table_cs(%pc),a1 - - moveq.l #0x07,d1 - -_b_cs: - move.l (a1)+, (a2)+ - dbra d1,_b_cs - - /* fill RAM if COLDSTART */ - tst.l d0 - bne _dont_fill - - movea.l #_EXTram_Start,a0 /* get start */ - move.l #_EXTram_Size,d1 /* get size */ - lsr.l #2,d1 /* ajust for long word */ - -_fill_loop: - clr.l (a0)+ - subq.l #1,d1 - bne _fill_loop - -_dont_fill: - jmp SYM(_Init68340) | Start C code (which never returns) - -/* - * Copy DATA segment, clear BSS segment, set up real stack, - * initialize heap, start C program. - * Assume that DATA and BSS sizes are multiples of 4. - */ - PUBLIC (_CopyDataClearBSSAndStart) -SYM(_CopyDataClearBSSAndStart): - lea copy_start,a0 | Get start of DATA in RAM - lea SYM(etext),a2 | Get start of DATA in ROM - cmpl a0,a2 | Are they the same? - beq.s NOCOPY | Yes, no copy necessary - lea copy_end,a1 | Get end of DATA in RAM - bra.s COPYLOOPTEST | Branch into copy loop -COPYLOOP: - movel a2@+,a0@+ | Copy word from ROM to RAM -COPYLOOPTEST: - cmpl a1,a0 | Done? - bcs.s COPYLOOP | No, skip -NOCOPY: - - lea clear_start,a0 | Get start of BSS - lea clear_end,a1 | Get end of BSS - clrl d0 | Value to set - bra.s ZEROLOOPTEST | Branch into clear loop -ZEROLOOP: - movel d0,a0@+ | Clear a word -ZEROLOOPTEST: - cmpl a1,a0 | Done? - bcs.s ZEROLOOP | No, skip - - movel #stack_init,a7 | set master stack pointer - movel d0,a7@- | environp - movel d0,a7@- | argv - movel d0,a7@- | argc - jsr SYM(boot_card) | Call C main - - PUBLIC (_mainDone) -SYM(_mainDone): - nop | Leave spot for breakpoint - movew #1,a7 | Force a double bus error - movel d0,a7@- | This should cause a RESET - stop #0x2700 | Stop with interrupts disabled - bra.s SYM(_mainDone) | Stuck forever - - .align 2 - PUBLIC (_HeapSize) -SYM (_HeapSize): - .long HeapSize - PUBLIC (_StackSize) -SYM (_StackSize): - .long StackSize -END_CODE - -BEGIN_DATA_DCL - .align 2 - PUBLIC (environ) -SYM (environ): - .long 0 - PUBLIC (_M68kSpuriousInterruptCount) -SYM (_M68kSpuriousInterruptCount): - .long 0 -END_DATA_DCL - -END - diff --git a/c/src/lib/libbsp/m68k/gen68340/start340/Makefile.in b/c/src/lib/libbsp/m68k/gen68340/start340/Makefile.in index ce91b95e3b..4dfebd249f 100644 --- a/c/src/lib/libbsp/m68k/gen68340/start340/Makefile.in +++ b/c/src/lib/libbsp/m68k/gen68340/start340/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=start340 -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/m68k/gen68340/start340/start340.S b/c/src/lib/libbsp/m68k/gen68340/start340/start340.S new file mode 100644 index 0000000000..58ea0c92d0 --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68340/start340/start340.S @@ -0,0 +1,874 @@ +/* + * This file contains the entry point for the application. + * The name of this entry point is compiler dependent. + * It jumps to the BSP which is responsible for performing + * all initialization. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * Based on the `gen68360' board support package, and covered by the + * original distribution terms. + * + * Geoffroy Montel + * France Telecom - CNET/DSM/TAM/CAT + * 4, rue du Clos Courtel + * 35512 CESSON-SEVIGNE + * FRANCE + * + * e-mail: g_montel@yahoo.com + * + * $Id$ + */ + +#include "asm.h" +#include + +#define _OLD_ASTECC 1 /* old addresses for AST68340 only, undefine for AST68349 */ + +BEGIN_CODE + /* + * Step 1: Decide on Reset Stack Pointer and Initial Program Counter + */ +Entry: + .long SYM(m340)+1024 | 0: Initial SSP + .long start | 1: Initial PC + .long SYM(_uhoh) | 2: Bus error + .long SYM(_uhoh) | 3: Address error + .long SYM(_uhoh) | 4: Illegal instruction + .long SYM(_uhoh) | 5: Zero division + .long SYM(_uhoh) | 6: CHK, CHK2 instruction + .long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions + .long SYM(_uhoh) | 8: Privilege violation + .long SYM(_uhoh) | 9: Trace + .long SYM(_uhoh) | 10: Line 1010 emulator + .long SYM(_uhoh) | 11: Line 1111 emulator + .long SYM(_uhoh) | 12: Hardware breakpoint + .long SYM(_uhoh) | 13: Reserved for coprocessor violation + .long SYM(_uhoh) | 14: Format error + .long SYM(_uhoh) | 15: Uninitialized interrupt + .long SYM(_uhoh) | 16: Unassigned, reserved + .long SYM(_uhoh) | 17: + .long SYM(_uhoh) | 18: + .long SYM(_uhoh) | 19: + .long SYM(_uhoh) | 20: + .long SYM(_uhoh) | 21: + .long SYM(_uhoh) | 22: + .long SYM(_uhoh) | 23: + .long SYM(_spuriousInterrupt) | 24: Spurious interrupt + .long SYM(_uhoh) | 25: Level 1 interrupt autovector + .long SYM(_uhoh) | 26: Level 2 interrupt autovector + .long SYM(_uhoh) | 27: Level 3 interrupt autovector + .long SYM(_uhoh) | 28: Level 4 interrupt autovector + .long SYM(_uhoh) | 29: Level 5 interrupt autovector + .long SYM(_uhoh) | 30: Level 6 interrupt autovector + .long SYM(_uhoh) | 31: Level 7 interrupt autovector + .long SYM(_uhoh) | 32: Trap instruction (0-15) + .long SYM(_uhoh) | 33: + .long SYM(_uhoh) | 34: + .long SYM(_uhoh) | 35: + .long SYM(_uhoh) | 36: + .long SYM(_uhoh) | 37: + .long SYM(_uhoh) | 38: + .long SYM(_uhoh) | 39: + .long SYM(_uhoh) | 40: + .long SYM(_uhoh) | 41: + .long SYM(_uhoh) | 42: + .long SYM(_uhoh) | 43: + .long SYM(_uhoh) | 44: + .long SYM(_uhoh) | 45: + .long SYM(_uhoh) | 46: + .long SYM(_uhoh) | 47: + .long SYM(_uhoh) | 48: Reserved for coprocessor + .long SYM(_uhoh) | 49: + .long SYM(_uhoh) | 50: + .long SYM(_uhoh) | 51: + .long SYM(_uhoh) | 52: + .long SYM(_uhoh) | 53: + .long SYM(_uhoh) | 54: + .long SYM(_uhoh) | 55: + .long SYM(_uhoh) | 56: + .long SYM(_uhoh) | 57: + .long SYM(_uhoh) | 58: + .long SYM(_uhoh) | 59: Unassigned, reserved + .long SYM(_uhoh) | 60: + .long SYM(_uhoh) | 61: + .long SYM(_uhoh) | 62: + .long SYM(_uhoh) | 63: + .long SYM(_uhoh) | 64: User defined vectors (192) + .long SYM(_uhoh) | 65: + .long SYM(_uhoh) | 66: + .long SYM(_uhoh) | 67: + .long SYM(_uhoh) | 68: + .long SYM(_uhoh) | 69: + .long SYM(_uhoh) | 70: + .long SYM(_uhoh) | 71: + .long SYM(_uhoh) | 72: + .long SYM(_uhoh) | 73: + .long SYM(_uhoh) | 74: + .long SYM(_uhoh) | 75: + .long SYM(_uhoh) | 76: + .long SYM(_uhoh) | 77: + .long SYM(_uhoh) | 78: + .long SYM(_uhoh) | 79: + .long SYM(_uhoh) | 80: + .long SYM(_uhoh) | 81: + .long SYM(_uhoh) | 82: + .long SYM(_uhoh) | 83: + .long SYM(_uhoh) | 84: + .long SYM(_uhoh) | 85: + .long SYM(_uhoh) | 86: + .long SYM(_uhoh) | 87: + .long SYM(_uhoh) | 88: + .long SYM(_uhoh) | 89: + .long SYM(_uhoh) | 90: + .long SYM(_uhoh) | 91: + .long SYM(_uhoh) | 92: + .long SYM(_uhoh) | 93: + .long SYM(_uhoh) | 94: + .long SYM(_uhoh) | 95: + .long SYM(_uhoh) | 96: + .long SYM(_uhoh) | 97: + .long SYM(_uhoh) | 98: + .long SYM(_uhoh) | 99: + .long SYM(_uhoh) | 100: + .long SYM(_uhoh) | 101: + .long SYM(_uhoh) | 102: + .long SYM(_uhoh) | 103: + .long SYM(_uhoh) | 104: + .long SYM(_uhoh) | 105: + .long SYM(_uhoh) | 106: + .long SYM(_uhoh) | 107: + .long SYM(_uhoh) | 108: + .long SYM(_uhoh) | 109: + .long SYM(_uhoh) | 110: + .long SYM(_uhoh) | 111: + .long SYM(_uhoh) | 112: + .long SYM(_uhoh) | 113: + .long SYM(_uhoh) | 114: + .long SYM(_uhoh) | 115: + .long SYM(_uhoh) | 116: + .long SYM(_uhoh) | 117: + .long SYM(_uhoh) | 118: + .long SYM(_uhoh) | 119: + .long SYM(_uhoh) | 120: + .long SYM(_uhoh) | 121: + .long SYM(_uhoh) | 122: + .long SYM(_uhoh) | 123: + .long SYM(_uhoh) | 124: + .long SYM(_uhoh) | 125: + .long SYM(_uhoh) | 126: + .long SYM(_uhoh) | 127: + .long SYM(_uhoh) | 128: + .long SYM(_uhoh) | 129: + .long SYM(_uhoh) | 130: + .long SYM(_uhoh) | 131: + .long SYM(_uhoh) | 132: + .long SYM(_uhoh) | 133: + .long SYM(_uhoh) | 134: + .long SYM(_uhoh) | 135: + .long SYM(_uhoh) | 136: + .long SYM(_uhoh) | 137: + .long SYM(_uhoh) | 138: + .long SYM(_uhoh) | 139: + .long SYM(_uhoh) | 140: + .long SYM(_uhoh) | 141: + .long SYM(_uhoh) | 142: + .long SYM(_uhoh) | 143: + .long SYM(_uhoh) | 144: + .long SYM(_uhoh) | 145: + .long SYM(_uhoh) | 146: + .long SYM(_uhoh) | 147: + .long SYM(_uhoh) | 148: + .long SYM(_uhoh) | 149: + .long SYM(_uhoh) | 150: + .long SYM(_uhoh) | 151: + .long SYM(_uhoh) | 152: + .long SYM(_uhoh) | 153: + .long SYM(_uhoh) | 154: + .long SYM(_uhoh) | 155: + .long SYM(_uhoh) | 156: + .long SYM(_uhoh) | 157: + .long SYM(_uhoh) | 158: + .long SYM(_uhoh) | 159: + .long SYM(_uhoh) | 160: + .long SYM(_uhoh) | 161: + .long SYM(_uhoh) | 162: + .long SYM(_uhoh) | 163: + .long SYM(_uhoh) | 164: + .long SYM(_uhoh) | 165: + .long SYM(_uhoh) | 166: + .long SYM(_uhoh) | 167: + .long SYM(_uhoh) | 168: + .long SYM(_uhoh) | 169: + .long SYM(_uhoh) | 170: + .long SYM(_uhoh) | 171: + .long SYM(_uhoh) | 172: + .long SYM(_uhoh) | 173: + .long SYM(_uhoh) | 174: + .long SYM(_uhoh) | 175: + .long SYM(_uhoh) | 176: + .long SYM(_uhoh) | 177: + .long SYM(_uhoh) | 178: + .long SYM(_uhoh) | 179: + .long SYM(_uhoh) | 180: + .long SYM(_uhoh) | 181: + .long SYM(_uhoh) | 182: + .long SYM(_uhoh) | 183: + .long SYM(_uhoh) | 184: + .long SYM(_uhoh) | 185: + .long SYM(_uhoh) | 186: + .long SYM(_uhoh) | 187: + .long SYM(_uhoh) | 188: + .long SYM(_uhoh) | 189: + .long SYM(_uhoh) | 190: + .long SYM(_uhoh) | 191: + .long SYM(_uhoh) | 192: + .long SYM(_uhoh) | 193: + .long SYM(_uhoh) | 194: + .long SYM(_uhoh) | 195: + .long SYM(_uhoh) | 196: + .long SYM(_uhoh) | 197: + .long SYM(_uhoh) | 198: + .long SYM(_uhoh) | 199: + .long SYM(_uhoh) | 200: + .long SYM(_uhoh) | 201: + .long SYM(_uhoh) | 202: + .long SYM(_uhoh) | 203: + .long SYM(_uhoh) | 204: + .long SYM(_uhoh) | 205: + .long SYM(_uhoh) | 206: + .long SYM(_uhoh) | 207: + .long SYM(_uhoh) | 208: + .long SYM(_uhoh) | 209: + .long SYM(_uhoh) | 210: + .long SYM(_uhoh) | 211: + .long SYM(_uhoh) | 212: + .long SYM(_uhoh) | 213: + .long SYM(_uhoh) | 214: + .long SYM(_uhoh) | 215: + .long SYM(_uhoh) | 216: + .long SYM(_uhoh) | 217: + .long SYM(_uhoh) | 218: + .long SYM(_uhoh) | 219: + .long SYM(_uhoh) | 220: + .long SYM(_uhoh) | 221: + .long SYM(_uhoh) | 222: + .long SYM(_uhoh) | 223: + .long SYM(_uhoh) | 224: + .long SYM(_uhoh) | 225: + .long SYM(_uhoh) | 226: + .long SYM(_uhoh) | 227: + .long SYM(_uhoh) | 228: + .long SYM(_uhoh) | 229: + .long SYM(_uhoh) | 230: + .long SYM(_uhoh) | 231: + .long SYM(_uhoh) | 232: + .long SYM(_uhoh) | 233: + .long SYM(_uhoh) | 234: + .long SYM(_uhoh) | 235: + .long SYM(_uhoh) | 236: + .long SYM(_uhoh) | 237: + .long SYM(_uhoh) | 238: + .long SYM(_uhoh) | 239: + .long SYM(_uhoh) | 240: + .long SYM(_uhoh) | 241: + .long SYM(_uhoh) | 242: + .long SYM(_uhoh) | 243: + .long SYM(_uhoh) | 244: + .long SYM(_uhoh) | 245: + .long SYM(_uhoh) | 246: + .long SYM(_uhoh) | 247: + .long SYM(_uhoh) | 248: + .long SYM(_uhoh) | 249: + .long SYM(_uhoh) | 250: + .long SYM(_uhoh) | 251: + .long SYM(_uhoh) | 252: + .long SYM(_uhoh) | 253: + .long SYM(_uhoh) | 254: + .long SYM(_uhoh) | 255: + +/* + * Default trap handler + * With an oscilloscope you can see AS* stop + */ + PUBLIC (_uhoh) +SYM(_uhoh): nop | Leave spot for breakpoint +/* stop #0x2700 | Stop with interrupts disabled */ + move.w #0x2700,sr + move.w (a7),_boot_panic_registers+4 | SR + move.l 2(a7),_boot_panic_registers | PC + move.w 6(a7),_boot_panic_registers+6 | format & vector + movem.l d0-d7/a0-a7, _boot_panic_registers+8 + movec sfc, d0 + movem.l d0, _boot_panic_registers+72 + movec dfc, d0 + movem.l d0, _boot_panic_registers+76 + movec vbr, d0 + movem.l d0, _boot_panic_registers+80 + jmp SYM(_dbug_dumpanic) + bra.s _crt0_cold_start + +/* + * Log, but otherwise ignore, spurious interrupts + */ + PUBLIC (_spuriousInterrupt) +SYM(_spuriousInterrupt): + addql #1,SYM(_M68kSpuriousInterruptCount) + rte + +/* + * Place the low-order 3 octets of the board's ethernet address at + * a `well-known' fixed location relative to the startup location. + */ + .align 2 + .word 0 | Padding +ethernet_address_buffer: + .word 0x08F3 | Default address + .word 0xDEAD + .word 0xCAFE + +BEGIN_DATA + +/* equates */ + +.equ _CPU340, 0x0 +.equ _CPU349, 0x31 + +#ifdef _OLD_ASTECC /* old addresses for AST68340 only */ +.equ _EPLD_CS_BASE, 0x1 +.equ _PROM_Start, 0x01000000 /* CS0 */ +.equ _FLEX_Start, 0x08000000 /* CS2 */ +.equ _I2C_Start, 0x0c000000 /* CS3 */ + +.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */ +.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */ + +.equ _ExtRam_Start, 0x10000000 /* SRAM */ +.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */ + +.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */ +.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */ + +#else /* new addresses for AST68349 and 68340 */ + +.equ _EPLD_CS_BASE, 0x5 +.equ _PROM_Start, 0x50000000 /* CS0 */ +.equ _FLEX_Start, 0x08000000 /* CS2 */ +.equ _I2C_Start, 0x0c000000 /* CS3 */ + +.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */ +.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */ + +.equ _ExtRam_Start, 0x80000000 /* DRAM */ +.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */ + +.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */ +.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */ +#endif + +.equ _SPEED349, 0xD680 /* 24 Mhz */ +.equ _SPEED340, 0xD700 /* 25 Mhz */ +/* .equ _SPEED340, 0xCE00 16 Mhz */ + +#define crt0_boot_type d0 /* cold/warm start (must be D0) */ +#define crt0_temp d1 +#define crt0_cpu_type d2 +#define crt0_csswitch d3 +#define crt0_buswidth d4 +#define crt0_pdcs d5 +#define crt0_spare6 d6 +#define crt0_spare7 d7 +#define crt0_sim_base a0 +#define crt0_glue a1 +#define crt0_dram a2 +#define crt0_ptr3 a3 +#define crt0_ptr4 a4 +#define crt0_ptr5 a5 +#define crt0_ptr6 a6 + +/* -- PDCS buffer equates -- */ +.equ pdcs_mask, 0x1F /* DRAM configuration */ +.equ pdcs_sw12, 7 /* switch 12 */ +.equ pdcs_sw11, 6 /* switch 11 */ +.equ pdcs_sw14, 5 /* switch 14 */ + +.equ bit_cache, pdcs_sw12 /* enable cache if on */ +.equ bit_meminit, pdcs_sw11 /* init memory if on */ + +/* -- Initialization stack and vars -- */ + +_AsteccBusWidth: ds.b 1 +_AsteccCsSwitch: ds.b 1 +_AsteccCpuName: ds.l 1 + +.align 4 + +_crt0_init_stack: + ds.l 500 +_crt0_init_stktop: + +/* -- Initialization code -- */ +BEGIN_CODE + +.align 4 + dc.l _crt0_init_stktop /* reset SP */ + dc.l _crt0_cold_start /* reset PC */ + dc.l _crt0_warm_start + + .ascii "BOOT XHM68K/Spectra for ASTECC 68349 and 68340 boards" + dc.w 0 +.align 4 + +.globl start +start: + +_crt0_cold_start: + moveq.l #0,crt0_boot_type | signal cold reset + bra.s _crt0_common_start + +_crt0_warm_start: + moveq.l #1,crt0_boot_type | signal warm reset + +_crt0_common_start: + move.w #0x2700,sr | disable interrupts and switch to interrupt mode + movea.l #_crt0_init_stktop,sp | set up initialization stack + + move.l #Entry,crt0_temp | VBR initialization + movec.l crt0_temp,vbr | + moveq.l #0x07,crt0_temp + movec.l crt0_temp,dfc | prepare access in CPU space + move.l #(BASE_SIM+0x111),crt0_temp | mask CPU, RESERVED USER SPACES + moves.l crt0_temp,BASE_REG | base initialization (must be MOVES, PCC-130795) + + movea.l #BASE_SIM,crt0_sim_base + + /* -- disable Bus Monitor -- */ + move.b #0,SIM_SYPCR(crt0_sim_base) | system protection control register + + /* -- enable A31-A24 -- */ + clr.b SIM_PPRA1(crt0_sim_base) + + /* -- show cycles, user acces to SIM, 4 /CS & 4 /IT -- */ + move.w #0x427F,SIM_MCR(crt0_sim_base) + + /* -- enable /IRQ3, 5, 6, 7 -- */ + move.b #0xE8,SIM_PPRB(crt0_sim_base) + + /* -- enable autovector on /IRQ7 -- */ + move.b #0x80,SIM_AVR(crt0_sim_base) + + /* -- test CPU type -- */ + cmp.b #_CPU349,SIM_IDR(crt0_sim_base) + bne cpu_is_68340 + +/*-------------------------------------------------------------------------------------------*/ +cpu_is_68349: + + /* -- set cpu clock -- */ + move.w #_SPEED349,SIM_SYNCR(crt0_sim_base) | clock + +sync_wait349: + btst.b #3,(SIM_SYNCR+1)(crt0_sim_base) + beq sync_wait349 + + /* to allow access to the EPLD internal registers, it is necessary + to disable the global chip-select /CS0 (which decodes every external + cycles). To do that, we initialize the 68349 internal RAM, + copy a part of the initialization code in it, and jump there. + from that moment, /CS0 is not used, therefore it can be initialized + with its default value. Its width may be incorrect, but it will be + adjusted later. The goal is to avoid any conflict with + the accesses to the EPLD registers. + When this is done, we read the RESET parameters (boot prom width + and chip-select switch) and proceed with the initialization + when all is done, we jump back to the boot prom now + decoded with a properly configured /CS0 */ + + /*-------------------------------------*/ + /* -- configure internal SRAM banks -- */ + + move.l #0x00000000,QDMM_MCR(crt0_sim_base) + move.l #_FastRam_Start+0x0005,QDMM_QBAR0(crt0_sim_base) + move.l #_FastRam_Start+0x0405,QDMM_QBAR1(crt0_sim_base) + move.l #_FastRam_Start+0x0805,QDMM_QBAR2(crt0_sim_base) + move.l #_FastRam_Start+0x0c05,QDMM_QBAR3(crt0_sim_base) + + /*--------------------------------------------------------*/ + /* -- copy to address of the 68349 initialization code -- */ + + lea.l _copy_start(%pc),crt0_ptr3 + lea.l _copy_end(%pc),crt0_ptr4 + move.l crt0_ptr4,crt0_temp + sub.l crt0_ptr3,crt0_temp + add.l #3,crt0_temp | adjust to next long word + lsr.l #2,crt0_temp + + move.l #_FastRam_Start,crt0_ptr4 +_copy_loop: + move.l (crt0_ptr3)+,(crt0_ptr4)+ + subq.l #1,crt0_temp + bne.s _copy_loop + bra.l _FastRam_Start | jump to code in internal RAM + + /*------------------------------------*/ + /* -- start of initialization code -- */ + +_copy_start: + bra.l _begin_68349_init + + /*----------------------------------------------------------*/ + /* Astecc 68349 board : chip-select initialization values */ + +_table_csepld: + dc.b (_EPLD_CS_BASE&0x0F)+0x80 | 16 bits, 0ws + dc.b 0x80 | 16 bits, 0 ws + dc.b 0x90 | 16 bits, ext /dsack + dc.b 0x90 | 16 bits, ext /dsack + +_table_cs349: + dc.l 0x003FFFF4 | Mask CS0 (4Mbytes PROM, 32bits, 1WS) + dc.l (_PROM_Start&0xFFFFFF00)+0x00000003 | Base CS0 + dc.l 0x003FFFF1 | MASK CS1 (4Mbytes RAM, 16bits, 0WS) + dc.l (_BCCram_Start&0xFFFFFF00)+0x00000003 | Base CS1 + dc.l 0x000000FF | MASK CS2 (FLEX, ext DTACK, 256 bytes) + dc.l (_FLEX_Start&0xFFFFFF00)+0x00000003 | Base CS2 + dc.l 0x000000FF | Mask CS3 (I2C, ext DTACK, 256 bytes) + dc.l (_I2C_Start&0xFFFFFF00)+0x00000003 | Base CS3 + + /*-------------------------------------------------*/ +_begin_68349_init: + + /*-------------------------------------------------*/ + /* 68349 chip select initialization + + at this stage, the width of /CS0 may be incorrect + it will be corrected later + */ + +_cs68349_init: + lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 + lea.l _table_cs349(%pc),crt0_ptr3 + + moveq.l #0x07,crt0_temp +_cs349_init2: + move.l (crt0_ptr3)+,(crt0_ptr4)+ + dbra crt0_temp,_cs349_init2 + + /*-----------------------------------------------*/ + /* -- prepare access to the internal registers --*/ + moveq.l #EPLD_SPACE,crt0_temp + movec.l crt0_temp,dfc + movec.l crt0_temp,sfc + move.l #GLUE_EPLD,crt0_glue + move.l #DRAM_EPLD,crt0_dram + + /*-------------------------------------------*/ + /* EPLD generated /CS[3..0] must be disabled */ + +_csepld_clear: + move.l crt0_glue,crt0_ptr4 + move.w #3,crt0_spare6 + clr.b crt0_temp + +_csepld_clear1: + moves.b crt0_temp,(crt0_ptr4)+ + dbra crt0_spare6,_csepld_clear1 + + /*---------------------------------------------------------*/ + /* -- get width of boot PROM, and active chip-select set --*/ + moves.b REG_BUSWIDTH(crt0_dram),crt0_csswitch + move.b crt0_csswitch,crt0_buswidth + + /* state of CS_SWITCH : sel == 0 => CPU chip_selects (/CS[3..0]) + : sel == 1 => EPLD chip_selects (/CS[3..0]) */ + and.b #1,crt0_csswitch + + /* bus width of /CS0 during reset bw[1..0] : 0 1 2 3 + bus width : 32 16 8 ext./dsackx */ + rol.b #2,crt0_buswidth + and.b #3,crt0_buswidth + + /*----------------------------------------------------*/ + /* -- configure chip select 0 with boot prom width -- */ + lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 + lea.l _table_cs349(%pc),crt0_ptr3 + move.l (crt0_ptr3)+,crt0_temp + and.b #0xFC,crt0_temp | clear PS0 & PS1 + or.b crt0_buswidth,crt0_temp | set boot PROM bus width + move.l crt0_temp,(crt0_ptr4)+ + + /*------------------------*/ + /* -- read PDCS buffer -- */ + moves.b REG_PDCS(crt0_glue),crt0_pdcs +/* move.b #0x3F,crt0_pdcs pour test */ + + + /*---------------------------------------*/ + /* -- EPLD chip-select initialization -- */ + /*---------------------------------------*/ + btst.b #0,crt0_csswitch + beq _cs_init_end + + /*--------------------------------------------*/ + /* 68349 generated /CS[3..0] must be disabled */ + lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 + lea.l _table_cs349(%pc),crt0_ptr3 + moveq.l #0x03,crt0_temp +_cs349_clear: + move.l (crt0_ptr3)+,(crt0_ptr4)+ + move.l (crt0_ptr3)+,crt0_spare6 + and.b #0xFE,crt0_spare6 | disable chip-select + move.l crt0_spare6,(crt0_ptr4)+ + dbra crt0_temp,_cs349_clear + + /*---------------------------------------------*/ + /* EPLD generated /CS[3..0] must be configured */ +_csepld_init: + move.l crt0_glue,crt0_ptr4 + lea.l _table_csepld(%pc),crt0_ptr3 + + move.b (crt0_ptr3)+,crt0_temp + or.b #0x20,crt0_temp | default width is 32 bits + tst.b crt0_buswidth | is boot PROM bus width 32 bits ? + beq _csepld1 | if not + and.b #0xDF,crt0_temp | set width to 16 bits +_csepld1: + moves.b crt0_temp,(crt0_ptr4)+ + + moveq.l #0x02,crt0_spare6 +_csepld2: + move.b (crt0_ptr3)+,crt0_temp + moves.b crt0_temp,(crt0_ptr4)+ + dbra crt0_spare6,_csepld2 + +_cs_init_end: + + /*--------------------------------------*/ + /* -- DRAM controller initialization -- */ +_dram_init: + move.w #15,crt0_temp + move.l #_ExtRam_Start,crt0_ptr3 + +_dram_init1: + clr.l (crt0_ptr3)+ | must access DRAM + dbra crt0_temp,_dram_init1 | prior to init refresh + +_dram_init2: + move.b #3,crt0_temp + moves.b crt0_temp,REG_WS(crt0_dram) | set 3 wait-states + + move.b #0x81,crt0_temp + moves.b crt0_temp,REG_REFRESH(crt0_dram) | refresh every 10µs + + move.b #0,crt0_temp + moves.b crt0_temp,REG_CONFIG(crt0_dram) | default size = 4Mbytes + + /*-----------------------*/ + /* -- configure cache -- */ +_init_cache: + move.l #0x000001E0,CACHE_MCR(crt0_sim_base) + btst.b #bit_cache,crt0_pdcs + bne _init_cache_end + or.l #0x00000001,CACHE_MCR(crt0_sim_base) + +_init_cache_end: + + /*-----------------------------*/ + /* -- timers initialization -- */ + + clr.b crt0_temp + moves.b crt0_temp,REG_TIMER1(crt0_glue) | disable timer 1 + moves.b crt0_temp,REG_TIMER2(crt0_glue) | disable timer 2 + + /*--------------------------*/ + /* -- I2C initialization -- */ + move.b #3,crt0_temp + moves.b crt0_temp,REG_I2C(crt0_glue) | tri-states I2C ports + + /*-----------------------------------------*/ + /* -- baudrate generator initialization -- */ + move.b #2,crt0_temp + moves.b crt0_temp,REG_BAUDRATE(crt0_glue) | baudrate = 38400 + + /*-------------------------------*/ + /* -- IO port initialization -- */ + clr.b crt0_temp + moves.b crt0_temp,REG_IO(crt0_glue) | set port as input + + /* -- */ + + move.l #68349,crt0_cpu_type + + + /* -- jump back to PROM -- */ + + jmp.l (_fill_test) | must be absolute long + +_copy_end: + +/*------------------------------------------------- + initialization code for the 68340 board + -------------------------------------------------*/ + + /* Astecc 68340 board : chip-select initialization values */ +_table_cs340: + dc.l 0x003FFFF0 /* Mask CS0 (4Mbytes PROM, 32bits, 0WS) */ + dc.l ((_PROM_Start&0xFFFFFF00)+0x00000003) /* Base CS0 */ + dc.l 0x0000FFFD /* MASK CS1 (RAMBCC340, 0WS, FTE) */ + dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000003) /* Base CS1 */ + dc.l 0x000000FF /* MASK CS2 (FLEX, ext DTACK, 256 bytes) */ + dc.l ((_FLEX_Start&0xFFFFFF00)+0x00000003) /* Base CS2 */ + dc.l 0x000000FF /* Mask CS3 (I2C, ext DTACK, 256 bytes) */ + dc.l ((_I2C_Start&0xFFFFFF00)+0x00000003) /* Base CS3 */ + +cpu_is_68340: + + /* -- set cpu clock -- */ + move.w #_SPEED340,SIM_SYNCR(crt0_sim_base) | clock +sync_wait340: + btst.b #3,(SIM_SYNCR+1)(crt0_sim_base) + beq sync_wait340 + + /* -- chip select initialization -- */ + lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 + lea.l _table_cs340(%pc),crt0_ptr3 + moveq.l #0x07,crt0_temp +_b_cs340: + move.l (crt0_ptr3)+,crt0_ptr5 + move.l crt0_ptr5,(crt0_ptr4)+ | pour test + dbra crt0_temp,_b_cs340 + + move.l #68340,crt0_cpu_type + move.b #0,crt0_csswitch | CPU + move.b #1,crt0_buswidth | 16 bits + + + /*------------------------------------------------- + fill RAM if COLDSTART + -------------------------------------------------*/ +_fill_test: + + tst.l crt0_boot_type + bne _dont_fill + + cmp.b #_CPU349,SIM_IDR(crt0_sim_base) + bne _fill + btst.b #bit_meminit,crt0_pdcs + bne _dont_fill + + /* fill main memory */ +_fill: + move.l #_crt0_init_stack,crt0_ptr3 | skip Astecc vars + move.l #_ExtRam_Start,crt0_temp + sub.l #_crt0_init_stack,crt0_temp + add.l #_ExtRam_Size,crt0_temp | get size + lsr.l #2,crt0_temp | ajust for long word +_fill_loop: + clr.l (crt0_ptr3)+ + subq.l #1,crt0_temp + bne _fill_loop + + cmp.b #_CPU349,SIM_IDR(crt0_sim_base) + bne _fill_bccram + + /* fill QDMM memory */ + movea.l #_FastRam_Start,crt0_ptr3 | get start + move.l #_FastRam_Size,crt0_temp | get size + lsr.l #2,crt0_temp | ajust for long word + +_QDMMfill_loop: + clr.l (crt0_ptr3)+ + subq.l #1,crt0_temp + bne _QDMMfill_loop + bra _dont_fill + + /* fill BCC memory */ +_fill_bccram: + movea.l #_BCCram_Start,crt0_ptr3 | get start + move.l #_BCCram_Size,crt0_temp | get size + lsr.l #2,crt0_temp | ajust for long word +_BCCfill_loop: + clr.l (crt0_ptr3)+ + subq.l #1,crt0_temp + bne _BCCfill_loop + + *-------------------------------------------------*/ +_dont_fill: + move.b crt0_csswitch,_AsteccCsSwitch + move.b crt0_buswidth,_AsteccBusWidth + move.l crt0_cpu_type,_AsteccCpuName + + jmp SYM(_Init68340) | Start C code (which never returns) + +/* + * Copy DATA segment, clear BSS segment, set up real stack, + * initialize heap, start C program. + * Assume that DATA and BSS sizes are multiples of 4. + */ + PUBLIC (_CopyDataClearBSSAndStart) +SYM(_CopyDataClearBSSAndStart): + lea copy_start,a0 | Get start of DATA in RAM + lea SYM(etext),a2 | Get start of DATA in ROM + cmpl a0,a2 | Are they the same? + beq.s NOCOPY | Yes, no copy necessary + lea copy_end,a1 | Get end of DATA in RAM + bra.s COPYLOOPTEST | Branch into copy loop +COPYLOOP: + movel a2@+,a0@+ | Copy word from ROM to RAM +COPYLOOPTEST: + cmpl a1,a0 | Done? + bcs.s COPYLOOP | No, skip +NOCOPY: + + lea clear_start,a0 | Get start of BSS + lea clear_end,a1 | Get end of BSS + clrl d0 | Value to set + bra.s ZEROLOOPTEST | Branch into clear loop +ZEROLOOP: + movel d0,a0@+ | Clear a word +ZEROLOOPTEST: + cmpl a1,a0 | Done? + bcs.s ZEROLOOP | No, skip + + movel #stack_init,a7 | set master stack pointer + movel d0,a7@- | environp + movel d0,a7@- | argv + movel d0,a7@- | argc + jsr SYM(boot_card) | Call C main + + PUBLIC (_mainDone) +SYM(_mainDone): + nop | Leave spot for breakpoint + movew #1,a7 | Force a double bus error + movel d0,a7@- | This should cause a RESET +/* stop #0x2700 | Stop with interrupts disabled */ + move.w #0x2700,sr + bra.s SYM(_mainDone) | Stuck forever + + .align 2 + PUBLIC (_HeapSize) +SYM (_HeapSize): + .long HeapSize + PUBLIC (_StackSize) +SYM (_StackSize): + .long StackSize +END_CODE + +BEGIN_DATA_DCL + .align 2 + PUBLIC (environ) +SYM (environ): + .long 0 + PUBLIC (_M68kSpuriousInterruptCount) +SYM (_M68kSpuriousInterruptCount): + .long 0 +END_DATA_DCL + +END + diff --git a/c/src/lib/libbsp/m68k/gen68340/start340/start340.s b/c/src/lib/libbsp/m68k/gen68340/start340/start340.s deleted file mode 100644 index 58ea0c92d0..0000000000 --- a/c/src/lib/libbsp/m68k/gen68340/start340/start340.s +++ /dev/null @@ -1,874 +0,0 @@ -/* - * This file contains the entry point for the application. - * The name of this entry point is compiler dependent. - * It jumps to the BSP which is responsible for performing - * all initialization. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may in - * the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * Based on the `gen68360' board support package, and covered by the - * original distribution terms. - * - * Geoffroy Montel - * France Telecom - CNET/DSM/TAM/CAT - * 4, rue du Clos Courtel - * 35512 CESSON-SEVIGNE - * FRANCE - * - * e-mail: g_montel@yahoo.com - * - * $Id$ - */ - -#include "asm.h" -#include - -#define _OLD_ASTECC 1 /* old addresses for AST68340 only, undefine for AST68349 */ - -BEGIN_CODE - /* - * Step 1: Decide on Reset Stack Pointer and Initial Program Counter - */ -Entry: - .long SYM(m340)+1024 | 0: Initial SSP - .long start | 1: Initial PC - .long SYM(_uhoh) | 2: Bus error - .long SYM(_uhoh) | 3: Address error - .long SYM(_uhoh) | 4: Illegal instruction - .long SYM(_uhoh) | 5: Zero division - .long SYM(_uhoh) | 6: CHK, CHK2 instruction - .long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions - .long SYM(_uhoh) | 8: Privilege violation - .long SYM(_uhoh) | 9: Trace - .long SYM(_uhoh) | 10: Line 1010 emulator - .long SYM(_uhoh) | 11: Line 1111 emulator - .long SYM(_uhoh) | 12: Hardware breakpoint - .long SYM(_uhoh) | 13: Reserved for coprocessor violation - .long SYM(_uhoh) | 14: Format error - .long SYM(_uhoh) | 15: Uninitialized interrupt - .long SYM(_uhoh) | 16: Unassigned, reserved - .long SYM(_uhoh) | 17: - .long SYM(_uhoh) | 18: - .long SYM(_uhoh) | 19: - .long SYM(_uhoh) | 20: - .long SYM(_uhoh) | 21: - .long SYM(_uhoh) | 22: - .long SYM(_uhoh) | 23: - .long SYM(_spuriousInterrupt) | 24: Spurious interrupt - .long SYM(_uhoh) | 25: Level 1 interrupt autovector - .long SYM(_uhoh) | 26: Level 2 interrupt autovector - .long SYM(_uhoh) | 27: Level 3 interrupt autovector - .long SYM(_uhoh) | 28: Level 4 interrupt autovector - .long SYM(_uhoh) | 29: Level 5 interrupt autovector - .long SYM(_uhoh) | 30: Level 6 interrupt autovector - .long SYM(_uhoh) | 31: Level 7 interrupt autovector - .long SYM(_uhoh) | 32: Trap instruction (0-15) - .long SYM(_uhoh) | 33: - .long SYM(_uhoh) | 34: - .long SYM(_uhoh) | 35: - .long SYM(_uhoh) | 36: - .long SYM(_uhoh) | 37: - .long SYM(_uhoh) | 38: - .long SYM(_uhoh) | 39: - .long SYM(_uhoh) | 40: - .long SYM(_uhoh) | 41: - .long SYM(_uhoh) | 42: - .long SYM(_uhoh) | 43: - .long SYM(_uhoh) | 44: - .long SYM(_uhoh) | 45: - .long SYM(_uhoh) | 46: - .long SYM(_uhoh) | 47: - .long SYM(_uhoh) | 48: Reserved for coprocessor - .long SYM(_uhoh) | 49: - .long SYM(_uhoh) | 50: - .long SYM(_uhoh) | 51: - .long SYM(_uhoh) | 52: - .long SYM(_uhoh) | 53: - .long SYM(_uhoh) | 54: - .long SYM(_uhoh) | 55: - .long SYM(_uhoh) | 56: - .long SYM(_uhoh) | 57: - .long SYM(_uhoh) | 58: - .long SYM(_uhoh) | 59: Unassigned, reserved - .long SYM(_uhoh) | 60: - .long SYM(_uhoh) | 61: - .long SYM(_uhoh) | 62: - .long SYM(_uhoh) | 63: - .long SYM(_uhoh) | 64: User defined vectors (192) - .long SYM(_uhoh) | 65: - .long SYM(_uhoh) | 66: - .long SYM(_uhoh) | 67: - .long SYM(_uhoh) | 68: - .long SYM(_uhoh) | 69: - .long SYM(_uhoh) | 70: - .long SYM(_uhoh) | 71: - .long SYM(_uhoh) | 72: - .long SYM(_uhoh) | 73: - .long SYM(_uhoh) | 74: - .long SYM(_uhoh) | 75: - .long SYM(_uhoh) | 76: - .long SYM(_uhoh) | 77: - .long SYM(_uhoh) | 78: - .long SYM(_uhoh) | 79: - .long SYM(_uhoh) | 80: - .long SYM(_uhoh) | 81: - .long SYM(_uhoh) | 82: - .long SYM(_uhoh) | 83: - .long SYM(_uhoh) | 84: - .long SYM(_uhoh) | 85: - .long SYM(_uhoh) | 86: - .long SYM(_uhoh) | 87: - .long SYM(_uhoh) | 88: - .long SYM(_uhoh) | 89: - .long SYM(_uhoh) | 90: - .long SYM(_uhoh) | 91: - .long SYM(_uhoh) | 92: - .long SYM(_uhoh) | 93: - .long SYM(_uhoh) | 94: - .long SYM(_uhoh) | 95: - .long SYM(_uhoh) | 96: - .long SYM(_uhoh) | 97: - .long SYM(_uhoh) | 98: - .long SYM(_uhoh) | 99: - .long SYM(_uhoh) | 100: - .long SYM(_uhoh) | 101: - .long SYM(_uhoh) | 102: - .long SYM(_uhoh) | 103: - .long SYM(_uhoh) | 104: - .long SYM(_uhoh) | 105: - .long SYM(_uhoh) | 106: - .long SYM(_uhoh) | 107: - .long SYM(_uhoh) | 108: - .long SYM(_uhoh) | 109: - .long SYM(_uhoh) | 110: - .long SYM(_uhoh) | 111: - .long SYM(_uhoh) | 112: - .long SYM(_uhoh) | 113: - .long SYM(_uhoh) | 114: - .long SYM(_uhoh) | 115: - .long SYM(_uhoh) | 116: - .long SYM(_uhoh) | 117: - .long SYM(_uhoh) | 118: - .long SYM(_uhoh) | 119: - .long SYM(_uhoh) | 120: - .long SYM(_uhoh) | 121: - .long SYM(_uhoh) | 122: - .long SYM(_uhoh) | 123: - .long SYM(_uhoh) | 124: - .long SYM(_uhoh) | 125: - .long SYM(_uhoh) | 126: - .long SYM(_uhoh) | 127: - .long SYM(_uhoh) | 128: - .long SYM(_uhoh) | 129: - .long SYM(_uhoh) | 130: - .long SYM(_uhoh) | 131: - .long SYM(_uhoh) | 132: - .long SYM(_uhoh) | 133: - .long SYM(_uhoh) | 134: - .long SYM(_uhoh) | 135: - .long SYM(_uhoh) | 136: - .long SYM(_uhoh) | 137: - .long SYM(_uhoh) | 138: - .long SYM(_uhoh) | 139: - .long SYM(_uhoh) | 140: - .long SYM(_uhoh) | 141: - .long SYM(_uhoh) | 142: - .long SYM(_uhoh) | 143: - .long SYM(_uhoh) | 144: - .long SYM(_uhoh) | 145: - .long SYM(_uhoh) | 146: - .long SYM(_uhoh) | 147: - .long SYM(_uhoh) | 148: - .long SYM(_uhoh) | 149: - .long SYM(_uhoh) | 150: - .long SYM(_uhoh) | 151: - .long SYM(_uhoh) | 152: - .long SYM(_uhoh) | 153: - .long SYM(_uhoh) | 154: - .long SYM(_uhoh) | 155: - .long SYM(_uhoh) | 156: - .long SYM(_uhoh) | 157: - .long SYM(_uhoh) | 158: - .long SYM(_uhoh) | 159: - .long SYM(_uhoh) | 160: - .long SYM(_uhoh) | 161: - .long SYM(_uhoh) | 162: - .long SYM(_uhoh) | 163: - .long SYM(_uhoh) | 164: - .long SYM(_uhoh) | 165: - .long SYM(_uhoh) | 166: - .long SYM(_uhoh) | 167: - .long SYM(_uhoh) | 168: - .long SYM(_uhoh) | 169: - .long SYM(_uhoh) | 170: - .long SYM(_uhoh) | 171: - .long SYM(_uhoh) | 172: - .long SYM(_uhoh) | 173: - .long SYM(_uhoh) | 174: - .long SYM(_uhoh) | 175: - .long SYM(_uhoh) | 176: - .long SYM(_uhoh) | 177: - .long SYM(_uhoh) | 178: - .long SYM(_uhoh) | 179: - .long SYM(_uhoh) | 180: - .long SYM(_uhoh) | 181: - .long SYM(_uhoh) | 182: - .long SYM(_uhoh) | 183: - .long SYM(_uhoh) | 184: - .long SYM(_uhoh) | 185: - .long SYM(_uhoh) | 186: - .long SYM(_uhoh) | 187: - .long SYM(_uhoh) | 188: - .long SYM(_uhoh) | 189: - .long SYM(_uhoh) | 190: - .long SYM(_uhoh) | 191: - .long SYM(_uhoh) | 192: - .long SYM(_uhoh) | 193: - .long SYM(_uhoh) | 194: - .long SYM(_uhoh) | 195: - .long SYM(_uhoh) | 196: - .long SYM(_uhoh) | 197: - .long SYM(_uhoh) | 198: - .long SYM(_uhoh) | 199: - .long SYM(_uhoh) | 200: - .long SYM(_uhoh) | 201: - .long SYM(_uhoh) | 202: - .long SYM(_uhoh) | 203: - .long SYM(_uhoh) | 204: - .long SYM(_uhoh) | 205: - .long SYM(_uhoh) | 206: - .long SYM(_uhoh) | 207: - .long SYM(_uhoh) | 208: - .long SYM(_uhoh) | 209: - .long SYM(_uhoh) | 210: - .long SYM(_uhoh) | 211: - .long SYM(_uhoh) | 212: - .long SYM(_uhoh) | 213: - .long SYM(_uhoh) | 214: - .long SYM(_uhoh) | 215: - .long SYM(_uhoh) | 216: - .long SYM(_uhoh) | 217: - .long SYM(_uhoh) | 218: - .long SYM(_uhoh) | 219: - .long SYM(_uhoh) | 220: - .long SYM(_uhoh) | 221: - .long SYM(_uhoh) | 222: - .long SYM(_uhoh) | 223: - .long SYM(_uhoh) | 224: - .long SYM(_uhoh) | 225: - .long SYM(_uhoh) | 226: - .long SYM(_uhoh) | 227: - .long SYM(_uhoh) | 228: - .long SYM(_uhoh) | 229: - .long SYM(_uhoh) | 230: - .long SYM(_uhoh) | 231: - .long SYM(_uhoh) | 232: - .long SYM(_uhoh) | 233: - .long SYM(_uhoh) | 234: - .long SYM(_uhoh) | 235: - .long SYM(_uhoh) | 236: - .long SYM(_uhoh) | 237: - .long SYM(_uhoh) | 238: - .long SYM(_uhoh) | 239: - .long SYM(_uhoh) | 240: - .long SYM(_uhoh) | 241: - .long SYM(_uhoh) | 242: - .long SYM(_uhoh) | 243: - .long SYM(_uhoh) | 244: - .long SYM(_uhoh) | 245: - .long SYM(_uhoh) | 246: - .long SYM(_uhoh) | 247: - .long SYM(_uhoh) | 248: - .long SYM(_uhoh) | 249: - .long SYM(_uhoh) | 250: - .long SYM(_uhoh) | 251: - .long SYM(_uhoh) | 252: - .long SYM(_uhoh) | 253: - .long SYM(_uhoh) | 254: - .long SYM(_uhoh) | 255: - -/* - * Default trap handler - * With an oscilloscope you can see AS* stop - */ - PUBLIC (_uhoh) -SYM(_uhoh): nop | Leave spot for breakpoint -/* stop #0x2700 | Stop with interrupts disabled */ - move.w #0x2700,sr - move.w (a7),_boot_panic_registers+4 | SR - move.l 2(a7),_boot_panic_registers | PC - move.w 6(a7),_boot_panic_registers+6 | format & vector - movem.l d0-d7/a0-a7, _boot_panic_registers+8 - movec sfc, d0 - movem.l d0, _boot_panic_registers+72 - movec dfc, d0 - movem.l d0, _boot_panic_registers+76 - movec vbr, d0 - movem.l d0, _boot_panic_registers+80 - jmp SYM(_dbug_dumpanic) - bra.s _crt0_cold_start - -/* - * Log, but otherwise ignore, spurious interrupts - */ - PUBLIC (_spuriousInterrupt) -SYM(_spuriousInterrupt): - addql #1,SYM(_M68kSpuriousInterruptCount) - rte - -/* - * Place the low-order 3 octets of the board's ethernet address at - * a `well-known' fixed location relative to the startup location. - */ - .align 2 - .word 0 | Padding -ethernet_address_buffer: - .word 0x08F3 | Default address - .word 0xDEAD - .word 0xCAFE - -BEGIN_DATA - -/* equates */ - -.equ _CPU340, 0x0 -.equ _CPU349, 0x31 - -#ifdef _OLD_ASTECC /* old addresses for AST68340 only */ -.equ _EPLD_CS_BASE, 0x1 -.equ _PROM_Start, 0x01000000 /* CS0 */ -.equ _FLEX_Start, 0x08000000 /* CS2 */ -.equ _I2C_Start, 0x0c000000 /* CS3 */ - -.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */ -.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */ - -.equ _ExtRam_Start, 0x10000000 /* SRAM */ -.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */ - -.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */ -.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */ - -#else /* new addresses for AST68349 and 68340 */ - -.equ _EPLD_CS_BASE, 0x5 -.equ _PROM_Start, 0x50000000 /* CS0 */ -.equ _FLEX_Start, 0x08000000 /* CS2 */ -.equ _I2C_Start, 0x0c000000 /* CS3 */ - -.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */ -.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */ - -.equ _ExtRam_Start, 0x80000000 /* DRAM */ -.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */ - -.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */ -.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */ -#endif - -.equ _SPEED349, 0xD680 /* 24 Mhz */ -.equ _SPEED340, 0xD700 /* 25 Mhz */ -/* .equ _SPEED340, 0xCE00 16 Mhz */ - -#define crt0_boot_type d0 /* cold/warm start (must be D0) */ -#define crt0_temp d1 -#define crt0_cpu_type d2 -#define crt0_csswitch d3 -#define crt0_buswidth d4 -#define crt0_pdcs d5 -#define crt0_spare6 d6 -#define crt0_spare7 d7 -#define crt0_sim_base a0 -#define crt0_glue a1 -#define crt0_dram a2 -#define crt0_ptr3 a3 -#define crt0_ptr4 a4 -#define crt0_ptr5 a5 -#define crt0_ptr6 a6 - -/* -- PDCS buffer equates -- */ -.equ pdcs_mask, 0x1F /* DRAM configuration */ -.equ pdcs_sw12, 7 /* switch 12 */ -.equ pdcs_sw11, 6 /* switch 11 */ -.equ pdcs_sw14, 5 /* switch 14 */ - -.equ bit_cache, pdcs_sw12 /* enable cache if on */ -.equ bit_meminit, pdcs_sw11 /* init memory if on */ - -/* -- Initialization stack and vars -- */ - -_AsteccBusWidth: ds.b 1 -_AsteccCsSwitch: ds.b 1 -_AsteccCpuName: ds.l 1 - -.align 4 - -_crt0_init_stack: - ds.l 500 -_crt0_init_stktop: - -/* -- Initialization code -- */ -BEGIN_CODE - -.align 4 - dc.l _crt0_init_stktop /* reset SP */ - dc.l _crt0_cold_start /* reset PC */ - dc.l _crt0_warm_start - - .ascii "BOOT XHM68K/Spectra for ASTECC 68349 and 68340 boards" - dc.w 0 -.align 4 - -.globl start -start: - -_crt0_cold_start: - moveq.l #0,crt0_boot_type | signal cold reset - bra.s _crt0_common_start - -_crt0_warm_start: - moveq.l #1,crt0_boot_type | signal warm reset - -_crt0_common_start: - move.w #0x2700,sr | disable interrupts and switch to interrupt mode - movea.l #_crt0_init_stktop,sp | set up initialization stack - - move.l #Entry,crt0_temp | VBR initialization - movec.l crt0_temp,vbr | - moveq.l #0x07,crt0_temp - movec.l crt0_temp,dfc | prepare access in CPU space - move.l #(BASE_SIM+0x111),crt0_temp | mask CPU, RESERVED USER SPACES - moves.l crt0_temp,BASE_REG | base initialization (must be MOVES, PCC-130795) - - movea.l #BASE_SIM,crt0_sim_base - - /* -- disable Bus Monitor -- */ - move.b #0,SIM_SYPCR(crt0_sim_base) | system protection control register - - /* -- enable A31-A24 -- */ - clr.b SIM_PPRA1(crt0_sim_base) - - /* -- show cycles, user acces to SIM, 4 /CS & 4 /IT -- */ - move.w #0x427F,SIM_MCR(crt0_sim_base) - - /* -- enable /IRQ3, 5, 6, 7 -- */ - move.b #0xE8,SIM_PPRB(crt0_sim_base) - - /* -- enable autovector on /IRQ7 -- */ - move.b #0x80,SIM_AVR(crt0_sim_base) - - /* -- test CPU type -- */ - cmp.b #_CPU349,SIM_IDR(crt0_sim_base) - bne cpu_is_68340 - -/*-------------------------------------------------------------------------------------------*/ -cpu_is_68349: - - /* -- set cpu clock -- */ - move.w #_SPEED349,SIM_SYNCR(crt0_sim_base) | clock - -sync_wait349: - btst.b #3,(SIM_SYNCR+1)(crt0_sim_base) - beq sync_wait349 - - /* to allow access to the EPLD internal registers, it is necessary - to disable the global chip-select /CS0 (which decodes every external - cycles). To do that, we initialize the 68349 internal RAM, - copy a part of the initialization code in it, and jump there. - from that moment, /CS0 is not used, therefore it can be initialized - with its default value. Its width may be incorrect, but it will be - adjusted later. The goal is to avoid any conflict with - the accesses to the EPLD registers. - When this is done, we read the RESET parameters (boot prom width - and chip-select switch) and proceed with the initialization - when all is done, we jump back to the boot prom now - decoded with a properly configured /CS0 */ - - /*-------------------------------------*/ - /* -- configure internal SRAM banks -- */ - - move.l #0x00000000,QDMM_MCR(crt0_sim_base) - move.l #_FastRam_Start+0x0005,QDMM_QBAR0(crt0_sim_base) - move.l #_FastRam_Start+0x0405,QDMM_QBAR1(crt0_sim_base) - move.l #_FastRam_Start+0x0805,QDMM_QBAR2(crt0_sim_base) - move.l #_FastRam_Start+0x0c05,QDMM_QBAR3(crt0_sim_base) - - /*--------------------------------------------------------*/ - /* -- copy to address of the 68349 initialization code -- */ - - lea.l _copy_start(%pc),crt0_ptr3 - lea.l _copy_end(%pc),crt0_ptr4 - move.l crt0_ptr4,crt0_temp - sub.l crt0_ptr3,crt0_temp - add.l #3,crt0_temp | adjust to next long word - lsr.l #2,crt0_temp - - move.l #_FastRam_Start,crt0_ptr4 -_copy_loop: - move.l (crt0_ptr3)+,(crt0_ptr4)+ - subq.l #1,crt0_temp - bne.s _copy_loop - bra.l _FastRam_Start | jump to code in internal RAM - - /*------------------------------------*/ - /* -- start of initialization code -- */ - -_copy_start: - bra.l _begin_68349_init - - /*----------------------------------------------------------*/ - /* Astecc 68349 board : chip-select initialization values */ - -_table_csepld: - dc.b (_EPLD_CS_BASE&0x0F)+0x80 | 16 bits, 0ws - dc.b 0x80 | 16 bits, 0 ws - dc.b 0x90 | 16 bits, ext /dsack - dc.b 0x90 | 16 bits, ext /dsack - -_table_cs349: - dc.l 0x003FFFF4 | Mask CS0 (4Mbytes PROM, 32bits, 1WS) - dc.l (_PROM_Start&0xFFFFFF00)+0x00000003 | Base CS0 - dc.l 0x003FFFF1 | MASK CS1 (4Mbytes RAM, 16bits, 0WS) - dc.l (_BCCram_Start&0xFFFFFF00)+0x00000003 | Base CS1 - dc.l 0x000000FF | MASK CS2 (FLEX, ext DTACK, 256 bytes) - dc.l (_FLEX_Start&0xFFFFFF00)+0x00000003 | Base CS2 - dc.l 0x000000FF | Mask CS3 (I2C, ext DTACK, 256 bytes) - dc.l (_I2C_Start&0xFFFFFF00)+0x00000003 | Base CS3 - - /*-------------------------------------------------*/ -_begin_68349_init: - - /*-------------------------------------------------*/ - /* 68349 chip select initialization - - at this stage, the width of /CS0 may be incorrect - it will be corrected later - */ - -_cs68349_init: - lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 - lea.l _table_cs349(%pc),crt0_ptr3 - - moveq.l #0x07,crt0_temp -_cs349_init2: - move.l (crt0_ptr3)+,(crt0_ptr4)+ - dbra crt0_temp,_cs349_init2 - - /*-----------------------------------------------*/ - /* -- prepare access to the internal registers --*/ - moveq.l #EPLD_SPACE,crt0_temp - movec.l crt0_temp,dfc - movec.l crt0_temp,sfc - move.l #GLUE_EPLD,crt0_glue - move.l #DRAM_EPLD,crt0_dram - - /*-------------------------------------------*/ - /* EPLD generated /CS[3..0] must be disabled */ - -_csepld_clear: - move.l crt0_glue,crt0_ptr4 - move.w #3,crt0_spare6 - clr.b crt0_temp - -_csepld_clear1: - moves.b crt0_temp,(crt0_ptr4)+ - dbra crt0_spare6,_csepld_clear1 - - /*---------------------------------------------------------*/ - /* -- get width of boot PROM, and active chip-select set --*/ - moves.b REG_BUSWIDTH(crt0_dram),crt0_csswitch - move.b crt0_csswitch,crt0_buswidth - - /* state of CS_SWITCH : sel == 0 => CPU chip_selects (/CS[3..0]) - : sel == 1 => EPLD chip_selects (/CS[3..0]) */ - and.b #1,crt0_csswitch - - /* bus width of /CS0 during reset bw[1..0] : 0 1 2 3 - bus width : 32 16 8 ext./dsackx */ - rol.b #2,crt0_buswidth - and.b #3,crt0_buswidth - - /*----------------------------------------------------*/ - /* -- configure chip select 0 with boot prom width -- */ - lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 - lea.l _table_cs349(%pc),crt0_ptr3 - move.l (crt0_ptr3)+,crt0_temp - and.b #0xFC,crt0_temp | clear PS0 & PS1 - or.b crt0_buswidth,crt0_temp | set boot PROM bus width - move.l crt0_temp,(crt0_ptr4)+ - - /*------------------------*/ - /* -- read PDCS buffer -- */ - moves.b REG_PDCS(crt0_glue),crt0_pdcs -/* move.b #0x3F,crt0_pdcs pour test */ - - - /*---------------------------------------*/ - /* -- EPLD chip-select initialization -- */ - /*---------------------------------------*/ - btst.b #0,crt0_csswitch - beq _cs_init_end - - /*--------------------------------------------*/ - /* 68349 generated /CS[3..0] must be disabled */ - lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 - lea.l _table_cs349(%pc),crt0_ptr3 - moveq.l #0x03,crt0_temp -_cs349_clear: - move.l (crt0_ptr3)+,(crt0_ptr4)+ - move.l (crt0_ptr3)+,crt0_spare6 - and.b #0xFE,crt0_spare6 | disable chip-select - move.l crt0_spare6,(crt0_ptr4)+ - dbra crt0_temp,_cs349_clear - - /*---------------------------------------------*/ - /* EPLD generated /CS[3..0] must be configured */ -_csepld_init: - move.l crt0_glue,crt0_ptr4 - lea.l _table_csepld(%pc),crt0_ptr3 - - move.b (crt0_ptr3)+,crt0_temp - or.b #0x20,crt0_temp | default width is 32 bits - tst.b crt0_buswidth | is boot PROM bus width 32 bits ? - beq _csepld1 | if not - and.b #0xDF,crt0_temp | set width to 16 bits -_csepld1: - moves.b crt0_temp,(crt0_ptr4)+ - - moveq.l #0x02,crt0_spare6 -_csepld2: - move.b (crt0_ptr3)+,crt0_temp - moves.b crt0_temp,(crt0_ptr4)+ - dbra crt0_spare6,_csepld2 - -_cs_init_end: - - /*--------------------------------------*/ - /* -- DRAM controller initialization -- */ -_dram_init: - move.w #15,crt0_temp - move.l #_ExtRam_Start,crt0_ptr3 - -_dram_init1: - clr.l (crt0_ptr3)+ | must access DRAM - dbra crt0_temp,_dram_init1 | prior to init refresh - -_dram_init2: - move.b #3,crt0_temp - moves.b crt0_temp,REG_WS(crt0_dram) | set 3 wait-states - - move.b #0x81,crt0_temp - moves.b crt0_temp,REG_REFRESH(crt0_dram) | refresh every 10µs - - move.b #0,crt0_temp - moves.b crt0_temp,REG_CONFIG(crt0_dram) | default size = 4Mbytes - - /*-----------------------*/ - /* -- configure cache -- */ -_init_cache: - move.l #0x000001E0,CACHE_MCR(crt0_sim_base) - btst.b #bit_cache,crt0_pdcs - bne _init_cache_end - or.l #0x00000001,CACHE_MCR(crt0_sim_base) - -_init_cache_end: - - /*-----------------------------*/ - /* -- timers initialization -- */ - - clr.b crt0_temp - moves.b crt0_temp,REG_TIMER1(crt0_glue) | disable timer 1 - moves.b crt0_temp,REG_TIMER2(crt0_glue) | disable timer 2 - - /*--------------------------*/ - /* -- I2C initialization -- */ - move.b #3,crt0_temp - moves.b crt0_temp,REG_I2C(crt0_glue) | tri-states I2C ports - - /*-----------------------------------------*/ - /* -- baudrate generator initialization -- */ - move.b #2,crt0_temp - moves.b crt0_temp,REG_BAUDRATE(crt0_glue) | baudrate = 38400 - - /*-------------------------------*/ - /* -- IO port initialization -- */ - clr.b crt0_temp - moves.b crt0_temp,REG_IO(crt0_glue) | set port as input - - /* -- */ - - move.l #68349,crt0_cpu_type - - - /* -- jump back to PROM -- */ - - jmp.l (_fill_test) | must be absolute long - -_copy_end: - -/*------------------------------------------------- - initialization code for the 68340 board - -------------------------------------------------*/ - - /* Astecc 68340 board : chip-select initialization values */ -_table_cs340: - dc.l 0x003FFFF0 /* Mask CS0 (4Mbytes PROM, 32bits, 0WS) */ - dc.l ((_PROM_Start&0xFFFFFF00)+0x00000003) /* Base CS0 */ - dc.l 0x0000FFFD /* MASK CS1 (RAMBCC340, 0WS, FTE) */ - dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000003) /* Base CS1 */ - dc.l 0x000000FF /* MASK CS2 (FLEX, ext DTACK, 256 bytes) */ - dc.l ((_FLEX_Start&0xFFFFFF00)+0x00000003) /* Base CS2 */ - dc.l 0x000000FF /* Mask CS3 (I2C, ext DTACK, 256 bytes) */ - dc.l ((_I2C_Start&0xFFFFFF00)+0x00000003) /* Base CS3 */ - -cpu_is_68340: - - /* -- set cpu clock -- */ - move.w #_SPEED340,SIM_SYNCR(crt0_sim_base) | clock -sync_wait340: - btst.b #3,(SIM_SYNCR+1)(crt0_sim_base) - beq sync_wait340 - - /* -- chip select initialization -- */ - lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 - lea.l _table_cs340(%pc),crt0_ptr3 - moveq.l #0x07,crt0_temp -_b_cs340: - move.l (crt0_ptr3)+,crt0_ptr5 - move.l crt0_ptr5,(crt0_ptr4)+ | pour test - dbra crt0_temp,_b_cs340 - - move.l #68340,crt0_cpu_type - move.b #0,crt0_csswitch | CPU - move.b #1,crt0_buswidth | 16 bits - - - /*------------------------------------------------- - fill RAM if COLDSTART - -------------------------------------------------*/ -_fill_test: - - tst.l crt0_boot_type - bne _dont_fill - - cmp.b #_CPU349,SIM_IDR(crt0_sim_base) - bne _fill - btst.b #bit_meminit,crt0_pdcs - bne _dont_fill - - /* fill main memory */ -_fill: - move.l #_crt0_init_stack,crt0_ptr3 | skip Astecc vars - move.l #_ExtRam_Start,crt0_temp - sub.l #_crt0_init_stack,crt0_temp - add.l #_ExtRam_Size,crt0_temp | get size - lsr.l #2,crt0_temp | ajust for long word -_fill_loop: - clr.l (crt0_ptr3)+ - subq.l #1,crt0_temp - bne _fill_loop - - cmp.b #_CPU349,SIM_IDR(crt0_sim_base) - bne _fill_bccram - - /* fill QDMM memory */ - movea.l #_FastRam_Start,crt0_ptr3 | get start - move.l #_FastRam_Size,crt0_temp | get size - lsr.l #2,crt0_temp | ajust for long word - -_QDMMfill_loop: - clr.l (crt0_ptr3)+ - subq.l #1,crt0_temp - bne _QDMMfill_loop - bra _dont_fill - - /* fill BCC memory */ -_fill_bccram: - movea.l #_BCCram_Start,crt0_ptr3 | get start - move.l #_BCCram_Size,crt0_temp | get size - lsr.l #2,crt0_temp | ajust for long word -_BCCfill_loop: - clr.l (crt0_ptr3)+ - subq.l #1,crt0_temp - bne _BCCfill_loop - - *-------------------------------------------------*/ -_dont_fill: - move.b crt0_csswitch,_AsteccCsSwitch - move.b crt0_buswidth,_AsteccBusWidth - move.l crt0_cpu_type,_AsteccCpuName - - jmp SYM(_Init68340) | Start C code (which never returns) - -/* - * Copy DATA segment, clear BSS segment, set up real stack, - * initialize heap, start C program. - * Assume that DATA and BSS sizes are multiples of 4. - */ - PUBLIC (_CopyDataClearBSSAndStart) -SYM(_CopyDataClearBSSAndStart): - lea copy_start,a0 | Get start of DATA in RAM - lea SYM(etext),a2 | Get start of DATA in ROM - cmpl a0,a2 | Are they the same? - beq.s NOCOPY | Yes, no copy necessary - lea copy_end,a1 | Get end of DATA in RAM - bra.s COPYLOOPTEST | Branch into copy loop -COPYLOOP: - movel a2@+,a0@+ | Copy word from ROM to RAM -COPYLOOPTEST: - cmpl a1,a0 | Done? - bcs.s COPYLOOP | No, skip -NOCOPY: - - lea clear_start,a0 | Get start of BSS - lea clear_end,a1 | Get end of BSS - clrl d0 | Value to set - bra.s ZEROLOOPTEST | Branch into clear loop -ZEROLOOP: - movel d0,a0@+ | Clear a word -ZEROLOOPTEST: - cmpl a1,a0 | Done? - bcs.s ZEROLOOP | No, skip - - movel #stack_init,a7 | set master stack pointer - movel d0,a7@- | environp - movel d0,a7@- | argv - movel d0,a7@- | argc - jsr SYM(boot_card) | Call C main - - PUBLIC (_mainDone) -SYM(_mainDone): - nop | Leave spot for breakpoint - movew #1,a7 | Force a double bus error - movel d0,a7@- | This should cause a RESET -/* stop #0x2700 | Stop with interrupts disabled */ - move.w #0x2700,sr - bra.s SYM(_mainDone) | Stuck forever - - .align 2 - PUBLIC (_HeapSize) -SYM (_HeapSize): - .long HeapSize - PUBLIC (_StackSize) -SYM (_StackSize): - .long StackSize -END_CODE - -BEGIN_DATA_DCL - .align 2 - PUBLIC (environ) -SYM (environ): - .long 0 - PUBLIC (_M68kSpuriousInterruptCount) -SYM (_M68kSpuriousInterruptCount): - .long 0 -END_DATA_DCL - -END - diff --git a/c/src/lib/libbsp/m68k/gen68340/start340/startfor340only.S b/c/src/lib/libbsp/m68k/gen68340/start340/startfor340only.S new file mode 100644 index 0000000000..930694f02e --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68340/start340/startfor340only.S @@ -0,0 +1,499 @@ +/* + * This file contains the entry point for the application. + * The name of this entry point is compiler dependent. + * It jumps to the BSP which is responsible for performing + * all initialization. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * Based on the `gen68360' board support package, and covered by the + * original distribution terms. + * + * Geoffroy Montel + * France Telecom - CNET/DSM/TAM/CAT + * 4, rue du Clos Courtel + * 35512 CESSON-SEVIGNE + * FRANCE + * + * e-mail: g_montel@yahoo.com + * + * $Id$ + */ + +#include "asm.h" +#include + +BEGIN_CODE + /* + * Step 1: Decide on Reset Stack Pointer and Initial Program Counter + */ +Entry: + .long SYM(m340)+1024 | 0: Initial SSP + .long start | 1: Initial PC + .long SYM(_uhoh) | 2: Bus error + .long SYM(_uhoh) | 3: Address error + .long SYM(_uhoh) | 4: Illegal instruction + .long SYM(_uhoh) | 5: Zero division + .long SYM(_uhoh) | 6: CHK, CHK2 instruction + .long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions + .long SYM(_uhoh) | 8: Privilege violation + .long SYM(_uhoh) | 9: Trace + .long SYM(_uhoh) | 10: Line 1010 emulator + .long SYM(_uhoh) | 11: Line 1111 emulator + .long SYM(_uhoh) | 12: Hardware breakpoint + .long SYM(_uhoh) | 13: Reserved for coprocessor violation + .long SYM(_uhoh) | 14: Format error + .long SYM(_uhoh) | 15: Uninitialized interrupt + .long SYM(_uhoh) | 16: Unassigned, reserved + .long SYM(_uhoh) | 17: + .long SYM(_uhoh) | 18: + .long SYM(_uhoh) | 19: + .long SYM(_uhoh) | 20: + .long SYM(_uhoh) | 21: + .long SYM(_uhoh) | 22: + .long SYM(_uhoh) | 23: + .long SYM(_spuriousInterrupt) | 24: Spurious interrupt + .long SYM(_uhoh) | 25: Level 1 interrupt autovector + .long SYM(_uhoh) | 26: Level 2 interrupt autovector + .long SYM(_uhoh) | 27: Level 3 interrupt autovector + .long SYM(_uhoh) | 28: Level 4 interrupt autovector + .long SYM(_uhoh) | 29: Level 5 interrupt autovector + .long SYM(_uhoh) | 30: Level 6 interrupt autovector + .long SYM(_uhoh) | 31: Level 7 interrupt autovector + .long SYM(_uhoh) | 32: Trap instruction (0-15) + .long SYM(_uhoh) | 33: + .long SYM(_uhoh) | 34: + .long SYM(_uhoh) | 35: + .long SYM(_uhoh) | 36: + .long SYM(_uhoh) | 37: + .long SYM(_uhoh) | 38: + .long SYM(_uhoh) | 39: + .long SYM(_uhoh) | 40: + .long SYM(_uhoh) | 41: + .long SYM(_uhoh) | 42: + .long SYM(_uhoh) | 43: + .long SYM(_uhoh) | 44: + .long SYM(_uhoh) | 45: + .long SYM(_uhoh) | 46: + .long SYM(_uhoh) | 47: + .long SYM(_uhoh) | 48: Reserved for coprocessor + .long SYM(_uhoh) | 49: + .long SYM(_uhoh) | 50: + .long SYM(_uhoh) | 51: + .long SYM(_uhoh) | 52: + .long SYM(_uhoh) | 53: + .long SYM(_uhoh) | 54: + .long SYM(_uhoh) | 55: + .long SYM(_uhoh) | 56: + .long SYM(_uhoh) | 57: + .long SYM(_uhoh) | 58: + .long SYM(_uhoh) | 59: Unassigned, reserved + .long SYM(_uhoh) | 60: + .long SYM(_uhoh) | 61: + .long SYM(_uhoh) | 62: + .long SYM(_uhoh) | 63: + .long SYM(_uhoh) | 64: User defined vectors (192) + .long SYM(_uhoh) | 65: + .long SYM(_uhoh) | 66: + .long SYM(_uhoh) | 67: + .long SYM(_uhoh) | 68: + .long SYM(_uhoh) | 69: + .long SYM(_uhoh) | 70: + .long SYM(_uhoh) | 71: + .long SYM(_uhoh) | 72: + .long SYM(_uhoh) | 73: + .long SYM(_uhoh) | 74: + .long SYM(_uhoh) | 75: + .long SYM(_uhoh) | 76: + .long SYM(_uhoh) | 77: + .long SYM(_uhoh) | 78: + .long SYM(_uhoh) | 79: + .long SYM(_uhoh) | 80: + .long SYM(_uhoh) | 81: + .long SYM(_uhoh) | 82: + .long SYM(_uhoh) | 83: + .long SYM(_uhoh) | 84: + .long SYM(_uhoh) | 85: + .long SYM(_uhoh) | 86: + .long SYM(_uhoh) | 87: + .long SYM(_uhoh) | 88: + .long SYM(_uhoh) | 89: + .long SYM(_uhoh) | 90: + .long SYM(_uhoh) | 91: + .long SYM(_uhoh) | 92: + .long SYM(_uhoh) | 93: + .long SYM(_uhoh) | 94: + .long SYM(_uhoh) | 95: + .long SYM(_uhoh) | 96: + .long SYM(_uhoh) | 97: + .long SYM(_uhoh) | 98: + .long SYM(_uhoh) | 99: + .long SYM(_uhoh) | 100: + .long SYM(_uhoh) | 101: + .long SYM(_uhoh) | 102: + .long SYM(_uhoh) | 103: + .long SYM(_uhoh) | 104: + .long SYM(_uhoh) | 105: + .long SYM(_uhoh) | 106: + .long SYM(_uhoh) | 107: + .long SYM(_uhoh) | 108: + .long SYM(_uhoh) | 109: + .long SYM(_uhoh) | 110: + .long SYM(_uhoh) | 111: + .long SYM(_uhoh) | 112: + .long SYM(_uhoh) | 113: + .long SYM(_uhoh) | 114: + .long SYM(_uhoh) | 115: + .long SYM(_uhoh) | 116: + .long SYM(_uhoh) | 117: + .long SYM(_uhoh) | 118: + .long SYM(_uhoh) | 119: + .long SYM(_uhoh) | 120: + .long SYM(_uhoh) | 121: + .long SYM(_uhoh) | 122: + .long SYM(_uhoh) | 123: + .long SYM(_uhoh) | 124: + .long SYM(_uhoh) | 125: + .long SYM(_uhoh) | 126: + .long SYM(_uhoh) | 127: + .long SYM(_uhoh) | 128: + .long SYM(_uhoh) | 129: + .long SYM(_uhoh) | 130: + .long SYM(_uhoh) | 131: + .long SYM(_uhoh) | 132: + .long SYM(_uhoh) | 133: + .long SYM(_uhoh) | 134: + .long SYM(_uhoh) | 135: + .long SYM(_uhoh) | 136: + .long SYM(_uhoh) | 137: + .long SYM(_uhoh) | 138: + .long SYM(_uhoh) | 139: + .long SYM(_uhoh) | 140: + .long SYM(_uhoh) | 141: + .long SYM(_uhoh) | 142: + .long SYM(_uhoh) | 143: + .long SYM(_uhoh) | 144: + .long SYM(_uhoh) | 145: + .long SYM(_uhoh) | 146: + .long SYM(_uhoh) | 147: + .long SYM(_uhoh) | 148: + .long SYM(_uhoh) | 149: + .long SYM(_uhoh) | 150: + .long SYM(_uhoh) | 151: + .long SYM(_uhoh) | 152: + .long SYM(_uhoh) | 153: + .long SYM(_uhoh) | 154: + .long SYM(_uhoh) | 155: + .long SYM(_uhoh) | 156: + .long SYM(_uhoh) | 157: + .long SYM(_uhoh) | 158: + .long SYM(_uhoh) | 159: + .long SYM(_uhoh) | 160: + .long SYM(_uhoh) | 161: + .long SYM(_uhoh) | 162: + .long SYM(_uhoh) | 163: + .long SYM(_uhoh) | 164: + .long SYM(_uhoh) | 165: + .long SYM(_uhoh) | 166: + .long SYM(_uhoh) | 167: + .long SYM(_uhoh) | 168: + .long SYM(_uhoh) | 169: + .long SYM(_uhoh) | 170: + .long SYM(_uhoh) | 171: + .long SYM(_uhoh) | 172: + .long SYM(_uhoh) | 173: + .long SYM(_uhoh) | 174: + .long SYM(_uhoh) | 175: + .long SYM(_uhoh) | 176: + .long SYM(_uhoh) | 177: + .long SYM(_uhoh) | 178: + .long SYM(_uhoh) | 179: + .long SYM(_uhoh) | 180: + .long SYM(_uhoh) | 181: + .long SYM(_uhoh) | 182: + .long SYM(_uhoh) | 183: + .long SYM(_uhoh) | 184: + .long SYM(_uhoh) | 185: + .long SYM(_uhoh) | 186: + .long SYM(_uhoh) | 187: + .long SYM(_uhoh) | 188: + .long SYM(_uhoh) | 189: + .long SYM(_uhoh) | 190: + .long SYM(_uhoh) | 191: + .long SYM(_uhoh) | 192: + .long SYM(_uhoh) | 193: + .long SYM(_uhoh) | 194: + .long SYM(_uhoh) | 195: + .long SYM(_uhoh) | 196: + .long SYM(_uhoh) | 197: + .long SYM(_uhoh) | 198: + .long SYM(_uhoh) | 199: + .long SYM(_uhoh) | 200: + .long SYM(_uhoh) | 201: + .long SYM(_uhoh) | 202: + .long SYM(_uhoh) | 203: + .long SYM(_uhoh) | 204: + .long SYM(_uhoh) | 205: + .long SYM(_uhoh) | 206: + .long SYM(_uhoh) | 207: + .long SYM(_uhoh) | 208: + .long SYM(_uhoh) | 209: + .long SYM(_uhoh) | 210: + .long SYM(_uhoh) | 211: + .long SYM(_uhoh) | 212: + .long SYM(_uhoh) | 213: + .long SYM(_uhoh) | 214: + .long SYM(_uhoh) | 215: + .long SYM(_uhoh) | 216: + .long SYM(_uhoh) | 217: + .long SYM(_uhoh) | 218: + .long SYM(_uhoh) | 219: + .long SYM(_uhoh) | 220: + .long SYM(_uhoh) | 221: + .long SYM(_uhoh) | 222: + .long SYM(_uhoh) | 223: + .long SYM(_uhoh) | 224: + .long SYM(_uhoh) | 225: + .long SYM(_uhoh) | 226: + .long SYM(_uhoh) | 227: + .long SYM(_uhoh) | 228: + .long SYM(_uhoh) | 229: + .long SYM(_uhoh) | 230: + .long SYM(_uhoh) | 231: + .long SYM(_uhoh) | 232: + .long SYM(_uhoh) | 233: + .long SYM(_uhoh) | 234: + .long SYM(_uhoh) | 235: + .long SYM(_uhoh) | 236: + .long SYM(_uhoh) | 237: + .long SYM(_uhoh) | 238: + .long SYM(_uhoh) | 239: + .long SYM(_uhoh) | 240: + .long SYM(_uhoh) | 241: + .long SYM(_uhoh) | 242: + .long SYM(_uhoh) | 243: + .long SYM(_uhoh) | 244: + .long SYM(_uhoh) | 245: + .long SYM(_uhoh) | 246: + .long SYM(_uhoh) | 247: + .long SYM(_uhoh) | 248: + .long SYM(_uhoh) | 249: + .long SYM(_uhoh) | 250: + .long SYM(_uhoh) | 251: + .long SYM(_uhoh) | 252: + .long SYM(_uhoh) | 253: + .long SYM(_uhoh) | 254: + .long SYM(_uhoh) | 255: + +/* + * Default trap handler + * With an oscilloscope you can see AS* stop + */ + PUBLIC (_uhoh) +SYM(_uhoh): nop | Leave spot for breakpoint + stop #0x2700 | Stop with interrupts disabled + bra.s SYM(_uhoh) | Stuck forever + +/* + * Log, but otherwise ignore, spurious interrupts + */ + PUBLIC (_spuriousInterrupt) +SYM(_spuriousInterrupt): + addql #1,SYM(_M68kSpuriousInterruptCount) + rte + +/* + * Place the low-order 3 octets of the board's ethernet address at + * a `well-known' fixed location relative to the startup location. + */ + .align 2 + .word 0 | Padding +ethernet_address_buffer: + .word 0x08F3 | Default address + .word 0xDEAD + .word 0xCAFE + +/* -- equates -- */ +.equ _PROM_Start, 0x01000000 /* CS0 */ +.equ _BCCram_Start, 0x00000000 /* CS1 */ +.equ _FLEX_Start, 0x08000000 /* CS2 */ +.equ _I2C_Start, 0x02000000 /* CS3 */ +.equ _EXTram_Start, 0x10000000 /* CS4 */ +.equ _EXTram_Size, 0x000400000 /* 4 Mbytes */ +.equ _SPEED, 0xD780 /* 25 Mhz CPU349 */ +/* .equ _SPEED, 0xD700 25 Mhz */ +/* .equ _SPEED, 0xCE00 16 Mhz */ + +BEGIN_DATA + +_crt0_init_stack: + ds.l 0x1000 +_crt0_init_stktop: + + +BEGIN_CODE + dc.l _crt0_init_stktop /* reset SP */ + dc.l _crt0_cold_start /* reset PC */ + dc.l _crt0_warm_start + + .ascii "RTEMS" + dc.w 0 + +.align 2 + +_table_cs: + /* carte Astecc - 68340 */ + dc.l 0x003FFFF0 /* Mask CS0 (4Mbytes PROM, 32bits, 0WS) */ +/* dc.l 0x003FFFFD Mask CS0 (4Mbytes PROM, 16bits, 3WS) */ + dc.l ((_PROM_Start&0xFFFFFF00)+0x00000003) /* Base CS0 */ +/* dc.l 0x0000FFF1 MASK CS1 (RAMBCC340, 0WS, FTE) */ + dc.l 0x0000FFFD /* MASK CS1 (RAMBCC340, 0WS, FTE) */ +/* dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000007) Base CS1 */ + dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000003) /* Base CS1 */ + dc.l 0x000000FF /* MASK CS2 (FLEX, ext DTACK, 256 bytes) */ + dc.l ((_FLEX_Start&0xFFFFFF00)+0x00000003) /* Base CS2 */ + dc.l 0x000000FF /* Mask CS3 (I2C, ext DTACK, 256 bytes) */ + dc.l ((_I2C_Start&0xFFFFFF00)+0x00000003) /* Base CS3 */ + +/* + * Initial PC + */ +.globl start +start: + +_crt0_cold_start: + moveq.l #0,d0 /* signal cold reset */ + bra.s _crt0_common_start + +_crt0_warm_start: + moveq.l #1,d0 /* signal warm reset */ + +_crt0_common_start: + move.w #0x2700,sr /* disable interrupts and switch to interrupt mode */ + movea.l #_crt0_init_stktop,sp /* set up initialization stack */ + + lea Entry,a0 /* Get base of vector table */ + movec a0,vbr /* Set up the VBR */ + + moveq.l #0x07,d1 + movec.l d1,dfc /* prepare access in CPU space */ + move.l #(BASE_SIM+1),d1 + moves.l d1,BASE_REG /* base initialization (must be MOVES, PCC-130795) */ + moveq.l #0x05,d1 + movec.l d1,dfc + + movea.l #BASE_SIM,a0 + + /* -- disable Bus Monitor -- */ + move.b #0,SIM_SYPCR(a0) /* system protection control register */ + + /* -- set frequency to 25.16 Mhz -- */ + move.w #_SPEED,SIM_SYNCR(a0) /* clock */ + +sync_wait: + btst.b #3,(SIM_SYNCR+1)(a0) + beq sync_wait + + /* -- enable A31-A24 -- */ + clr.b SIM_PPRA1(a0) + + /* -- show cycles, user acces to SIM, 4 /CS & 4 /IT -- */ + move.w #0x427F,SIM_MCR(a0) + + /* -- chip select initialization -- */ + lea.l SIM_MASKH0(a0),a2 + lea.l _table_cs(%pc),a1 + + moveq.l #0x07,d1 + +_b_cs: + move.l (a1)+, (a2)+ + dbra d1,_b_cs + + /* fill RAM if COLDSTART */ + tst.l d0 + bne _dont_fill + + movea.l #_EXTram_Start,a0 /* get start */ + move.l #_EXTram_Size,d1 /* get size */ + lsr.l #2,d1 /* ajust for long word */ + +_fill_loop: + clr.l (a0)+ + subq.l #1,d1 + bne _fill_loop + +_dont_fill: + jmp SYM(_Init68340) | Start C code (which never returns) + +/* + * Copy DATA segment, clear BSS segment, set up real stack, + * initialize heap, start C program. + * Assume that DATA and BSS sizes are multiples of 4. + */ + PUBLIC (_CopyDataClearBSSAndStart) +SYM(_CopyDataClearBSSAndStart): + lea copy_start,a0 | Get start of DATA in RAM + lea SYM(etext),a2 | Get start of DATA in ROM + cmpl a0,a2 | Are they the same? + beq.s NOCOPY | Yes, no copy necessary + lea copy_end,a1 | Get end of DATA in RAM + bra.s COPYLOOPTEST | Branch into copy loop +COPYLOOP: + movel a2@+,a0@+ | Copy word from ROM to RAM +COPYLOOPTEST: + cmpl a1,a0 | Done? + bcs.s COPYLOOP | No, skip +NOCOPY: + + lea clear_start,a0 | Get start of BSS + lea clear_end,a1 | Get end of BSS + clrl d0 | Value to set + bra.s ZEROLOOPTEST | Branch into clear loop +ZEROLOOP: + movel d0,a0@+ | Clear a word +ZEROLOOPTEST: + cmpl a1,a0 | Done? + bcs.s ZEROLOOP | No, skip + + movel #stack_init,a7 | set master stack pointer + movel d0,a7@- | environp + movel d0,a7@- | argv + movel d0,a7@- | argc + jsr SYM(boot_card) | Call C main + + PUBLIC (_mainDone) +SYM(_mainDone): + nop | Leave spot for breakpoint + movew #1,a7 | Force a double bus error + movel d0,a7@- | This should cause a RESET + stop #0x2700 | Stop with interrupts disabled + bra.s SYM(_mainDone) | Stuck forever + + .align 2 + PUBLIC (_HeapSize) +SYM (_HeapSize): + .long HeapSize + PUBLIC (_StackSize) +SYM (_StackSize): + .long StackSize +END_CODE + +BEGIN_DATA_DCL + .align 2 + PUBLIC (environ) +SYM (environ): + .long 0 + PUBLIC (_M68kSpuriousInterruptCount) +SYM (_M68kSpuriousInterruptCount): + .long 0 +END_DATA_DCL + +END + diff --git a/c/src/lib/libbsp/m68k/gen68340/start340/startfor340only.s b/c/src/lib/libbsp/m68k/gen68340/start340/startfor340only.s deleted file mode 100644 index 930694f02e..0000000000 --- a/c/src/lib/libbsp/m68k/gen68340/start340/startfor340only.s +++ /dev/null @@ -1,499 +0,0 @@ -/* - * This file contains the entry point for the application. - * The name of this entry point is compiler dependent. - * It jumps to the BSP which is responsible for performing - * all initialization. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may in - * the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * Based on the `gen68360' board support package, and covered by the - * original distribution terms. - * - * Geoffroy Montel - * France Telecom - CNET/DSM/TAM/CAT - * 4, rue du Clos Courtel - * 35512 CESSON-SEVIGNE - * FRANCE - * - * e-mail: g_montel@yahoo.com - * - * $Id$ - */ - -#include "asm.h" -#include - -BEGIN_CODE - /* - * Step 1: Decide on Reset Stack Pointer and Initial Program Counter - */ -Entry: - .long SYM(m340)+1024 | 0: Initial SSP - .long start | 1: Initial PC - .long SYM(_uhoh) | 2: Bus error - .long SYM(_uhoh) | 3: Address error - .long SYM(_uhoh) | 4: Illegal instruction - .long SYM(_uhoh) | 5: Zero division - .long SYM(_uhoh) | 6: CHK, CHK2 instruction - .long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions - .long SYM(_uhoh) | 8: Privilege violation - .long SYM(_uhoh) | 9: Trace - .long SYM(_uhoh) | 10: Line 1010 emulator - .long SYM(_uhoh) | 11: Line 1111 emulator - .long SYM(_uhoh) | 12: Hardware breakpoint - .long SYM(_uhoh) | 13: Reserved for coprocessor violation - .long SYM(_uhoh) | 14: Format error - .long SYM(_uhoh) | 15: Uninitialized interrupt - .long SYM(_uhoh) | 16: Unassigned, reserved - .long SYM(_uhoh) | 17: - .long SYM(_uhoh) | 18: - .long SYM(_uhoh) | 19: - .long SYM(_uhoh) | 20: - .long SYM(_uhoh) | 21: - .long SYM(_uhoh) | 22: - .long SYM(_uhoh) | 23: - .long SYM(_spuriousInterrupt) | 24: Spurious interrupt - .long SYM(_uhoh) | 25: Level 1 interrupt autovector - .long SYM(_uhoh) | 26: Level 2 interrupt autovector - .long SYM(_uhoh) | 27: Level 3 interrupt autovector - .long SYM(_uhoh) | 28: Level 4 interrupt autovector - .long SYM(_uhoh) | 29: Level 5 interrupt autovector - .long SYM(_uhoh) | 30: Level 6 interrupt autovector - .long SYM(_uhoh) | 31: Level 7 interrupt autovector - .long SYM(_uhoh) | 32: Trap instruction (0-15) - .long SYM(_uhoh) | 33: - .long SYM(_uhoh) | 34: - .long SYM(_uhoh) | 35: - .long SYM(_uhoh) | 36: - .long SYM(_uhoh) | 37: - .long SYM(_uhoh) | 38: - .long SYM(_uhoh) | 39: - .long SYM(_uhoh) | 40: - .long SYM(_uhoh) | 41: - .long SYM(_uhoh) | 42: - .long SYM(_uhoh) | 43: - .long SYM(_uhoh) | 44: - .long SYM(_uhoh) | 45: - .long SYM(_uhoh) | 46: - .long SYM(_uhoh) | 47: - .long SYM(_uhoh) | 48: Reserved for coprocessor - .long SYM(_uhoh) | 49: - .long SYM(_uhoh) | 50: - .long SYM(_uhoh) | 51: - .long SYM(_uhoh) | 52: - .long SYM(_uhoh) | 53: - .long SYM(_uhoh) | 54: - .long SYM(_uhoh) | 55: - .long SYM(_uhoh) | 56: - .long SYM(_uhoh) | 57: - .long SYM(_uhoh) | 58: - .long SYM(_uhoh) | 59: Unassigned, reserved - .long SYM(_uhoh) | 60: - .long SYM(_uhoh) | 61: - .long SYM(_uhoh) | 62: - .long SYM(_uhoh) | 63: - .long SYM(_uhoh) | 64: User defined vectors (192) - .long SYM(_uhoh) | 65: - .long SYM(_uhoh) | 66: - .long SYM(_uhoh) | 67: - .long SYM(_uhoh) | 68: - .long SYM(_uhoh) | 69: - .long SYM(_uhoh) | 70: - .long SYM(_uhoh) | 71: - .long SYM(_uhoh) | 72: - .long SYM(_uhoh) | 73: - .long SYM(_uhoh) | 74: - .long SYM(_uhoh) | 75: - .long SYM(_uhoh) | 76: - .long SYM(_uhoh) | 77: - .long SYM(_uhoh) | 78: - .long SYM(_uhoh) | 79: - .long SYM(_uhoh) | 80: - .long SYM(_uhoh) | 81: - .long SYM(_uhoh) | 82: - .long SYM(_uhoh) | 83: - .long SYM(_uhoh) | 84: - .long SYM(_uhoh) | 85: - .long SYM(_uhoh) | 86: - .long SYM(_uhoh) | 87: - .long SYM(_uhoh) | 88: - .long SYM(_uhoh) | 89: - .long SYM(_uhoh) | 90: - .long SYM(_uhoh) | 91: - .long SYM(_uhoh) | 92: - .long SYM(_uhoh) | 93: - .long SYM(_uhoh) | 94: - .long SYM(_uhoh) | 95: - .long SYM(_uhoh) | 96: - .long SYM(_uhoh) | 97: - .long SYM(_uhoh) | 98: - .long SYM(_uhoh) | 99: - .long SYM(_uhoh) | 100: - .long SYM(_uhoh) | 101: - .long SYM(_uhoh) | 102: - .long SYM(_uhoh) | 103: - .long SYM(_uhoh) | 104: - .long SYM(_uhoh) | 105: - .long SYM(_uhoh) | 106: - .long SYM(_uhoh) | 107: - .long SYM(_uhoh) | 108: - .long SYM(_uhoh) | 109: - .long SYM(_uhoh) | 110: - .long SYM(_uhoh) | 111: - .long SYM(_uhoh) | 112: - .long SYM(_uhoh) | 113: - .long SYM(_uhoh) | 114: - .long SYM(_uhoh) | 115: - .long SYM(_uhoh) | 116: - .long SYM(_uhoh) | 117: - .long SYM(_uhoh) | 118: - .long SYM(_uhoh) | 119: - .long SYM(_uhoh) | 120: - .long SYM(_uhoh) | 121: - .long SYM(_uhoh) | 122: - .long SYM(_uhoh) | 123: - .long SYM(_uhoh) | 124: - .long SYM(_uhoh) | 125: - .long SYM(_uhoh) | 126: - .long SYM(_uhoh) | 127: - .long SYM(_uhoh) | 128: - .long SYM(_uhoh) | 129: - .long SYM(_uhoh) | 130: - .long SYM(_uhoh) | 131: - .long SYM(_uhoh) | 132: - .long SYM(_uhoh) | 133: - .long SYM(_uhoh) | 134: - .long SYM(_uhoh) | 135: - .long SYM(_uhoh) | 136: - .long SYM(_uhoh) | 137: - .long SYM(_uhoh) | 138: - .long SYM(_uhoh) | 139: - .long SYM(_uhoh) | 140: - .long SYM(_uhoh) | 141: - .long SYM(_uhoh) | 142: - .long SYM(_uhoh) | 143: - .long SYM(_uhoh) | 144: - .long SYM(_uhoh) | 145: - .long SYM(_uhoh) | 146: - .long SYM(_uhoh) | 147: - .long SYM(_uhoh) | 148: - .long SYM(_uhoh) | 149: - .long SYM(_uhoh) | 150: - .long SYM(_uhoh) | 151: - .long SYM(_uhoh) | 152: - .long SYM(_uhoh) | 153: - .long SYM(_uhoh) | 154: - .long SYM(_uhoh) | 155: - .long SYM(_uhoh) | 156: - .long SYM(_uhoh) | 157: - .long SYM(_uhoh) | 158: - .long SYM(_uhoh) | 159: - .long SYM(_uhoh) | 160: - .long SYM(_uhoh) | 161: - .long SYM(_uhoh) | 162: - .long SYM(_uhoh) | 163: - .long SYM(_uhoh) | 164: - .long SYM(_uhoh) | 165: - .long SYM(_uhoh) | 166: - .long SYM(_uhoh) | 167: - .long SYM(_uhoh) | 168: - .long SYM(_uhoh) | 169: - .long SYM(_uhoh) | 170: - .long SYM(_uhoh) | 171: - .long SYM(_uhoh) | 172: - .long SYM(_uhoh) | 173: - .long SYM(_uhoh) | 174: - .long SYM(_uhoh) | 175: - .long SYM(_uhoh) | 176: - .long SYM(_uhoh) | 177: - .long SYM(_uhoh) | 178: - .long SYM(_uhoh) | 179: - .long SYM(_uhoh) | 180: - .long SYM(_uhoh) | 181: - .long SYM(_uhoh) | 182: - .long SYM(_uhoh) | 183: - .long SYM(_uhoh) | 184: - .long SYM(_uhoh) | 185: - .long SYM(_uhoh) | 186: - .long SYM(_uhoh) | 187: - .long SYM(_uhoh) | 188: - .long SYM(_uhoh) | 189: - .long SYM(_uhoh) | 190: - .long SYM(_uhoh) | 191: - .long SYM(_uhoh) | 192: - .long SYM(_uhoh) | 193: - .long SYM(_uhoh) | 194: - .long SYM(_uhoh) | 195: - .long SYM(_uhoh) | 196: - .long SYM(_uhoh) | 197: - .long SYM(_uhoh) | 198: - .long SYM(_uhoh) | 199: - .long SYM(_uhoh) | 200: - .long SYM(_uhoh) | 201: - .long SYM(_uhoh) | 202: - .long SYM(_uhoh) | 203: - .long SYM(_uhoh) | 204: - .long SYM(_uhoh) | 205: - .long SYM(_uhoh) | 206: - .long SYM(_uhoh) | 207: - .long SYM(_uhoh) | 208: - .long SYM(_uhoh) | 209: - .long SYM(_uhoh) | 210: - .long SYM(_uhoh) | 211: - .long SYM(_uhoh) | 212: - .long SYM(_uhoh) | 213: - .long SYM(_uhoh) | 214: - .long SYM(_uhoh) | 215: - .long SYM(_uhoh) | 216: - .long SYM(_uhoh) | 217: - .long SYM(_uhoh) | 218: - .long SYM(_uhoh) | 219: - .long SYM(_uhoh) | 220: - .long SYM(_uhoh) | 221: - .long SYM(_uhoh) | 222: - .long SYM(_uhoh) | 223: - .long SYM(_uhoh) | 224: - .long SYM(_uhoh) | 225: - .long SYM(_uhoh) | 226: - .long SYM(_uhoh) | 227: - .long SYM(_uhoh) | 228: - .long SYM(_uhoh) | 229: - .long SYM(_uhoh) | 230: - .long SYM(_uhoh) | 231: - .long SYM(_uhoh) | 232: - .long SYM(_uhoh) | 233: - .long SYM(_uhoh) | 234: - .long SYM(_uhoh) | 235: - .long SYM(_uhoh) | 236: - .long SYM(_uhoh) | 237: - .long SYM(_uhoh) | 238: - .long SYM(_uhoh) | 239: - .long SYM(_uhoh) | 240: - .long SYM(_uhoh) | 241: - .long SYM(_uhoh) | 242: - .long SYM(_uhoh) | 243: - .long SYM(_uhoh) | 244: - .long SYM(_uhoh) | 245: - .long SYM(_uhoh) | 246: - .long SYM(_uhoh) | 247: - .long SYM(_uhoh) | 248: - .long SYM(_uhoh) | 249: - .long SYM(_uhoh) | 250: - .long SYM(_uhoh) | 251: - .long SYM(_uhoh) | 252: - .long SYM(_uhoh) | 253: - .long SYM(_uhoh) | 254: - .long SYM(_uhoh) | 255: - -/* - * Default trap handler - * With an oscilloscope you can see AS* stop - */ - PUBLIC (_uhoh) -SYM(_uhoh): nop | Leave spot for breakpoint - stop #0x2700 | Stop with interrupts disabled - bra.s SYM(_uhoh) | Stuck forever - -/* - * Log, but otherwise ignore, spurious interrupts - */ - PUBLIC (_spuriousInterrupt) -SYM(_spuriousInterrupt): - addql #1,SYM(_M68kSpuriousInterruptCount) - rte - -/* - * Place the low-order 3 octets of the board's ethernet address at - * a `well-known' fixed location relative to the startup location. - */ - .align 2 - .word 0 | Padding -ethernet_address_buffer: - .word 0x08F3 | Default address - .word 0xDEAD - .word 0xCAFE - -/* -- equates -- */ -.equ _PROM_Start, 0x01000000 /* CS0 */ -.equ _BCCram_Start, 0x00000000 /* CS1 */ -.equ _FLEX_Start, 0x08000000 /* CS2 */ -.equ _I2C_Start, 0x02000000 /* CS3 */ -.equ _EXTram_Start, 0x10000000 /* CS4 */ -.equ _EXTram_Size, 0x000400000 /* 4 Mbytes */ -.equ _SPEED, 0xD780 /* 25 Mhz CPU349 */ -/* .equ _SPEED, 0xD700 25 Mhz */ -/* .equ _SPEED, 0xCE00 16 Mhz */ - -BEGIN_DATA - -_crt0_init_stack: - ds.l 0x1000 -_crt0_init_stktop: - - -BEGIN_CODE - dc.l _crt0_init_stktop /* reset SP */ - dc.l _crt0_cold_start /* reset PC */ - dc.l _crt0_warm_start - - .ascii "RTEMS" - dc.w 0 - -.align 2 - -_table_cs: - /* carte Astecc - 68340 */ - dc.l 0x003FFFF0 /* Mask CS0 (4Mbytes PROM, 32bits, 0WS) */ -/* dc.l 0x003FFFFD Mask CS0 (4Mbytes PROM, 16bits, 3WS) */ - dc.l ((_PROM_Start&0xFFFFFF00)+0x00000003) /* Base CS0 */ -/* dc.l 0x0000FFF1 MASK CS1 (RAMBCC340, 0WS, FTE) */ - dc.l 0x0000FFFD /* MASK CS1 (RAMBCC340, 0WS, FTE) */ -/* dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000007) Base CS1 */ - dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000003) /* Base CS1 */ - dc.l 0x000000FF /* MASK CS2 (FLEX, ext DTACK, 256 bytes) */ - dc.l ((_FLEX_Start&0xFFFFFF00)+0x00000003) /* Base CS2 */ - dc.l 0x000000FF /* Mask CS3 (I2C, ext DTACK, 256 bytes) */ - dc.l ((_I2C_Start&0xFFFFFF00)+0x00000003) /* Base CS3 */ - -/* - * Initial PC - */ -.globl start -start: - -_crt0_cold_start: - moveq.l #0,d0 /* signal cold reset */ - bra.s _crt0_common_start - -_crt0_warm_start: - moveq.l #1,d0 /* signal warm reset */ - -_crt0_common_start: - move.w #0x2700,sr /* disable interrupts and switch to interrupt mode */ - movea.l #_crt0_init_stktop,sp /* set up initialization stack */ - - lea Entry,a0 /* Get base of vector table */ - movec a0,vbr /* Set up the VBR */ - - moveq.l #0x07,d1 - movec.l d1,dfc /* prepare access in CPU space */ - move.l #(BASE_SIM+1),d1 - moves.l d1,BASE_REG /* base initialization (must be MOVES, PCC-130795) */ - moveq.l #0x05,d1 - movec.l d1,dfc - - movea.l #BASE_SIM,a0 - - /* -- disable Bus Monitor -- */ - move.b #0,SIM_SYPCR(a0) /* system protection control register */ - - /* -- set frequency to 25.16 Mhz -- */ - move.w #_SPEED,SIM_SYNCR(a0) /* clock */ - -sync_wait: - btst.b #3,(SIM_SYNCR+1)(a0) - beq sync_wait - - /* -- enable A31-A24 -- */ - clr.b SIM_PPRA1(a0) - - /* -- show cycles, user acces to SIM, 4 /CS & 4 /IT -- */ - move.w #0x427F,SIM_MCR(a0) - - /* -- chip select initialization -- */ - lea.l SIM_MASKH0(a0),a2 - lea.l _table_cs(%pc),a1 - - moveq.l #0x07,d1 - -_b_cs: - move.l (a1)+, (a2)+ - dbra d1,_b_cs - - /* fill RAM if COLDSTART */ - tst.l d0 - bne _dont_fill - - movea.l #_EXTram_Start,a0 /* get start */ - move.l #_EXTram_Size,d1 /* get size */ - lsr.l #2,d1 /* ajust for long word */ - -_fill_loop: - clr.l (a0)+ - subq.l #1,d1 - bne _fill_loop - -_dont_fill: - jmp SYM(_Init68340) | Start C code (which never returns) - -/* - * Copy DATA segment, clear BSS segment, set up real stack, - * initialize heap, start C program. - * Assume that DATA and BSS sizes are multiples of 4. - */ - PUBLIC (_CopyDataClearBSSAndStart) -SYM(_CopyDataClearBSSAndStart): - lea copy_start,a0 | Get start of DATA in RAM - lea SYM(etext),a2 | Get start of DATA in ROM - cmpl a0,a2 | Are they the same? - beq.s NOCOPY | Yes, no copy necessary - lea copy_end,a1 | Get end of DATA in RAM - bra.s COPYLOOPTEST | Branch into copy loop -COPYLOOP: - movel a2@+,a0@+ | Copy word from ROM to RAM -COPYLOOPTEST: - cmpl a1,a0 | Done? - bcs.s COPYLOOP | No, skip -NOCOPY: - - lea clear_start,a0 | Get start of BSS - lea clear_end,a1 | Get end of BSS - clrl d0 | Value to set - bra.s ZEROLOOPTEST | Branch into clear loop -ZEROLOOP: - movel d0,a0@+ | Clear a word -ZEROLOOPTEST: - cmpl a1,a0 | Done? - bcs.s ZEROLOOP | No, skip - - movel #stack_init,a7 | set master stack pointer - movel d0,a7@- | environp - movel d0,a7@- | argv - movel d0,a7@- | argc - jsr SYM(boot_card) | Call C main - - PUBLIC (_mainDone) -SYM(_mainDone): - nop | Leave spot for breakpoint - movew #1,a7 | Force a double bus error - movel d0,a7@- | This should cause a RESET - stop #0x2700 | Stop with interrupts disabled - bra.s SYM(_mainDone) | Stuck forever - - .align 2 - PUBLIC (_HeapSize) -SYM (_HeapSize): - .long HeapSize - PUBLIC (_StackSize) -SYM (_StackSize): - .long StackSize -END_CODE - -BEGIN_DATA_DCL - .align 2 - PUBLIC (environ) -SYM (environ): - .long 0 - PUBLIC (_M68kSpuriousInterruptCount) -SYM (_M68kSpuriousInterruptCount): - .long 0 -END_DATA_DCL - -END - diff --git a/c/src/lib/libbsp/m68k/gen68360/start/Makefile.in b/c/src/lib/libbsp/m68k/gen68360/start/Makefile.in index 4d339f46fc..25c914ea5a 100644 --- a/c/src/lib/libbsp/m68k/gen68360/start/Makefile.in +++ b/c/src/lib/libbsp/m68k/gen68360/start/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=start360 -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/m68k/gen68360/start/start.S b/c/src/lib/libbsp/m68k/gen68360/start/start.S new file mode 100644 index 0000000000..2c979e294f --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68360/start/start.S @@ -0,0 +1,432 @@ +/* + * + * This file contains the entry point for the application. + * The name of this entry point is compiler dependent. + * It jumps to the BSP which is responsible for performing + * all initialization. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * Based on the `gen68302' board support package, and covered by the + * original distribution terms. + * + * W. Eric Norum + * Saskatchewan Accelerator Laboratory + * University of Saskatchewan + * Saskatoon, Saskatchewan, CANADA + * eric@skatter.usask.ca + * + * $Id$ + */ + +#include "asm.h" + +BEGIN_CODE + /* + * Step 1: Decide on Reset Stack Pointer and Initial Program Counter + */ +Entry: + .long SYM(m360)+1024 | 0: Initial SSP + .long start | 1: Initial PC + .long SYM(_uhoh) | 2: Bus error + .long SYM(_uhoh) | 3: Address error + .long SYM(_uhoh) | 4: Illegal instruction + .long SYM(_uhoh) | 5: Zero division + .long SYM(_uhoh) | 6: CHK, CHK2 instruction + .long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions + .long SYM(_uhoh) | 8: Privilege violation + .long SYM(_uhoh) | 9: Trace + .long SYM(_uhoh) | 10: Line 1010 emulator + .long SYM(_uhoh) | 11: Line 1111 emulator + .long SYM(_uhoh) | 12: Hardware breakpoint + .long SYM(_uhoh) | 13: Reserved for coprocessor violation + .long SYM(_uhoh) | 14: Format error + .long SYM(_uhoh) | 15: Uninitialized interrupt + .long SYM(_uhoh) | 16: Unassigned, reserved + .long SYM(_uhoh) | 17: + .long SYM(_uhoh) | 18: + .long SYM(_uhoh) | 19: + .long SYM(_uhoh) | 20: + .long SYM(_uhoh) | 21: + .long SYM(_uhoh) | 22: + .long SYM(_uhoh) | 23: + .long SYM(_spuriousInterrupt) | 24: Spurious interrupt + .long SYM(_uhoh) | 25: Level 1 interrupt autovector + .long SYM(_uhoh) | 26: Level 2 interrupt autovector + .long SYM(_uhoh) | 27: Level 3 interrupt autovector + .long SYM(_uhoh) | 28: Level 4 interrupt autovector + .long SYM(_uhoh) | 29: Level 5 interrupt autovector + .long SYM(_uhoh) | 30: Level 6 interrupt autovector + .long SYM(_uhoh) | 31: Level 7 interrupt autovector + .long SYM(_uhoh) | 32: Trap instruction (0-15) + .long SYM(_uhoh) | 33: + .long SYM(_uhoh) | 34: + .long SYM(_uhoh) | 35: + .long SYM(_uhoh) | 36: + .long SYM(_uhoh) | 37: + .long SYM(_uhoh) | 38: + .long SYM(_uhoh) | 39: + .long SYM(_uhoh) | 40: + .long SYM(_uhoh) | 41: + .long SYM(_uhoh) | 42: + .long SYM(_uhoh) | 43: + .long SYM(_uhoh) | 44: + .long SYM(_uhoh) | 45: + .long SYM(_uhoh) | 46: + .long SYM(_uhoh) | 47: + .long SYM(_uhoh) | 48: Reserved for coprocessor + .long SYM(_uhoh) | 49: + .long SYM(_uhoh) | 50: + .long SYM(_uhoh) | 51: + .long SYM(_uhoh) | 52: + .long SYM(_uhoh) | 53: + .long SYM(_uhoh) | 54: + .long SYM(_uhoh) | 55: + .long SYM(_uhoh) | 56: + .long SYM(_uhoh) | 57: + .long SYM(_uhoh) | 58: + .long SYM(_uhoh) | 59: Unassigned, reserved + .long SYM(_uhoh) | 60: + .long SYM(_uhoh) | 61: + .long SYM(_uhoh) | 62: + .long SYM(_uhoh) | 63: + .long SYM(_uhoh) | 64: User defined vectors (192) + .long SYM(_uhoh) | 65: + .long SYM(_uhoh) | 66: + .long SYM(_uhoh) | 67: + .long SYM(_uhoh) | 68: + .long SYM(_uhoh) | 69: + .long SYM(_uhoh) | 70: + .long SYM(_uhoh) | 71: + .long SYM(_uhoh) | 72: + .long SYM(_uhoh) | 73: + .long SYM(_uhoh) | 74: + .long SYM(_uhoh) | 75: + .long SYM(_uhoh) | 76: + .long SYM(_uhoh) | 77: + .long SYM(_uhoh) | 78: + .long SYM(_uhoh) | 79: + .long SYM(_uhoh) | 80: + .long SYM(_uhoh) | 81: + .long SYM(_uhoh) | 82: + .long SYM(_uhoh) | 83: + .long SYM(_uhoh) | 84: + .long SYM(_uhoh) | 85: + .long SYM(_uhoh) | 86: + .long SYM(_uhoh) | 87: + .long SYM(_uhoh) | 88: + .long SYM(_uhoh) | 89: + .long SYM(_uhoh) | 90: + .long SYM(_uhoh) | 91: + .long SYM(_uhoh) | 92: + .long SYM(_uhoh) | 93: + .long SYM(_uhoh) | 94: + .long SYM(_uhoh) | 95: + .long SYM(_uhoh) | 96: + .long SYM(_uhoh) | 97: + .long SYM(_uhoh) | 98: + .long SYM(_uhoh) | 99: + .long SYM(_uhoh) | 100: + .long SYM(_uhoh) | 101: + .long SYM(_uhoh) | 102: + .long SYM(_uhoh) | 103: + .long SYM(_uhoh) | 104: + .long SYM(_uhoh) | 105: + .long SYM(_uhoh) | 106: + .long SYM(_uhoh) | 107: + .long SYM(_uhoh) | 108: + .long SYM(_uhoh) | 109: + .long SYM(_uhoh) | 110: + .long SYM(_uhoh) | 111: + .long SYM(_uhoh) | 112: + .long SYM(_uhoh) | 113: + .long SYM(_uhoh) | 114: + .long SYM(_uhoh) | 115: + .long SYM(_uhoh) | 116: + .long SYM(_uhoh) | 117: + .long SYM(_uhoh) | 118: + .long SYM(_uhoh) | 119: + .long SYM(_uhoh) | 120: + .long SYM(_uhoh) | 121: + .long SYM(_uhoh) | 122: + .long SYM(_uhoh) | 123: + .long SYM(_uhoh) | 124: + .long SYM(_uhoh) | 125: + .long SYM(_uhoh) | 126: + .long SYM(_uhoh) | 127: + .long SYM(_uhoh) | 128: + .long SYM(_uhoh) | 129: + .long SYM(_uhoh) | 130: + .long SYM(_uhoh) | 131: + .long SYM(_uhoh) | 132: + .long SYM(_uhoh) | 133: + .long SYM(_uhoh) | 134: + .long SYM(_uhoh) | 135: + .long SYM(_uhoh) | 136: + .long SYM(_uhoh) | 137: + .long SYM(_uhoh) | 138: + .long SYM(_uhoh) | 139: + .long SYM(_uhoh) | 140: + .long SYM(_uhoh) | 141: + .long SYM(_uhoh) | 142: + .long SYM(_uhoh) | 143: + .long SYM(_uhoh) | 144: + .long SYM(_uhoh) | 145: + .long SYM(_uhoh) | 146: + .long SYM(_uhoh) | 147: + .long SYM(_uhoh) | 148: + .long SYM(_uhoh) | 149: + .long SYM(_uhoh) | 150: + .long SYM(_uhoh) | 151: + .long SYM(_uhoh) | 152: + .long SYM(_uhoh) | 153: + .long SYM(_uhoh) | 154: + .long SYM(_uhoh) | 155: + .long SYM(_uhoh) | 156: + .long SYM(_uhoh) | 157: + .long SYM(_uhoh) | 158: + .long SYM(_uhoh) | 159: + .long SYM(_uhoh) | 160: + .long SYM(_uhoh) | 161: + .long SYM(_uhoh) | 162: + .long SYM(_uhoh) | 163: + .long SYM(_uhoh) | 164: + .long SYM(_uhoh) | 165: + .long SYM(_uhoh) | 166: + .long SYM(_uhoh) | 167: + .long SYM(_uhoh) | 168: + .long SYM(_uhoh) | 169: + .long SYM(_uhoh) | 170: + .long SYM(_uhoh) | 171: + .long SYM(_uhoh) | 172: + .long SYM(_uhoh) | 173: + .long SYM(_uhoh) | 174: + .long SYM(_uhoh) | 175: + .long SYM(_uhoh) | 176: + .long SYM(_uhoh) | 177: + .long SYM(_uhoh) | 178: + .long SYM(_uhoh) | 179: + .long SYM(_uhoh) | 180: + .long SYM(_uhoh) | 181: + .long SYM(_uhoh) | 182: + .long SYM(_uhoh) | 183: + .long SYM(_uhoh) | 184: + .long SYM(_uhoh) | 185: + .long SYM(_uhoh) | 186: + .long SYM(_uhoh) | 187: + .long SYM(_uhoh) | 188: + .long SYM(_uhoh) | 189: + .long SYM(_uhoh) | 190: + .long SYM(_uhoh) | 191: + .long SYM(_uhoh) | 192: + .long SYM(_uhoh) | 193: + .long SYM(_uhoh) | 194: + .long SYM(_uhoh) | 195: + .long SYM(_uhoh) | 196: + .long SYM(_uhoh) | 197: + .long SYM(_uhoh) | 198: + .long SYM(_uhoh) | 199: + .long SYM(_uhoh) | 200: + .long SYM(_uhoh) | 201: + .long SYM(_uhoh) | 202: + .long SYM(_uhoh) | 203: + .long SYM(_uhoh) | 204: + .long SYM(_uhoh) | 205: + .long SYM(_uhoh) | 206: + .long SYM(_uhoh) | 207: + .long SYM(_uhoh) | 208: + .long SYM(_uhoh) | 209: + .long SYM(_uhoh) | 210: + .long SYM(_uhoh) | 211: + .long SYM(_uhoh) | 212: + .long SYM(_uhoh) | 213: + .long SYM(_uhoh) | 214: + .long SYM(_uhoh) | 215: + .long SYM(_uhoh) | 216: + .long SYM(_uhoh) | 217: + .long SYM(_uhoh) | 218: + .long SYM(_uhoh) | 219: + .long SYM(_uhoh) | 220: + .long SYM(_uhoh) | 221: + .long SYM(_uhoh) | 222: + .long SYM(_uhoh) | 223: + .long SYM(_uhoh) | 224: + .long SYM(_uhoh) | 225: + .long SYM(_uhoh) | 226: + .long SYM(_uhoh) | 227: + .long SYM(_uhoh) | 228: + .long SYM(_uhoh) | 229: + .long SYM(_uhoh) | 230: + .long SYM(_uhoh) | 231: + .long SYM(_uhoh) | 232: + .long SYM(_uhoh) | 233: + .long SYM(_uhoh) | 234: + .long SYM(_uhoh) | 235: + .long SYM(_uhoh) | 236: + .long SYM(_uhoh) | 237: + .long SYM(_uhoh) | 238: + .long SYM(_uhoh) | 239: + .long SYM(_uhoh) | 240: + .long SYM(_uhoh) | 241: + .long SYM(_uhoh) | 242: + .long SYM(_uhoh) | 243: + .long SYM(_uhoh) | 244: + .long SYM(_uhoh) | 245: + .long SYM(_uhoh) | 246: + .long SYM(_uhoh) | 247: + .long SYM(_uhoh) | 248: + .long SYM(_uhoh) | 249: + .long SYM(_uhoh) | 250: + .long SYM(_uhoh) | 251: + .long SYM(_uhoh) | 252: + .long SYM(_uhoh) | 253: + .long SYM(_uhoh) | 254: + .long SYM(_uhoh) | 255: + +/* + * Default trap handler + * With an oscilloscope you can see AS* stop + */ + PUBLIC (_uhoh) +SYM(_uhoh): nop | Leave spot for breakpoint + stop #0x2700 | Stop with interrupts disabled + bra.s SYM(_uhoh) | Stuck forever + +/* + * Log, but otherwise ignore, spurious interrupts + */ + PUBLIC (_spuriousInterrupt) +SYM(_spuriousInterrupt): + addql #1,SYM(_M68kSpuriousInterruptCount) + rte + +/* + * Place the low-order 3 octets of the board's ethernet address at + * a `well-known' fixed location relative to the startup location. + */ + .align 2 + .word 0 | Padding +ethernet_address_buffer: + .word 0x08F3 | Default address + .word 0xDEAD + .word 0xCAFE + +/* + * Initial PC + */ +.globl start +start: + /* + * Step 2: Stay in Supervisor Mode + */ +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) + oriw #0x3000,sr | Switch to Master Stack Pointer + lea SYM(m360)+1024-64,a7 | Put stack in dual-port ram + | a little below the interrupt stack +#endif + + /* + * Step 3: Write the VBR + */ + lea Entry,a0 | Get base of vector table + movec a0,vbr | Set up the VBR + + /* + * Step 4: Write the MBAR + */ + movec dfc,d1 | Save destination register + moveq #7,d0 | CPU-space funcction code + movec d0,dfc | Set destination function code register + movel #SYM(m360)+0x101,d0 | MBAR value (mask CPU space accesses) + movesl d0,0x3FF00 | Set MBAR + movec d1,dfc | Restore destination register + + /* + * Step 5: Verify a dual-port RAM location + */ + lea SYM(m360),a0 | Point a0 to first DPRAM location + moveb #0x33,d0 | Set the test value + moveb d0,a0@ | Set the memory location + cmpb a0@,d0 | Does it read back? + bne SYM(_uhoh) | If not, bad news! + notb d0 | Flip bits + moveb d0,a0@ | Set the memory location + cmpb a0@,d0 | Does it read back? + bne SYM(_uhoh) | If not, bad news! + + /* + * Remaining steps are handled by C code + */ + jmp SYM(_Init68360) | Start C code (which never returns) + +/* + * Copy DATA segment, clear BSS segment, set up real stack, + * initialize heap, start C program. + * Assume that DATA and BSS sizes are multiples of 4. + */ + PUBLIC (_CopyDataClearBSSAndStart) +SYM(_CopyDataClearBSSAndStart): + lea copy_start,a0 | Get start of DATA in RAM + lea SYM(etext),a2 | Get start of DATA in ROM + cmpl a0,a2 | Are they the same? + beq.s NOCOPY | Yes, no copy necessary + lea copy_end,a1 | Get end of DATA in RAM + bra.s COPYLOOPTEST | Branch into copy loop +COPYLOOP: + movel a2@+,a0@+ | Copy word from ROM to RAM +COPYLOOPTEST: + cmpl a1,a0 | Done? + bcs.s COPYLOOP | No, skip +NOCOPY: + + lea clear_start,a0 | Get start of BSS + lea clear_end,a1 | Get end of BSS + clrl d0 | Value to set + bra.s ZEROLOOPTEST | Branch into clear loop +ZEROLOOP: + movel d0,a0@+ | Clear a word +ZEROLOOPTEST: + cmpl a1,a0 | Done? + bcs.s ZEROLOOP | No, skip + + movel #stack_init,a7 | set master stack pointer + movel d0,a7@- | environp + movel d0,a7@- | argv + movel d0,a7@- | argc + jsr SYM(boot_card) | Call C main + + PUBLIC (_mainDone) +SYM(_mainDone): + nop | Leave spot for breakpoint + movew #1,a7 | Force a double bus error + movel d0,a7@- | This should cause a RESET + stop #0x2700 | Stop with interrupts disabled + bra.s SYM(_mainDone) | Stuck forever + + .align 2 + PUBLIC (_HeapSize) +SYM (_HeapSize): + .long HeapSize + PUBLIC (_StackSize) +SYM (_StackSize): + .long StackSize +END_CODE + +BEGIN_DATA_DCL + .align 2 + PUBLIC (environ) +SYM (environ): + .long 0 + PUBLIC (_M68kSpuriousInterruptCount) +SYM (_M68kSpuriousInterruptCount): + .long 0 +END_DATA_DCL + +END + diff --git a/c/src/lib/libbsp/m68k/gen68360/start/start360.s b/c/src/lib/libbsp/m68k/gen68360/start/start360.s deleted file mode 100644 index 2c979e294f..0000000000 --- a/c/src/lib/libbsp/m68k/gen68360/start/start360.s +++ /dev/null @@ -1,432 +0,0 @@ -/* - * - * This file contains the entry point for the application. - * The name of this entry point is compiler dependent. - * It jumps to the BSP which is responsible for performing - * all initialization. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may in - * the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * Based on the `gen68302' board support package, and covered by the - * original distribution terms. - * - * W. Eric Norum - * Saskatchewan Accelerator Laboratory - * University of Saskatchewan - * Saskatoon, Saskatchewan, CANADA - * eric@skatter.usask.ca - * - * $Id$ - */ - -#include "asm.h" - -BEGIN_CODE - /* - * Step 1: Decide on Reset Stack Pointer and Initial Program Counter - */ -Entry: - .long SYM(m360)+1024 | 0: Initial SSP - .long start | 1: Initial PC - .long SYM(_uhoh) | 2: Bus error - .long SYM(_uhoh) | 3: Address error - .long SYM(_uhoh) | 4: Illegal instruction - .long SYM(_uhoh) | 5: Zero division - .long SYM(_uhoh) | 6: CHK, CHK2 instruction - .long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions - .long SYM(_uhoh) | 8: Privilege violation - .long SYM(_uhoh) | 9: Trace - .long SYM(_uhoh) | 10: Line 1010 emulator - .long SYM(_uhoh) | 11: Line 1111 emulator - .long SYM(_uhoh) | 12: Hardware breakpoint - .long SYM(_uhoh) | 13: Reserved for coprocessor violation - .long SYM(_uhoh) | 14: Format error - .long SYM(_uhoh) | 15: Uninitialized interrupt - .long SYM(_uhoh) | 16: Unassigned, reserved - .long SYM(_uhoh) | 17: - .long SYM(_uhoh) | 18: - .long SYM(_uhoh) | 19: - .long SYM(_uhoh) | 20: - .long SYM(_uhoh) | 21: - .long SYM(_uhoh) | 22: - .long SYM(_uhoh) | 23: - .long SYM(_spuriousInterrupt) | 24: Spurious interrupt - .long SYM(_uhoh) | 25: Level 1 interrupt autovector - .long SYM(_uhoh) | 26: Level 2 interrupt autovector - .long SYM(_uhoh) | 27: Level 3 interrupt autovector - .long SYM(_uhoh) | 28: Level 4 interrupt autovector - .long SYM(_uhoh) | 29: Level 5 interrupt autovector - .long SYM(_uhoh) | 30: Level 6 interrupt autovector - .long SYM(_uhoh) | 31: Level 7 interrupt autovector - .long SYM(_uhoh) | 32: Trap instruction (0-15) - .long SYM(_uhoh) | 33: - .long SYM(_uhoh) | 34: - .long SYM(_uhoh) | 35: - .long SYM(_uhoh) | 36: - .long SYM(_uhoh) | 37: - .long SYM(_uhoh) | 38: - .long SYM(_uhoh) | 39: - .long SYM(_uhoh) | 40: - .long SYM(_uhoh) | 41: - .long SYM(_uhoh) | 42: - .long SYM(_uhoh) | 43: - .long SYM(_uhoh) | 44: - .long SYM(_uhoh) | 45: - .long SYM(_uhoh) | 46: - .long SYM(_uhoh) | 47: - .long SYM(_uhoh) | 48: Reserved for coprocessor - .long SYM(_uhoh) | 49: - .long SYM(_uhoh) | 50: - .long SYM(_uhoh) | 51: - .long SYM(_uhoh) | 52: - .long SYM(_uhoh) | 53: - .long SYM(_uhoh) | 54: - .long SYM(_uhoh) | 55: - .long SYM(_uhoh) | 56: - .long SYM(_uhoh) | 57: - .long SYM(_uhoh) | 58: - .long SYM(_uhoh) | 59: Unassigned, reserved - .long SYM(_uhoh) | 60: - .long SYM(_uhoh) | 61: - .long SYM(_uhoh) | 62: - .long SYM(_uhoh) | 63: - .long SYM(_uhoh) | 64: User defined vectors (192) - .long SYM(_uhoh) | 65: - .long SYM(_uhoh) | 66: - .long SYM(_uhoh) | 67: - .long SYM(_uhoh) | 68: - .long SYM(_uhoh) | 69: - .long SYM(_uhoh) | 70: - .long SYM(_uhoh) | 71: - .long SYM(_uhoh) | 72: - .long SYM(_uhoh) | 73: - .long SYM(_uhoh) | 74: - .long SYM(_uhoh) | 75: - .long SYM(_uhoh) | 76: - .long SYM(_uhoh) | 77: - .long SYM(_uhoh) | 78: - .long SYM(_uhoh) | 79: - .long SYM(_uhoh) | 80: - .long SYM(_uhoh) | 81: - .long SYM(_uhoh) | 82: - .long SYM(_uhoh) | 83: - .long SYM(_uhoh) | 84: - .long SYM(_uhoh) | 85: - .long SYM(_uhoh) | 86: - .long SYM(_uhoh) | 87: - .long SYM(_uhoh) | 88: - .long SYM(_uhoh) | 89: - .long SYM(_uhoh) | 90: - .long SYM(_uhoh) | 91: - .long SYM(_uhoh) | 92: - .long SYM(_uhoh) | 93: - .long SYM(_uhoh) | 94: - .long SYM(_uhoh) | 95: - .long SYM(_uhoh) | 96: - .long SYM(_uhoh) | 97: - .long SYM(_uhoh) | 98: - .long SYM(_uhoh) | 99: - .long SYM(_uhoh) | 100: - .long SYM(_uhoh) | 101: - .long SYM(_uhoh) | 102: - .long SYM(_uhoh) | 103: - .long SYM(_uhoh) | 104: - .long SYM(_uhoh) | 105: - .long SYM(_uhoh) | 106: - .long SYM(_uhoh) | 107: - .long SYM(_uhoh) | 108: - .long SYM(_uhoh) | 109: - .long SYM(_uhoh) | 110: - .long SYM(_uhoh) | 111: - .long SYM(_uhoh) | 112: - .long SYM(_uhoh) | 113: - .long SYM(_uhoh) | 114: - .long SYM(_uhoh) | 115: - .long SYM(_uhoh) | 116: - .long SYM(_uhoh) | 117: - .long SYM(_uhoh) | 118: - .long SYM(_uhoh) | 119: - .long SYM(_uhoh) | 120: - .long SYM(_uhoh) | 121: - .long SYM(_uhoh) | 122: - .long SYM(_uhoh) | 123: - .long SYM(_uhoh) | 124: - .long SYM(_uhoh) | 125: - .long SYM(_uhoh) | 126: - .long SYM(_uhoh) | 127: - .long SYM(_uhoh) | 128: - .long SYM(_uhoh) | 129: - .long SYM(_uhoh) | 130: - .long SYM(_uhoh) | 131: - .long SYM(_uhoh) | 132: - .long SYM(_uhoh) | 133: - .long SYM(_uhoh) | 134: - .long SYM(_uhoh) | 135: - .long SYM(_uhoh) | 136: - .long SYM(_uhoh) | 137: - .long SYM(_uhoh) | 138: - .long SYM(_uhoh) | 139: - .long SYM(_uhoh) | 140: - .long SYM(_uhoh) | 141: - .long SYM(_uhoh) | 142: - .long SYM(_uhoh) | 143: - .long SYM(_uhoh) | 144: - .long SYM(_uhoh) | 145: - .long SYM(_uhoh) | 146: - .long SYM(_uhoh) | 147: - .long SYM(_uhoh) | 148: - .long SYM(_uhoh) | 149: - .long SYM(_uhoh) | 150: - .long SYM(_uhoh) | 151: - .long SYM(_uhoh) | 152: - .long SYM(_uhoh) | 153: - .long SYM(_uhoh) | 154: - .long SYM(_uhoh) | 155: - .long SYM(_uhoh) | 156: - .long SYM(_uhoh) | 157: - .long SYM(_uhoh) | 158: - .long SYM(_uhoh) | 159: - .long SYM(_uhoh) | 160: - .long SYM(_uhoh) | 161: - .long SYM(_uhoh) | 162: - .long SYM(_uhoh) | 163: - .long SYM(_uhoh) | 164: - .long SYM(_uhoh) | 165: - .long SYM(_uhoh) | 166: - .long SYM(_uhoh) | 167: - .long SYM(_uhoh) | 168: - .long SYM(_uhoh) | 169: - .long SYM(_uhoh) | 170: - .long SYM(_uhoh) | 171: - .long SYM(_uhoh) | 172: - .long SYM(_uhoh) | 173: - .long SYM(_uhoh) | 174: - .long SYM(_uhoh) | 175: - .long SYM(_uhoh) | 176: - .long SYM(_uhoh) | 177: - .long SYM(_uhoh) | 178: - .long SYM(_uhoh) | 179: - .long SYM(_uhoh) | 180: - .long SYM(_uhoh) | 181: - .long SYM(_uhoh) | 182: - .long SYM(_uhoh) | 183: - .long SYM(_uhoh) | 184: - .long SYM(_uhoh) | 185: - .long SYM(_uhoh) | 186: - .long SYM(_uhoh) | 187: - .long SYM(_uhoh) | 188: - .long SYM(_uhoh) | 189: - .long SYM(_uhoh) | 190: - .long SYM(_uhoh) | 191: - .long SYM(_uhoh) | 192: - .long SYM(_uhoh) | 193: - .long SYM(_uhoh) | 194: - .long SYM(_uhoh) | 195: - .long SYM(_uhoh) | 196: - .long SYM(_uhoh) | 197: - .long SYM(_uhoh) | 198: - .long SYM(_uhoh) | 199: - .long SYM(_uhoh) | 200: - .long SYM(_uhoh) | 201: - .long SYM(_uhoh) | 202: - .long SYM(_uhoh) | 203: - .long SYM(_uhoh) | 204: - .long SYM(_uhoh) | 205: - .long SYM(_uhoh) | 206: - .long SYM(_uhoh) | 207: - .long SYM(_uhoh) | 208: - .long SYM(_uhoh) | 209: - .long SYM(_uhoh) | 210: - .long SYM(_uhoh) | 211: - .long SYM(_uhoh) | 212: - .long SYM(_uhoh) | 213: - .long SYM(_uhoh) | 214: - .long SYM(_uhoh) | 215: - .long SYM(_uhoh) | 216: - .long SYM(_uhoh) | 217: - .long SYM(_uhoh) | 218: - .long SYM(_uhoh) | 219: - .long SYM(_uhoh) | 220: - .long SYM(_uhoh) | 221: - .long SYM(_uhoh) | 222: - .long SYM(_uhoh) | 223: - .long SYM(_uhoh) | 224: - .long SYM(_uhoh) | 225: - .long SYM(_uhoh) | 226: - .long SYM(_uhoh) | 227: - .long SYM(_uhoh) | 228: - .long SYM(_uhoh) | 229: - .long SYM(_uhoh) | 230: - .long SYM(_uhoh) | 231: - .long SYM(_uhoh) | 232: - .long SYM(_uhoh) | 233: - .long SYM(_uhoh) | 234: - .long SYM(_uhoh) | 235: - .long SYM(_uhoh) | 236: - .long SYM(_uhoh) | 237: - .long SYM(_uhoh) | 238: - .long SYM(_uhoh) | 239: - .long SYM(_uhoh) | 240: - .long SYM(_uhoh) | 241: - .long SYM(_uhoh) | 242: - .long SYM(_uhoh) | 243: - .long SYM(_uhoh) | 244: - .long SYM(_uhoh) | 245: - .long SYM(_uhoh) | 246: - .long SYM(_uhoh) | 247: - .long SYM(_uhoh) | 248: - .long SYM(_uhoh) | 249: - .long SYM(_uhoh) | 250: - .long SYM(_uhoh) | 251: - .long SYM(_uhoh) | 252: - .long SYM(_uhoh) | 253: - .long SYM(_uhoh) | 254: - .long SYM(_uhoh) | 255: - -/* - * Default trap handler - * With an oscilloscope you can see AS* stop - */ - PUBLIC (_uhoh) -SYM(_uhoh): nop | Leave spot for breakpoint - stop #0x2700 | Stop with interrupts disabled - bra.s SYM(_uhoh) | Stuck forever - -/* - * Log, but otherwise ignore, spurious interrupts - */ - PUBLIC (_spuriousInterrupt) -SYM(_spuriousInterrupt): - addql #1,SYM(_M68kSpuriousInterruptCount) - rte - -/* - * Place the low-order 3 octets of the board's ethernet address at - * a `well-known' fixed location relative to the startup location. - */ - .align 2 - .word 0 | Padding -ethernet_address_buffer: - .word 0x08F3 | Default address - .word 0xDEAD - .word 0xCAFE - -/* - * Initial PC - */ -.globl start -start: - /* - * Step 2: Stay in Supervisor Mode - */ -#if ( M68K_HAS_SEPARATE_STACKS == 1 ) - oriw #0x3000,sr | Switch to Master Stack Pointer - lea SYM(m360)+1024-64,a7 | Put stack in dual-port ram - | a little below the interrupt stack -#endif - - /* - * Step 3: Write the VBR - */ - lea Entry,a0 | Get base of vector table - movec a0,vbr | Set up the VBR - - /* - * Step 4: Write the MBAR - */ - movec dfc,d1 | Save destination register - moveq #7,d0 | CPU-space funcction code - movec d0,dfc | Set destination function code register - movel #SYM(m360)+0x101,d0 | MBAR value (mask CPU space accesses) - movesl d0,0x3FF00 | Set MBAR - movec d1,dfc | Restore destination register - - /* - * Step 5: Verify a dual-port RAM location - */ - lea SYM(m360),a0 | Point a0 to first DPRAM location - moveb #0x33,d0 | Set the test value - moveb d0,a0@ | Set the memory location - cmpb a0@,d0 | Does it read back? - bne SYM(_uhoh) | If not, bad news! - notb d0 | Flip bits - moveb d0,a0@ | Set the memory location - cmpb a0@,d0 | Does it read back? - bne SYM(_uhoh) | If not, bad news! - - /* - * Remaining steps are handled by C code - */ - jmp SYM(_Init68360) | Start C code (which never returns) - -/* - * Copy DATA segment, clear BSS segment, set up real stack, - * initialize heap, start C program. - * Assume that DATA and BSS sizes are multiples of 4. - */ - PUBLIC (_CopyDataClearBSSAndStart) -SYM(_CopyDataClearBSSAndStart): - lea copy_start,a0 | Get start of DATA in RAM - lea SYM(etext),a2 | Get start of DATA in ROM - cmpl a0,a2 | Are they the same? - beq.s NOCOPY | Yes, no copy necessary - lea copy_end,a1 | Get end of DATA in RAM - bra.s COPYLOOPTEST | Branch into copy loop -COPYLOOP: - movel a2@+,a0@+ | Copy word from ROM to RAM -COPYLOOPTEST: - cmpl a1,a0 | Done? - bcs.s COPYLOOP | No, skip -NOCOPY: - - lea clear_start,a0 | Get start of BSS - lea clear_end,a1 | Get end of BSS - clrl d0 | Value to set - bra.s ZEROLOOPTEST | Branch into clear loop -ZEROLOOP: - movel d0,a0@+ | Clear a word -ZEROLOOPTEST: - cmpl a1,a0 | Done? - bcs.s ZEROLOOP | No, skip - - movel #stack_init,a7 | set master stack pointer - movel d0,a7@- | environp - movel d0,a7@- | argv - movel d0,a7@- | argc - jsr SYM(boot_card) | Call C main - - PUBLIC (_mainDone) -SYM(_mainDone): - nop | Leave spot for breakpoint - movew #1,a7 | Force a double bus error - movel d0,a7@- | This should cause a RESET - stop #0x2700 | Stop with interrupts disabled - bra.s SYM(_mainDone) | Stuck forever - - .align 2 - PUBLIC (_HeapSize) -SYM (_HeapSize): - .long HeapSize - PUBLIC (_StackSize) -SYM (_StackSize): - .long StackSize -END_CODE - -BEGIN_DATA_DCL - .align 2 - PUBLIC (environ) -SYM (environ): - .long 0 - PUBLIC (_M68kSpuriousInterruptCount) -SYM (_M68kSpuriousInterruptCount): - .long 0 -END_DATA_DCL - -END - diff --git a/c/src/lib/libbsp/m68k/gen68360/start360/Makefile.in b/c/src/lib/libbsp/m68k/gen68360/start360/Makefile.in index 4d339f46fc..25c914ea5a 100644 --- a/c/src/lib/libbsp/m68k/gen68360/start360/Makefile.in +++ b/c/src/lib/libbsp/m68k/gen68360/start360/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=start360 -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/m68k/gen68360/start360/start360.S b/c/src/lib/libbsp/m68k/gen68360/start360/start360.S new file mode 100644 index 0000000000..2c979e294f --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68360/start360/start360.S @@ -0,0 +1,432 @@ +/* + * + * This file contains the entry point for the application. + * The name of this entry point is compiler dependent. + * It jumps to the BSP which is responsible for performing + * all initialization. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * Based on the `gen68302' board support package, and covered by the + * original distribution terms. + * + * W. Eric Norum + * Saskatchewan Accelerator Laboratory + * University of Saskatchewan + * Saskatoon, Saskatchewan, CANADA + * eric@skatter.usask.ca + * + * $Id$ + */ + +#include "asm.h" + +BEGIN_CODE + /* + * Step 1: Decide on Reset Stack Pointer and Initial Program Counter + */ +Entry: + .long SYM(m360)+1024 | 0: Initial SSP + .long start | 1: Initial PC + .long SYM(_uhoh) | 2: Bus error + .long SYM(_uhoh) | 3: Address error + .long SYM(_uhoh) | 4: Illegal instruction + .long SYM(_uhoh) | 5: Zero division + .long SYM(_uhoh) | 6: CHK, CHK2 instruction + .long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions + .long SYM(_uhoh) | 8: Privilege violation + .long SYM(_uhoh) | 9: Trace + .long SYM(_uhoh) | 10: Line 1010 emulator + .long SYM(_uhoh) | 11: Line 1111 emulator + .long SYM(_uhoh) | 12: Hardware breakpoint + .long SYM(_uhoh) | 13: Reserved for coprocessor violation + .long SYM(_uhoh) | 14: Format error + .long SYM(_uhoh) | 15: Uninitialized interrupt + .long SYM(_uhoh) | 16: Unassigned, reserved + .long SYM(_uhoh) | 17: + .long SYM(_uhoh) | 18: + .long SYM(_uhoh) | 19: + .long SYM(_uhoh) | 20: + .long SYM(_uhoh) | 21: + .long SYM(_uhoh) | 22: + .long SYM(_uhoh) | 23: + .long SYM(_spuriousInterrupt) | 24: Spurious interrupt + .long SYM(_uhoh) | 25: Level 1 interrupt autovector + .long SYM(_uhoh) | 26: Level 2 interrupt autovector + .long SYM(_uhoh) | 27: Level 3 interrupt autovector + .long SYM(_uhoh) | 28: Level 4 interrupt autovector + .long SYM(_uhoh) | 29: Level 5 interrupt autovector + .long SYM(_uhoh) | 30: Level 6 interrupt autovector + .long SYM(_uhoh) | 31: Level 7 interrupt autovector + .long SYM(_uhoh) | 32: Trap instruction (0-15) + .long SYM(_uhoh) | 33: + .long SYM(_uhoh) | 34: + .long SYM(_uhoh) | 35: + .long SYM(_uhoh) | 36: + .long SYM(_uhoh) | 37: + .long SYM(_uhoh) | 38: + .long SYM(_uhoh) | 39: + .long SYM(_uhoh) | 40: + .long SYM(_uhoh) | 41: + .long SYM(_uhoh) | 42: + .long SYM(_uhoh) | 43: + .long SYM(_uhoh) | 44: + .long SYM(_uhoh) | 45: + .long SYM(_uhoh) | 46: + .long SYM(_uhoh) | 47: + .long SYM(_uhoh) | 48: Reserved for coprocessor + .long SYM(_uhoh) | 49: + .long SYM(_uhoh) | 50: + .long SYM(_uhoh) | 51: + .long SYM(_uhoh) | 52: + .long SYM(_uhoh) | 53: + .long SYM(_uhoh) | 54: + .long SYM(_uhoh) | 55: + .long SYM(_uhoh) | 56: + .long SYM(_uhoh) | 57: + .long SYM(_uhoh) | 58: + .long SYM(_uhoh) | 59: Unassigned, reserved + .long SYM(_uhoh) | 60: + .long SYM(_uhoh) | 61: + .long SYM(_uhoh) | 62: + .long SYM(_uhoh) | 63: + .long SYM(_uhoh) | 64: User defined vectors (192) + .long SYM(_uhoh) | 65: + .long SYM(_uhoh) | 66: + .long SYM(_uhoh) | 67: + .long SYM(_uhoh) | 68: + .long SYM(_uhoh) | 69: + .long SYM(_uhoh) | 70: + .long SYM(_uhoh) | 71: + .long SYM(_uhoh) | 72: + .long SYM(_uhoh) | 73: + .long SYM(_uhoh) | 74: + .long SYM(_uhoh) | 75: + .long SYM(_uhoh) | 76: + .long SYM(_uhoh) | 77: + .long SYM(_uhoh) | 78: + .long SYM(_uhoh) | 79: + .long SYM(_uhoh) | 80: + .long SYM(_uhoh) | 81: + .long SYM(_uhoh) | 82: + .long SYM(_uhoh) | 83: + .long SYM(_uhoh) | 84: + .long SYM(_uhoh) | 85: + .long SYM(_uhoh) | 86: + .long SYM(_uhoh) | 87: + .long SYM(_uhoh) | 88: + .long SYM(_uhoh) | 89: + .long SYM(_uhoh) | 90: + .long SYM(_uhoh) | 91: + .long SYM(_uhoh) | 92: + .long SYM(_uhoh) | 93: + .long SYM(_uhoh) | 94: + .long SYM(_uhoh) | 95: + .long SYM(_uhoh) | 96: + .long SYM(_uhoh) | 97: + .long SYM(_uhoh) | 98: + .long SYM(_uhoh) | 99: + .long SYM(_uhoh) | 100: + .long SYM(_uhoh) | 101: + .long SYM(_uhoh) | 102: + .long SYM(_uhoh) | 103: + .long SYM(_uhoh) | 104: + .long SYM(_uhoh) | 105: + .long SYM(_uhoh) | 106: + .long SYM(_uhoh) | 107: + .long SYM(_uhoh) | 108: + .long SYM(_uhoh) | 109: + .long SYM(_uhoh) | 110: + .long SYM(_uhoh) | 111: + .long SYM(_uhoh) | 112: + .long SYM(_uhoh) | 113: + .long SYM(_uhoh) | 114: + .long SYM(_uhoh) | 115: + .long SYM(_uhoh) | 116: + .long SYM(_uhoh) | 117: + .long SYM(_uhoh) | 118: + .long SYM(_uhoh) | 119: + .long SYM(_uhoh) | 120: + .long SYM(_uhoh) | 121: + .long SYM(_uhoh) | 122: + .long SYM(_uhoh) | 123: + .long SYM(_uhoh) | 124: + .long SYM(_uhoh) | 125: + .long SYM(_uhoh) | 126: + .long SYM(_uhoh) | 127: + .long SYM(_uhoh) | 128: + .long SYM(_uhoh) | 129: + .long SYM(_uhoh) | 130: + .long SYM(_uhoh) | 131: + .long SYM(_uhoh) | 132: + .long SYM(_uhoh) | 133: + .long SYM(_uhoh) | 134: + .long SYM(_uhoh) | 135: + .long SYM(_uhoh) | 136: + .long SYM(_uhoh) | 137: + .long SYM(_uhoh) | 138: + .long SYM(_uhoh) | 139: + .long SYM(_uhoh) | 140: + .long SYM(_uhoh) | 141: + .long SYM(_uhoh) | 142: + .long SYM(_uhoh) | 143: + .long SYM(_uhoh) | 144: + .long SYM(_uhoh) | 145: + .long SYM(_uhoh) | 146: + .long SYM(_uhoh) | 147: + .long SYM(_uhoh) | 148: + .long SYM(_uhoh) | 149: + .long SYM(_uhoh) | 150: + .long SYM(_uhoh) | 151: + .long SYM(_uhoh) | 152: + .long SYM(_uhoh) | 153: + .long SYM(_uhoh) | 154: + .long SYM(_uhoh) | 155: + .long SYM(_uhoh) | 156: + .long SYM(_uhoh) | 157: + .long SYM(_uhoh) | 158: + .long SYM(_uhoh) | 159: + .long SYM(_uhoh) | 160: + .long SYM(_uhoh) | 161: + .long SYM(_uhoh) | 162: + .long SYM(_uhoh) | 163: + .long SYM(_uhoh) | 164: + .long SYM(_uhoh) | 165: + .long SYM(_uhoh) | 166: + .long SYM(_uhoh) | 167: + .long SYM(_uhoh) | 168: + .long SYM(_uhoh) | 169: + .long SYM(_uhoh) | 170: + .long SYM(_uhoh) | 171: + .long SYM(_uhoh) | 172: + .long SYM(_uhoh) | 173: + .long SYM(_uhoh) | 174: + .long SYM(_uhoh) | 175: + .long SYM(_uhoh) | 176: + .long SYM(_uhoh) | 177: + .long SYM(_uhoh) | 178: + .long SYM(_uhoh) | 179: + .long SYM(_uhoh) | 180: + .long SYM(_uhoh) | 181: + .long SYM(_uhoh) | 182: + .long SYM(_uhoh) | 183: + .long SYM(_uhoh) | 184: + .long SYM(_uhoh) | 185: + .long SYM(_uhoh) | 186: + .long SYM(_uhoh) | 187: + .long SYM(_uhoh) | 188: + .long SYM(_uhoh) | 189: + .long SYM(_uhoh) | 190: + .long SYM(_uhoh) | 191: + .long SYM(_uhoh) | 192: + .long SYM(_uhoh) | 193: + .long SYM(_uhoh) | 194: + .long SYM(_uhoh) | 195: + .long SYM(_uhoh) | 196: + .long SYM(_uhoh) | 197: + .long SYM(_uhoh) | 198: + .long SYM(_uhoh) | 199: + .long SYM(_uhoh) | 200: + .long SYM(_uhoh) | 201: + .long SYM(_uhoh) | 202: + .long SYM(_uhoh) | 203: + .long SYM(_uhoh) | 204: + .long SYM(_uhoh) | 205: + .long SYM(_uhoh) | 206: + .long SYM(_uhoh) | 207: + .long SYM(_uhoh) | 208: + .long SYM(_uhoh) | 209: + .long SYM(_uhoh) | 210: + .long SYM(_uhoh) | 211: + .long SYM(_uhoh) | 212: + .long SYM(_uhoh) | 213: + .long SYM(_uhoh) | 214: + .long SYM(_uhoh) | 215: + .long SYM(_uhoh) | 216: + .long SYM(_uhoh) | 217: + .long SYM(_uhoh) | 218: + .long SYM(_uhoh) | 219: + .long SYM(_uhoh) | 220: + .long SYM(_uhoh) | 221: + .long SYM(_uhoh) | 222: + .long SYM(_uhoh) | 223: + .long SYM(_uhoh) | 224: + .long SYM(_uhoh) | 225: + .long SYM(_uhoh) | 226: + .long SYM(_uhoh) | 227: + .long SYM(_uhoh) | 228: + .long SYM(_uhoh) | 229: + .long SYM(_uhoh) | 230: + .long SYM(_uhoh) | 231: + .long SYM(_uhoh) | 232: + .long SYM(_uhoh) | 233: + .long SYM(_uhoh) | 234: + .long SYM(_uhoh) | 235: + .long SYM(_uhoh) | 236: + .long SYM(_uhoh) | 237: + .long SYM(_uhoh) | 238: + .long SYM(_uhoh) | 239: + .long SYM(_uhoh) | 240: + .long SYM(_uhoh) | 241: + .long SYM(_uhoh) | 242: + .long SYM(_uhoh) | 243: + .long SYM(_uhoh) | 244: + .long SYM(_uhoh) | 245: + .long SYM(_uhoh) | 246: + .long SYM(_uhoh) | 247: + .long SYM(_uhoh) | 248: + .long SYM(_uhoh) | 249: + .long SYM(_uhoh) | 250: + .long SYM(_uhoh) | 251: + .long SYM(_uhoh) | 252: + .long SYM(_uhoh) | 253: + .long SYM(_uhoh) | 254: + .long SYM(_uhoh) | 255: + +/* + * Default trap handler + * With an oscilloscope you can see AS* stop + */ + PUBLIC (_uhoh) +SYM(_uhoh): nop | Leave spot for breakpoint + stop #0x2700 | Stop with interrupts disabled + bra.s SYM(_uhoh) | Stuck forever + +/* + * Log, but otherwise ignore, spurious interrupts + */ + PUBLIC (_spuriousInterrupt) +SYM(_spuriousInterrupt): + addql #1,SYM(_M68kSpuriousInterruptCount) + rte + +/* + * Place the low-order 3 octets of the board's ethernet address at + * a `well-known' fixed location relative to the startup location. + */ + .align 2 + .word 0 | Padding +ethernet_address_buffer: + .word 0x08F3 | Default address + .word 0xDEAD + .word 0xCAFE + +/* + * Initial PC + */ +.globl start +start: + /* + * Step 2: Stay in Supervisor Mode + */ +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) + oriw #0x3000,sr | Switch to Master Stack Pointer + lea SYM(m360)+1024-64,a7 | Put stack in dual-port ram + | a little below the interrupt stack +#endif + + /* + * Step 3: Write the VBR + */ + lea Entry,a0 | Get base of vector table + movec a0,vbr | Set up the VBR + + /* + * Step 4: Write the MBAR + */ + movec dfc,d1 | Save destination register + moveq #7,d0 | CPU-space funcction code + movec d0,dfc | Set destination function code register + movel #SYM(m360)+0x101,d0 | MBAR value (mask CPU space accesses) + movesl d0,0x3FF00 | Set MBAR + movec d1,dfc | Restore destination register + + /* + * Step 5: Verify a dual-port RAM location + */ + lea SYM(m360),a0 | Point a0 to first DPRAM location + moveb #0x33,d0 | Set the test value + moveb d0,a0@ | Set the memory location + cmpb a0@,d0 | Does it read back? + bne SYM(_uhoh) | If not, bad news! + notb d0 | Flip bits + moveb d0,a0@ | Set the memory location + cmpb a0@,d0 | Does it read back? + bne SYM(_uhoh) | If not, bad news! + + /* + * Remaining steps are handled by C code + */ + jmp SYM(_Init68360) | Start C code (which never returns) + +/* + * Copy DATA segment, clear BSS segment, set up real stack, + * initialize heap, start C program. + * Assume that DATA and BSS sizes are multiples of 4. + */ + PUBLIC (_CopyDataClearBSSAndStart) +SYM(_CopyDataClearBSSAndStart): + lea copy_start,a0 | Get start of DATA in RAM + lea SYM(etext),a2 | Get start of DATA in ROM + cmpl a0,a2 | Are they the same? + beq.s NOCOPY | Yes, no copy necessary + lea copy_end,a1 | Get end of DATA in RAM + bra.s COPYLOOPTEST | Branch into copy loop +COPYLOOP: + movel a2@+,a0@+ | Copy word from ROM to RAM +COPYLOOPTEST: + cmpl a1,a0 | Done? + bcs.s COPYLOOP | No, skip +NOCOPY: + + lea clear_start,a0 | Get start of BSS + lea clear_end,a1 | Get end of BSS + clrl d0 | Value to set + bra.s ZEROLOOPTEST | Branch into clear loop +ZEROLOOP: + movel d0,a0@+ | Clear a word +ZEROLOOPTEST: + cmpl a1,a0 | Done? + bcs.s ZEROLOOP | No, skip + + movel #stack_init,a7 | set master stack pointer + movel d0,a7@- | environp + movel d0,a7@- | argv + movel d0,a7@- | argc + jsr SYM(boot_card) | Call C main + + PUBLIC (_mainDone) +SYM(_mainDone): + nop | Leave spot for breakpoint + movew #1,a7 | Force a double bus error + movel d0,a7@- | This should cause a RESET + stop #0x2700 | Stop with interrupts disabled + bra.s SYM(_mainDone) | Stuck forever + + .align 2 + PUBLIC (_HeapSize) +SYM (_HeapSize): + .long HeapSize + PUBLIC (_StackSize) +SYM (_StackSize): + .long StackSize +END_CODE + +BEGIN_DATA_DCL + .align 2 + PUBLIC (environ) +SYM (environ): + .long 0 + PUBLIC (_M68kSpuriousInterruptCount) +SYM (_M68kSpuriousInterruptCount): + .long 0 +END_DATA_DCL + +END + diff --git a/c/src/lib/libbsp/m68k/gen68360/start360/start360.s b/c/src/lib/libbsp/m68k/gen68360/start360/start360.s deleted file mode 100644 index 2c979e294f..0000000000 --- a/c/src/lib/libbsp/m68k/gen68360/start360/start360.s +++ /dev/null @@ -1,432 +0,0 @@ -/* - * - * This file contains the entry point for the application. - * The name of this entry point is compiler dependent. - * It jumps to the BSP which is responsible for performing - * all initialization. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may in - * the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * Based on the `gen68302' board support package, and covered by the - * original distribution terms. - * - * W. Eric Norum - * Saskatchewan Accelerator Laboratory - * University of Saskatchewan - * Saskatoon, Saskatchewan, CANADA - * eric@skatter.usask.ca - * - * $Id$ - */ - -#include "asm.h" - -BEGIN_CODE - /* - * Step 1: Decide on Reset Stack Pointer and Initial Program Counter - */ -Entry: - .long SYM(m360)+1024 | 0: Initial SSP - .long start | 1: Initial PC - .long SYM(_uhoh) | 2: Bus error - .long SYM(_uhoh) | 3: Address error - .long SYM(_uhoh) | 4: Illegal instruction - .long SYM(_uhoh) | 5: Zero division - .long SYM(_uhoh) | 6: CHK, CHK2 instruction - .long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions - .long SYM(_uhoh) | 8: Privilege violation - .long SYM(_uhoh) | 9: Trace - .long SYM(_uhoh) | 10: Line 1010 emulator - .long SYM(_uhoh) | 11: Line 1111 emulator - .long SYM(_uhoh) | 12: Hardware breakpoint - .long SYM(_uhoh) | 13: Reserved for coprocessor violation - .long SYM(_uhoh) | 14: Format error - .long SYM(_uhoh) | 15: Uninitialized interrupt - .long SYM(_uhoh) | 16: Unassigned, reserved - .long SYM(_uhoh) | 17: - .long SYM(_uhoh) | 18: - .long SYM(_uhoh) | 19: - .long SYM(_uhoh) | 20: - .long SYM(_uhoh) | 21: - .long SYM(_uhoh) | 22: - .long SYM(_uhoh) | 23: - .long SYM(_spuriousInterrupt) | 24: Spurious interrupt - .long SYM(_uhoh) | 25: Level 1 interrupt autovector - .long SYM(_uhoh) | 26: Level 2 interrupt autovector - .long SYM(_uhoh) | 27: Level 3 interrupt autovector - .long SYM(_uhoh) | 28: Level 4 interrupt autovector - .long SYM(_uhoh) | 29: Level 5 interrupt autovector - .long SYM(_uhoh) | 30: Level 6 interrupt autovector - .long SYM(_uhoh) | 31: Level 7 interrupt autovector - .long SYM(_uhoh) | 32: Trap instruction (0-15) - .long SYM(_uhoh) | 33: - .long SYM(_uhoh) | 34: - .long SYM(_uhoh) | 35: - .long SYM(_uhoh) | 36: - .long SYM(_uhoh) | 37: - .long SYM(_uhoh) | 38: - .long SYM(_uhoh) | 39: - .long SYM(_uhoh) | 40: - .long SYM(_uhoh) | 41: - .long SYM(_uhoh) | 42: - .long SYM(_uhoh) | 43: - .long SYM(_uhoh) | 44: - .long SYM(_uhoh) | 45: - .long SYM(_uhoh) | 46: - .long SYM(_uhoh) | 47: - .long SYM(_uhoh) | 48: Reserved for coprocessor - .long SYM(_uhoh) | 49: - .long SYM(_uhoh) | 50: - .long SYM(_uhoh) | 51: - .long SYM(_uhoh) | 52: - .long SYM(_uhoh) | 53: - .long SYM(_uhoh) | 54: - .long SYM(_uhoh) | 55: - .long SYM(_uhoh) | 56: - .long SYM(_uhoh) | 57: - .long SYM(_uhoh) | 58: - .long SYM(_uhoh) | 59: Unassigned, reserved - .long SYM(_uhoh) | 60: - .long SYM(_uhoh) | 61: - .long SYM(_uhoh) | 62: - .long SYM(_uhoh) | 63: - .long SYM(_uhoh) | 64: User defined vectors (192) - .long SYM(_uhoh) | 65: - .long SYM(_uhoh) | 66: - .long SYM(_uhoh) | 67: - .long SYM(_uhoh) | 68: - .long SYM(_uhoh) | 69: - .long SYM(_uhoh) | 70: - .long SYM(_uhoh) | 71: - .long SYM(_uhoh) | 72: - .long SYM(_uhoh) | 73: - .long SYM(_uhoh) | 74: - .long SYM(_uhoh) | 75: - .long SYM(_uhoh) | 76: - .long SYM(_uhoh) | 77: - .long SYM(_uhoh) | 78: - .long SYM(_uhoh) | 79: - .long SYM(_uhoh) | 80: - .long SYM(_uhoh) | 81: - .long SYM(_uhoh) | 82: - .long SYM(_uhoh) | 83: - .long SYM(_uhoh) | 84: - .long SYM(_uhoh) | 85: - .long SYM(_uhoh) | 86: - .long SYM(_uhoh) | 87: - .long SYM(_uhoh) | 88: - .long SYM(_uhoh) | 89: - .long SYM(_uhoh) | 90: - .long SYM(_uhoh) | 91: - .long SYM(_uhoh) | 92: - .long SYM(_uhoh) | 93: - .long SYM(_uhoh) | 94: - .long SYM(_uhoh) | 95: - .long SYM(_uhoh) | 96: - .long SYM(_uhoh) | 97: - .long SYM(_uhoh) | 98: - .long SYM(_uhoh) | 99: - .long SYM(_uhoh) | 100: - .long SYM(_uhoh) | 101: - .long SYM(_uhoh) | 102: - .long SYM(_uhoh) | 103: - .long SYM(_uhoh) | 104: - .long SYM(_uhoh) | 105: - .long SYM(_uhoh) | 106: - .long SYM(_uhoh) | 107: - .long SYM(_uhoh) | 108: - .long SYM(_uhoh) | 109: - .long SYM(_uhoh) | 110: - .long SYM(_uhoh) | 111: - .long SYM(_uhoh) | 112: - .long SYM(_uhoh) | 113: - .long SYM(_uhoh) | 114: - .long SYM(_uhoh) | 115: - .long SYM(_uhoh) | 116: - .long SYM(_uhoh) | 117: - .long SYM(_uhoh) | 118: - .long SYM(_uhoh) | 119: - .long SYM(_uhoh) | 120: - .long SYM(_uhoh) | 121: - .long SYM(_uhoh) | 122: - .long SYM(_uhoh) | 123: - .long SYM(_uhoh) | 124: - .long SYM(_uhoh) | 125: - .long SYM(_uhoh) | 126: - .long SYM(_uhoh) | 127: - .long SYM(_uhoh) | 128: - .long SYM(_uhoh) | 129: - .long SYM(_uhoh) | 130: - .long SYM(_uhoh) | 131: - .long SYM(_uhoh) | 132: - .long SYM(_uhoh) | 133: - .long SYM(_uhoh) | 134: - .long SYM(_uhoh) | 135: - .long SYM(_uhoh) | 136: - .long SYM(_uhoh) | 137: - .long SYM(_uhoh) | 138: - .long SYM(_uhoh) | 139: - .long SYM(_uhoh) | 140: - .long SYM(_uhoh) | 141: - .long SYM(_uhoh) | 142: - .long SYM(_uhoh) | 143: - .long SYM(_uhoh) | 144: - .long SYM(_uhoh) | 145: - .long SYM(_uhoh) | 146: - .long SYM(_uhoh) | 147: - .long SYM(_uhoh) | 148: - .long SYM(_uhoh) | 149: - .long SYM(_uhoh) | 150: - .long SYM(_uhoh) | 151: - .long SYM(_uhoh) | 152: - .long SYM(_uhoh) | 153: - .long SYM(_uhoh) | 154: - .long SYM(_uhoh) | 155: - .long SYM(_uhoh) | 156: - .long SYM(_uhoh) | 157: - .long SYM(_uhoh) | 158: - .long SYM(_uhoh) | 159: - .long SYM(_uhoh) | 160: - .long SYM(_uhoh) | 161: - .long SYM(_uhoh) | 162: - .long SYM(_uhoh) | 163: - .long SYM(_uhoh) | 164: - .long SYM(_uhoh) | 165: - .long SYM(_uhoh) | 166: - .long SYM(_uhoh) | 167: - .long SYM(_uhoh) | 168: - .long SYM(_uhoh) | 169: - .long SYM(_uhoh) | 170: - .long SYM(_uhoh) | 171: - .long SYM(_uhoh) | 172: - .long SYM(_uhoh) | 173: - .long SYM(_uhoh) | 174: - .long SYM(_uhoh) | 175: - .long SYM(_uhoh) | 176: - .long SYM(_uhoh) | 177: - .long SYM(_uhoh) | 178: - .long SYM(_uhoh) | 179: - .long SYM(_uhoh) | 180: - .long SYM(_uhoh) | 181: - .long SYM(_uhoh) | 182: - .long SYM(_uhoh) | 183: - .long SYM(_uhoh) | 184: - .long SYM(_uhoh) | 185: - .long SYM(_uhoh) | 186: - .long SYM(_uhoh) | 187: - .long SYM(_uhoh) | 188: - .long SYM(_uhoh) | 189: - .long SYM(_uhoh) | 190: - .long SYM(_uhoh) | 191: - .long SYM(_uhoh) | 192: - .long SYM(_uhoh) | 193: - .long SYM(_uhoh) | 194: - .long SYM(_uhoh) | 195: - .long SYM(_uhoh) | 196: - .long SYM(_uhoh) | 197: - .long SYM(_uhoh) | 198: - .long SYM(_uhoh) | 199: - .long SYM(_uhoh) | 200: - .long SYM(_uhoh) | 201: - .long SYM(_uhoh) | 202: - .long SYM(_uhoh) | 203: - .long SYM(_uhoh) | 204: - .long SYM(_uhoh) | 205: - .long SYM(_uhoh) | 206: - .long SYM(_uhoh) | 207: - .long SYM(_uhoh) | 208: - .long SYM(_uhoh) | 209: - .long SYM(_uhoh) | 210: - .long SYM(_uhoh) | 211: - .long SYM(_uhoh) | 212: - .long SYM(_uhoh) | 213: - .long SYM(_uhoh) | 214: - .long SYM(_uhoh) | 215: - .long SYM(_uhoh) | 216: - .long SYM(_uhoh) | 217: - .long SYM(_uhoh) | 218: - .long SYM(_uhoh) | 219: - .long SYM(_uhoh) | 220: - .long SYM(_uhoh) | 221: - .long SYM(_uhoh) | 222: - .long SYM(_uhoh) | 223: - .long SYM(_uhoh) | 224: - .long SYM(_uhoh) | 225: - .long SYM(_uhoh) | 226: - .long SYM(_uhoh) | 227: - .long SYM(_uhoh) | 228: - .long SYM(_uhoh) | 229: - .long SYM(_uhoh) | 230: - .long SYM(_uhoh) | 231: - .long SYM(_uhoh) | 232: - .long SYM(_uhoh) | 233: - .long SYM(_uhoh) | 234: - .long SYM(_uhoh) | 235: - .long SYM(_uhoh) | 236: - .long SYM(_uhoh) | 237: - .long SYM(_uhoh) | 238: - .long SYM(_uhoh) | 239: - .long SYM(_uhoh) | 240: - .long SYM(_uhoh) | 241: - .long SYM(_uhoh) | 242: - .long SYM(_uhoh) | 243: - .long SYM(_uhoh) | 244: - .long SYM(_uhoh) | 245: - .long SYM(_uhoh) | 246: - .long SYM(_uhoh) | 247: - .long SYM(_uhoh) | 248: - .long SYM(_uhoh) | 249: - .long SYM(_uhoh) | 250: - .long SYM(_uhoh) | 251: - .long SYM(_uhoh) | 252: - .long SYM(_uhoh) | 253: - .long SYM(_uhoh) | 254: - .long SYM(_uhoh) | 255: - -/* - * Default trap handler - * With an oscilloscope you can see AS* stop - */ - PUBLIC (_uhoh) -SYM(_uhoh): nop | Leave spot for breakpoint - stop #0x2700 | Stop with interrupts disabled - bra.s SYM(_uhoh) | Stuck forever - -/* - * Log, but otherwise ignore, spurious interrupts - */ - PUBLIC (_spuriousInterrupt) -SYM(_spuriousInterrupt): - addql #1,SYM(_M68kSpuriousInterruptCount) - rte - -/* - * Place the low-order 3 octets of the board's ethernet address at - * a `well-known' fixed location relative to the startup location. - */ - .align 2 - .word 0 | Padding -ethernet_address_buffer: - .word 0x08F3 | Default address - .word 0xDEAD - .word 0xCAFE - -/* - * Initial PC - */ -.globl start -start: - /* - * Step 2: Stay in Supervisor Mode - */ -#if ( M68K_HAS_SEPARATE_STACKS == 1 ) - oriw #0x3000,sr | Switch to Master Stack Pointer - lea SYM(m360)+1024-64,a7 | Put stack in dual-port ram - | a little below the interrupt stack -#endif - - /* - * Step 3: Write the VBR - */ - lea Entry,a0 | Get base of vector table - movec a0,vbr | Set up the VBR - - /* - * Step 4: Write the MBAR - */ - movec dfc,d1 | Save destination register - moveq #7,d0 | CPU-space funcction code - movec d0,dfc | Set destination function code register - movel #SYM(m360)+0x101,d0 | MBAR value (mask CPU space accesses) - movesl d0,0x3FF00 | Set MBAR - movec d1,dfc | Restore destination register - - /* - * Step 5: Verify a dual-port RAM location - */ - lea SYM(m360),a0 | Point a0 to first DPRAM location - moveb #0x33,d0 | Set the test value - moveb d0,a0@ | Set the memory location - cmpb a0@,d0 | Does it read back? - bne SYM(_uhoh) | If not, bad news! - notb d0 | Flip bits - moveb d0,a0@ | Set the memory location - cmpb a0@,d0 | Does it read back? - bne SYM(_uhoh) | If not, bad news! - - /* - * Remaining steps are handled by C code - */ - jmp SYM(_Init68360) | Start C code (which never returns) - -/* - * Copy DATA segment, clear BSS segment, set up real stack, - * initialize heap, start C program. - * Assume that DATA and BSS sizes are multiples of 4. - */ - PUBLIC (_CopyDataClearBSSAndStart) -SYM(_CopyDataClearBSSAndStart): - lea copy_start,a0 | Get start of DATA in RAM - lea SYM(etext),a2 | Get start of DATA in ROM - cmpl a0,a2 | Are they the same? - beq.s NOCOPY | Yes, no copy necessary - lea copy_end,a1 | Get end of DATA in RAM - bra.s COPYLOOPTEST | Branch into copy loop -COPYLOOP: - movel a2@+,a0@+ | Copy word from ROM to RAM -COPYLOOPTEST: - cmpl a1,a0 | Done? - bcs.s COPYLOOP | No, skip -NOCOPY: - - lea clear_start,a0 | Get start of BSS - lea clear_end,a1 | Get end of BSS - clrl d0 | Value to set - bra.s ZEROLOOPTEST | Branch into clear loop -ZEROLOOP: - movel d0,a0@+ | Clear a word -ZEROLOOPTEST: - cmpl a1,a0 | Done? - bcs.s ZEROLOOP | No, skip - - movel #stack_init,a7 | set master stack pointer - movel d0,a7@- | environp - movel d0,a7@- | argv - movel d0,a7@- | argc - jsr SYM(boot_card) | Call C main - - PUBLIC (_mainDone) -SYM(_mainDone): - nop | Leave spot for breakpoint - movew #1,a7 | Force a double bus error - movel d0,a7@- | This should cause a RESET - stop #0x2700 | Stop with interrupts disabled - bra.s SYM(_mainDone) | Stuck forever - - .align 2 - PUBLIC (_HeapSize) -SYM (_HeapSize): - .long HeapSize - PUBLIC (_StackSize) -SYM (_StackSize): - .long StackSize -END_CODE - -BEGIN_DATA_DCL - .align 2 - PUBLIC (environ) -SYM (environ): - .long 0 - PUBLIC (_M68kSpuriousInterruptCount) -SYM (_M68kSpuriousInterruptCount): - .long 0 -END_DATA_DCL - -END - diff --git a/c/src/lib/libbsp/m68k/idp/timer/Makefile.in b/c/src/lib/libbsp/m68k/idp/timer/Makefile.in index 0c8ec3ccaa..4fabb39e55 100644 --- a/c/src/lib/libbsp/m68k/idp/timer/Makefile.in +++ b/c/src/lib/libbsp/m68k/idp/timer/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=timerisr -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/m68k/idp/timer/timerisr.S b/c/src/lib/libbsp/m68k/idp/timer/timerisr.S new file mode 100644 index 0000000000..74461f3714 --- /dev/null +++ b/c/src/lib/libbsp/m68k/idp/timer/timerisr.S @@ -0,0 +1,38 @@ +/* timer_isr() + * + * This routine provides the ISR for the MC68230 timer on the Motorola + * IDP board. The timer is set up to generate an interrupt at maximum + * intervals. + * + * Code modified by Doug McBride, Colorado Space Grant College + * countdown should be loaded automatically + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include "asm.h" + +BEGIN_CODE + +.set TSR, 0x00c0106B | base address of PIT register "TSR" + + PUBLIC (timerisr) +SYM (timerisr): + movb #1,TSR | acknowledge interrupt + addql #1, SYM (Ttimer_val) | increment timer value + rte + +END_CODE +END diff --git a/c/src/lib/libbsp/m68k/idp/timer/timerisr.s b/c/src/lib/libbsp/m68k/idp/timer/timerisr.s deleted file mode 100644 index 74461f3714..0000000000 --- a/c/src/lib/libbsp/m68k/idp/timer/timerisr.s +++ /dev/null @@ -1,38 +0,0 @@ -/* timer_isr() - * - * This routine provides the ISR for the MC68230 timer on the Motorola - * IDP board. The timer is set up to generate an interrupt at maximum - * intervals. - * - * Code modified by Doug McBride, Colorado Space Grant College - * countdown should be loaded automatically - * - * Input parameters: NONE - * - * Output parameters: NONE - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include "asm.h" - -BEGIN_CODE - -.set TSR, 0x00c0106B | base address of PIT register "TSR" - - PUBLIC (timerisr) -SYM (timerisr): - movb #1,TSR | acknowledge interrupt - addql #1, SYM (Ttimer_val) | increment timer value - rte - -END_CODE -END diff --git a/c/src/lib/libbsp/m68k/mvme136/timer/Makefile.in b/c/src/lib/libbsp/m68k/mvme136/timer/Makefile.in index 24809cbed8..21ca9675e7 100644 --- a/c/src/lib/libbsp/m68k/mvme136/timer/Makefile.in +++ b/c/src/lib/libbsp/m68k/mvme136/timer/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=timerisr -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/m68k/mvme136/timer/timerisr.S b/c/src/lib/libbsp/m68k/mvme136/timer/timerisr.S new file mode 100644 index 0000000000..63ee63bd8e --- /dev/null +++ b/c/src/lib/libbsp/m68k/mvme136/timer/timerisr.S @@ -0,0 +1,39 @@ +/* timer_isr() + * + * This routine provides the ISR for the Z8036 timer on the MVME136 + * board. The timer is set up to generate an interrupt at maximum + * intervals. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include "asm.h" + +BEGIN_CODE + +.set CT1_CMD_STATUS, 0xfffb000a | port A +.set RELOAD, 0x24 | clr IP & IUS,allow countdown + + PUBLIC (timerisr) +SYM (timerisr): + movl a0,a7@- | save a0 + movl #CT1_CMD_STATUS,a0 | a0 = addr of cmd status reg + movb #RELOAD,a0@ | reload countdown + addql #1, SYM (Ttimer_val) | increment timer value + movl a7@+,a0 | save a0 + rte + +END_CODE +END diff --git a/c/src/lib/libbsp/m68k/mvme136/timer/timerisr.s b/c/src/lib/libbsp/m68k/mvme136/timer/timerisr.s deleted file mode 100644 index 63ee63bd8e..0000000000 --- a/c/src/lib/libbsp/m68k/mvme136/timer/timerisr.s +++ /dev/null @@ -1,39 +0,0 @@ -/* timer_isr() - * - * This routine provides the ISR for the Z8036 timer on the MVME136 - * board. The timer is set up to generate an interrupt at maximum - * intervals. - * - * Input parameters: NONE - * - * Output parameters: NONE - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include "asm.h" - -BEGIN_CODE - -.set CT1_CMD_STATUS, 0xfffb000a | port A -.set RELOAD, 0x24 | clr IP & IUS,allow countdown - - PUBLIC (timerisr) -SYM (timerisr): - movl a0,a7@- | save a0 - movl #CT1_CMD_STATUS,a0 | a0 = addr of cmd status reg - movb #RELOAD,a0@ | reload countdown - addql #1, SYM (Ttimer_val) | increment timer value - movl a7@+,a0 | save a0 - rte - -END_CODE -END diff --git a/c/src/lib/libbsp/m68k/mvme136/wrapup/Makefile.in b/c/src/lib/libbsp/m68k/mvme136/wrapup/Makefile.in index 4dc4ea5208..aecc98b975 100644 --- a/c/src/lib/libbsp/m68k/mvme136/wrapup/Makefile.in +++ b/c/src/lib/libbsp/m68k/mvme136/wrapup/Makefile.in @@ -8,17 +8,22 @@ VPATH = @srcdir@ RTEMS_ROOT = @top_srcdir@ PROJECT_ROOT = @PROJECT_ROOT@ -BSP_PIECES=startup clock console shmsupp timer -GENERIC_PIECES=shmdr +BSP_PIECES=startup clock console timer +GENERIC_PIECES= + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/lib.cfg + +ifeq ($(HAS_MP),yes) +GENERIC_PIECES += shmdr +BSP_PIECES += shmsupp +endif # bummer; have to use $foreach since % pattern subst rules only replace 1x OBJS=$(foreach piece, $(BSP_PIECES), ../$(piece)/$(ARCH)/$(piece).rel) \ $(foreach piece, $(GENERIC_PIECES), ../../../$(piece)/$(ARCH)/$(piece).rel) LIB=$(ARCH)/libbsp.a -include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg -include $(RTEMS_ROOT)/make/lib.cfg - # # (OPTIONAL) Add local stuff here using += # diff --git a/c/src/lib/libbsp/m68k/mvme147/timer/Makefile.in b/c/src/lib/libbsp/m68k/mvme147/timer/Makefile.in index 24809cbed8..21ca9675e7 100644 --- a/c/src/lib/libbsp/m68k/mvme147/timer/Makefile.in +++ b/c/src/lib/libbsp/m68k/mvme147/timer/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=timerisr -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/m68k/mvme147/timer/timerisr.s b/c/src/lib/libbsp/m68k/mvme147/timer/timerisr.s deleted file mode 100644 index 7debd13849..0000000000 --- a/c/src/lib/libbsp/m68k/mvme147/timer/timerisr.s +++ /dev/null @@ -1,28 +0,0 @@ -/* timer_isr() - * - * This routine provides the ISR for the PCC timer on the MVME147 - * board. The timer is set up to generate an interrupt at maximum - * intervals. - * - * MVME147 port for TNI - Telecom Bretagne - * by Dominique LE CAMPION (Dominique.LECAMPION@enst-bretagne.fr) - * May 1996 - * - * $Id$ - */ - -#include "asm.h" - -BEGIN_CODE - -.set T1_CONTROL_REGISTER, 0xfffe1018 | timer 1 control register - - PUBLIC (timerisr) -SYM (timerisr): - orb #0x80, T1_CONTROL_REGISTER | clear T1 int status bit - addql #1, SYM (Ttimer_val) | increment timer value -end_timerisr: - rte - -END_CODE -END diff --git a/c/src/lib/libbsp/m68k/mvme147/wrapup/Makefile.in b/c/src/lib/libbsp/m68k/mvme147/wrapup/Makefile.in index 33d990d882..a42a827299 100644 --- a/c/src/lib/libbsp/m68k/mvme147/wrapup/Makefile.in +++ b/c/src/lib/libbsp/m68k/mvme147/wrapup/Makefile.in @@ -8,8 +8,8 @@ VPATH = @srcdir@ RTEMS_ROOT = @top_srcdir@ PROJECT_ROOT = @PROJECT_ROOT@ -BSP_PIECES=startup clock console timer # shmsupp -GENERIC_PIECES=# shmdr +BSP_PIECES=startup clock console timer +GENERIC_PIECES= # bummer; have to use $foreach since % pattern subst rules only replace 1x OBJS=$(foreach piece, $(BSP_PIECES), ../$(piece)/$(ARCH)/$(piece).rel) \ diff --git a/c/src/lib/libbsp/m68k/mvme147s/timer/Makefile.in b/c/src/lib/libbsp/m68k/mvme147s/timer/Makefile.in index c12e535ace..03902da08d 100644 --- a/c/src/lib/libbsp/m68k/mvme147s/timer/Makefile.in +++ b/c/src/lib/libbsp/m68k/mvme147s/timer/Makefile.in @@ -15,10 +15,10 @@ C_PIECES=timer C_FILES=$(C_PIECES:%=%.c) C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=timerisr -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) H_FILES= diff --git a/c/src/lib/libbsp/m68k/mvme147s/wrapup/Makefile.in b/c/src/lib/libbsp/m68k/mvme147s/wrapup/Makefile.in index 8c70b9398f..aecc98b975 100644 --- a/c/src/lib/libbsp/m68k/mvme147s/wrapup/Makefile.in +++ b/c/src/lib/libbsp/m68k/mvme147s/wrapup/Makefile.in @@ -8,17 +8,22 @@ VPATH = @srcdir@ RTEMS_ROOT = @top_srcdir@ PROJECT_ROOT = @PROJECT_ROOT@ -BSP_PIECES=startup clock console timer shmsupp -GENERIC_PIECES=shmdr +BSP_PIECES=startup clock console timer +GENERIC_PIECES= + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/lib.cfg + +ifeq ($(HAS_MP),yes) +GENERIC_PIECES += shmdr +BSP_PIECES += shmsupp +endif # bummer; have to use $foreach since % pattern subst rules only replace 1x OBJS=$(foreach piece, $(BSP_PIECES), ../$(piece)/$(ARCH)/$(piece).rel) \ $(foreach piece, $(GENERIC_PIECES), ../../../$(piece)/$(ARCH)/$(piece).rel) LIB=$(ARCH)/libbsp.a -include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg -include $(RTEMS_ROOT)/make/lib.cfg - # # (OPTIONAL) Add local stuff here using += # diff --git a/c/src/lib/libbsp/m68k/mvme162/timer/Makefile.in b/c/src/lib/libbsp/m68k/mvme162/timer/Makefile.in index 24809cbed8..21ca9675e7 100644 --- a/c/src/lib/libbsp/m68k/mvme162/timer/Makefile.in +++ b/c/src/lib/libbsp/m68k/mvme162/timer/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=timerisr -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/m68k/mvme162/timer/timerisr.S b/c/src/lib/libbsp/m68k/mvme162/timer/timerisr.S new file mode 100644 index 0000000000..9380fac0f0 --- /dev/null +++ b/c/src/lib/libbsp/m68k/mvme162/timer/timerisr.S @@ -0,0 +1,47 @@ +/* timer_isr() + * + * This routine provides the ISR for the Z8036 timer on the MVME136 + * board. The timer is set up to generate an interrupt at maximum + * intervals. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * Modifications of respective RTEMS file: COPYRIGHT (c) 1994. + * EISCAT Scientific Association. M.Savitski + * + * This material is a part of the MVME162 Board Support Package + * for the RTEMS executive. Its licensing policies are those of the + * RTEMS above. + * + * $Id$ + */ + +#include "asm.h" + +BEGIN_CODE + +.set INTR_CLEAR_REG, 0xfff40074 | interrupt clear register +.set RELOAD, 0x01000000 | clear tick 1 interrupt + + PUBLIC (Ttimer_val) + PUBLIC (timerisr) +SYM (timerisr): + move.l a0, -(a7) | save a0 + movea.l #INTR_CLEAR_REG, a0 | a0 = addr of cmd status reg + ori.l #RELOAD, (a0) | reload countdown + addq.l #1, SYM (Ttimer_val) | increment timer value + move.l (a7)+, a0 | restore a0 + rte + +END_CODE +END diff --git a/c/src/lib/libbsp/m68k/mvme162/timer/timerisr.s b/c/src/lib/libbsp/m68k/mvme162/timer/timerisr.s deleted file mode 100644 index 9380fac0f0..0000000000 --- a/c/src/lib/libbsp/m68k/mvme162/timer/timerisr.s +++ /dev/null @@ -1,47 +0,0 @@ -/* timer_isr() - * - * This routine provides the ISR for the Z8036 timer on the MVME136 - * board. The timer is set up to generate an interrupt at maximum - * intervals. - * - * Input parameters: NONE - * - * Output parameters: NONE - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * Modifications of respective RTEMS file: COPYRIGHT (c) 1994. - * EISCAT Scientific Association. M.Savitski - * - * This material is a part of the MVME162 Board Support Package - * for the RTEMS executive. Its licensing policies are those of the - * RTEMS above. - * - * $Id$ - */ - -#include "asm.h" - -BEGIN_CODE - -.set INTR_CLEAR_REG, 0xfff40074 | interrupt clear register -.set RELOAD, 0x01000000 | clear tick 1 interrupt - - PUBLIC (Ttimer_val) - PUBLIC (timerisr) -SYM (timerisr): - move.l a0, -(a7) | save a0 - movea.l #INTR_CLEAR_REG, a0 | a0 = addr of cmd status reg - ori.l #RELOAD, (a0) | reload countdown - addq.l #1, SYM (Ttimer_val) | increment timer value - move.l (a7)+, a0 | restore a0 - rte - -END_CODE -END diff --git a/c/src/lib/libbsp/m68k/ods68302/start/Makefile.in b/c/src/lib/libbsp/m68k/ods68302/start/Makefile.in index a6d3ba2c08..8344f4f8a9 100644 --- a/c/src/lib/libbsp/m68k/ods68302/start/Makefile.in +++ b/c/src/lib/libbsp/m68k/ods68302/start/Makefile.in @@ -24,10 +24,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=$(RESET_SRC) -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(S_O_FILES) $(C_O_FILES) diff --git a/c/src/lib/libbsp/m68k/ods68302/start302/Makefile.in b/c/src/lib/libbsp/m68k/ods68302/start302/Makefile.in index a6d3ba2c08..8344f4f8a9 100644 --- a/c/src/lib/libbsp/m68k/ods68302/start302/Makefile.in +++ b/c/src/lib/libbsp/m68k/ods68302/start302/Makefile.in @@ -24,10 +24,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=$(RESET_SRC) -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(S_O_FILES) $(C_O_FILES) diff --git a/c/src/lib/libbsp/m68k/ods68302/timer/Makefile.in b/c/src/lib/libbsp/m68k/ods68302/timer/Makefile.in index 24809cbed8..21ca9675e7 100644 --- a/c/src/lib/libbsp/m68k/ods68302/timer/Makefile.in +++ b/c/src/lib/libbsp/m68k/ods68302/timer/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=timerisr -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/m68k/ods68302/timer/timerisr.S b/c/src/lib/libbsp/m68k/ods68302/timer/timerisr.S new file mode 100644 index 0000000000..c804b9dfa6 --- /dev/null +++ b/c/src/lib/libbsp/m68k/ods68302/timer/timerisr.S @@ -0,0 +1,28 @@ +/* + * Handle 68302 TIMER2 interrupts. + * + * All code in this routine is pure overhead which can perturb the + * accuracy of RTEMS' timing test suite. + * + * See also: Read_timer() + * + * To reduce overhead this is best to be the "rawest" hardware interupt + * handler you can write. This should be the only interrupt which can + * occur during the measured time period. + * + * An external counter, Timer_interrupts, is incremented. + * + * $Id$ + */ + +#include "asm.h" + +BEGIN_CODE + PUBLIC(timerisr) +SYM(timerisr): + move.w #0x0040,SYM(m302)+2072 | clear interrupt in-service bit + move.b #3,SYM(m302)+2137 | clear timer interrupt event register + addq.l #1,SYM(Timer_interrupts) | increment timer value + rte +END_CODE +END diff --git a/c/src/lib/libbsp/m68k/ods68302/timer/timerisr.s b/c/src/lib/libbsp/m68k/ods68302/timer/timerisr.s deleted file mode 100644 index c804b9dfa6..0000000000 --- a/c/src/lib/libbsp/m68k/ods68302/timer/timerisr.s +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Handle 68302 TIMER2 interrupts. - * - * All code in this routine is pure overhead which can perturb the - * accuracy of RTEMS' timing test suite. - * - * See also: Read_timer() - * - * To reduce overhead this is best to be the "rawest" hardware interupt - * handler you can write. This should be the only interrupt which can - * occur during the measured time period. - * - * An external counter, Timer_interrupts, is incremented. - * - * $Id$ - */ - -#include "asm.h" - -BEGIN_CODE - PUBLIC(timerisr) -SYM(timerisr): - move.w #0x0040,SYM(m302)+2072 | clear interrupt in-service bit - move.b #3,SYM(m302)+2137 | clear timer interrupt event register - addq.l #1,SYM(Timer_interrupts) | increment timer value - rte -END_CODE -END diff --git a/c/src/lib/libbsp/m68k/shared/start.S b/c/src/lib/libbsp/m68k/shared/start.S new file mode 100644 index 0000000000..72849170d9 --- /dev/null +++ b/c/src/lib/libbsp/m68k/shared/start.S @@ -0,0 +1,153 @@ +/* entry.s + * + * This file contains the entry point for the application. + * The name of this entry point is compiler dependent. + * It jumps to the BSP which is responsible for performing + * all initialization. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include "asm.h" + +#if (M68K_COLDFIRE_ARCH == 0) /* All ColdFire BSPs must provide their own start vector */ + +BEGIN_CODE + | Default entry points for: + PUBLIC (start) | GNU + PUBLIC (M68Kvec) | Vector Table + +SYM (start): +SYM (M68Kvec): | standard location for vectors + nop | for linkers with problem + | location zero + jmp SYM (start_around) + + /* + * We can use the following space as our vector table + * if the CPU has a VBR or we can save vector table in it + * if the CPU does not. + */ + + .space 4088 | to avoid initial intr stack + | from 135BUG on MVME13? + | and start code at 0x4000 +SYM (vectors): + .space 1016 | reserve space for rest of vectors + +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) +SYM (lowintstack): + .space 4092 | reserve for interrupt stack +SYM (hiintstack): + .space 4 | end of interrupt stack +#endif + + PUBLIC (start_around) +SYM (start_around): + move.w sr, SYM (initial_sr) + oriw #0x3700,sr | SUPV MODE,INTERRUPTS OFF!!! +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) + movec isp,a0 + move.l a0, SYM (initial_isp) + movec usp,a0 + move.l a0, SYM (initial_usp) + movec msp,a0 + move.l a0, SYM (initial_msp) +#else + move.l a7, SYM (initial_msp) +#endif + + | + | zero out uninitialized data area + | +zerobss: + moveal # SYM (end),a0 | find end of .bss + moveal # SYM (bss_start),a1 | find beginning of .bss + movel #0,d0 + +loop: movel #0,a1@+ | to zero out uninitialized + cmpal a0,a1 + jlt loop | loop until _end reached + + movel # SYM (stack_init),d0 | d0 = stop of stack + andl #0xffffffc0,d0 | align it on 16 byte boundary + movw #0x3700,sr | SUPV MODE,INTERRUPTS OFF!!! + movel d0,a7 | set master stack pointer + movel d0,a6 | set base pointer + + /* + * RTEMS should maintain a separate interrupt stack on CPUs + * without one in hardware. This is currently not supported + * on versions of the m68k without a HW intr stack. + */ + +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) + lea SYM (hiintstack),a0 | a0 = high end of intr stack + movec a0,isp | set interrupt stack +#endif + movel #0,a7@- | push environp + movel #0,a7@- | push argv + movel #0,a7@- | push argc + + jsr SYM (boot_card) + addl #12,a7 + +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) + move.l SYM (initial_isp),a0 + movec a0,isp + move.l SYM (initial_usp),a0 + movec a0,usp + move.l SYM (initial_msp),a0 + movec a0,msp +#else + movea.l SYM (initial_msp),a7 +#endif + move.w SYM (initial_sr),sr + rts + +END_CODE + +BEGIN_DATA + + PUBLIC (start_frame) +SYM (start_frame): + .space 4,0 + +END_DATA + +BEGIN_BSS + + PUBLIC (environ) + .align 2 +SYM (environ): + .long 0 + + PUBLIC (initial_isp) +SYM (initial_isp): + .space 4 + + PUBLIC (initial_msp) +SYM (initial_msp): + .space 4 + + PUBLIC (initial_usp) +SYM (initial_usp): + .space 4 + + PUBLIC (initial_sr) +SYM (initial_sr): + .space 2 + +END_DATA +#endif +END + + diff --git a/c/src/lib/libbsp/mips64orion/p4000/start/Makefile.in b/c/src/lib/libbsp/mips64orion/p4000/start/Makefile.in index 046969120a..7aa139ca0b 100644 --- a/c/src/lib/libbsp/mips64orion/p4000/start/Makefile.in +++ b/c/src/lib/libbsp/mips64orion/p4000/start/Makefile.in @@ -15,10 +15,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=idt_csu S_FILES=$(S_PIECES:%=%.S) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/no_cpu/no_bsp/clock/Makefile.in b/c/src/lib/libbsp/no_cpu/no_bsp/clock/Makefile.in index 48b1c93ac7..c406942630 100644 --- a/c/src/lib/libbsp/no_cpu/no_bsp/clock/Makefile.in +++ b/c/src/lib/libbsp/no_cpu/no_bsp/clock/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES= -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/no_cpu/no_bsp/console/Makefile.in b/c/src/lib/libbsp/no_cpu/no_bsp/console/Makefile.in index b73d23df40..1b9944620b 100644 --- a/c/src/lib/libbsp/no_cpu/no_bsp/console/Makefile.in +++ b/c/src/lib/libbsp/no_cpu/no_bsp/console/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES= -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/no_cpu/no_bsp/shmsupp/Makefile.in b/c/src/lib/libbsp/no_cpu/no_bsp/shmsupp/Makefile.in index b4967b93cb..746f00b638 100644 --- a/c/src/lib/libbsp/no_cpu/no_bsp/shmsupp/Makefile.in +++ b/c/src/lib/libbsp/no_cpu/no_bsp/shmsupp/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES= -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/no_cpu/no_bsp/startup/Makefile.in b/c/src/lib/libbsp/no_cpu/no_bsp/startup/Makefile.in index 73bea20865..5b1c461c37 100644 --- a/c/src/lib/libbsp/no_cpu/no_bsp/startup/Makefile.in +++ b/c/src/lib/libbsp/no_cpu/no_bsp/startup/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES= -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=linkcmds $(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/no_cpu/no_bsp/timer/Makefile.in b/c/src/lib/libbsp/no_cpu/no_bsp/timer/Makefile.in index 076b7f4e77..57b562caf2 100644 --- a/c/src/lib/libbsp/no_cpu/no_bsp/timer/Makefile.in +++ b/c/src/lib/libbsp/no_cpu/no_bsp/timer/Makefile.in @@ -19,10 +19,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES= -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/no_cpu/no_bsp/wrapup/Makefile.in b/c/src/lib/libbsp/no_cpu/no_bsp/wrapup/Makefile.in index 4dc4ea5208..eb5d570df5 100644 --- a/c/src/lib/libbsp/no_cpu/no_bsp/wrapup/Makefile.in +++ b/c/src/lib/libbsp/no_cpu/no_bsp/wrapup/Makefile.in @@ -8,17 +8,22 @@ VPATH = @srcdir@ RTEMS_ROOT = @top_srcdir@ PROJECT_ROOT = @PROJECT_ROOT@ -BSP_PIECES=startup clock console shmsupp timer -GENERIC_PIECES=shmdr +BSP_PIECES=startup clock console timer +GENERIC_PIECES=$ + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/lib.cfg + +ifeq ($(HAS_MP),yes) +GENERIC_PIECES += shmdr +BSP_PIECES += shmsupp +endif # bummer; have to use $foreach since % pattern subst rules only replace 1x OBJS=$(foreach piece, $(BSP_PIECES), ../$(piece)/$(ARCH)/$(piece).rel) \ $(foreach piece, $(GENERIC_PIECES), ../../../$(piece)/$(ARCH)/$(piece).rel) LIB=$(ARCH)/libbsp.a -include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg -include $(RTEMS_ROOT)/make/lib.cfg - # # (OPTIONAL) Add local stuff here using += # diff --git a/c/src/lib/libbsp/powerpc/dmv177/clock/Makefile.in b/c/src/lib/libbsp/powerpc/dmv177/clock/Makefile.in index 7c2cfc0772..8a758fce71 100644 --- a/c/src/lib/libbsp/powerpc/dmv177/clock/Makefile.in +++ b/c/src/lib/libbsp/powerpc/dmv177/clock/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES= -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/powerpc/dmv177/sonic/Makefile.in b/c/src/lib/libbsp/powerpc/dmv177/sonic/Makefile.in index 35cd5ff209..b6c1bed0c4 100644 --- a/c/src/lib/libbsp/powerpc/dmv177/sonic/Makefile.in +++ b/c/src/lib/libbsp/powerpc/dmv177/sonic/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES= -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/powerpc/dmv177/start/Makefile.in b/c/src/lib/libbsp/powerpc/dmv177/start/Makefile.in index cb7d9c07ec..20c3bb77bf 100644 --- a/c/src/lib/libbsp/powerpc/dmv177/start/Makefile.in +++ b/c/src/lib/libbsp/powerpc/dmv177/start/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=start -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/powerpc/dmv177/start/start.S b/c/src/lib/libbsp/powerpc/dmv177/start/start.S new file mode 100644 index 0000000000..f8e4e4e614 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/dmv177/start/start.S @@ -0,0 +1,117 @@ +/* + * This is based on the mvme-crt0.S file from libgloss/rs6000. + * crt0.S -- startup file for PowerPC systems. + * + * Copyright (c) 1995 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + * + * $Id$ + */ + +#include +#include "ppc-asm.h" + + .file "start.s" + .section ".got2","aw" + .align 2 + +.LCTOC1 = .+32768 + + .extern FUNC_NAME(atexit) + .globl FUNC_NAME(__atexit) + .section ".sdata","aw" + .align 2 +FUNC_NAME(__atexit): /* tell C's eabi-ctor's we have an atexit function */ + .long FUNC_NAME(atexit)@fixup /* and that it is to register __do_global_dtors */ + + .section ".fixup","aw" + .align 2 + .long FUNC_NAME(__atexit) + + .section ".got2","aw" +.Ltable = .-.LCTOC1 + .long .LCTOC1 /* address we think .LCTOC1 is loaded at */ + +.Lbss_start = .-.LCTOC1 + .long __bss_start + +.Lend = .-.LCTOC1 + .long _end + +.Lstack = .-.LCTOC1 /* stack address if set by user */ + .long __stack + + .text +.Lptr: + .long .LCTOC1-.Laddr + + .globl _start + .type _start,@function +_start: + lis r5,0 + mr r4,r5 + ori r4,r4,0x0000 /* 0x2030 */ + mtmsr r4 + +/* Add special purpose register initialization based upon the console driver + * initialization of these registers XXXXX + */ + + bl .Laddr /* get current address */ + +.Laddr: + mflr r4 /* real address of .Laddr */ + lwz r5,(.Lptr-.Laddr)(r4) /* linker generated address of .LCTOC1 */ + add r5,r5,r4 /* correct to real pointer */ + lwz r4,.Ltable(r5) /* get linker's idea of where .Laddr is */ + subf r4,r4,r5 /* calculate difference between where linked and current */ + + /* clear bss */ + lwz r6,.Lbss_start(r5) /* calculate beginning of the BSS */ + lwz r7,.Lend(r5) /* calculate end of the BSS */ + add r6,r6,r4 /* adjust pointers */ + add r7,r7,r4 + + cmplw 1,r6,r7 + bc 4,4,.Ldone + + subf r8,r6,r7 /* number of bytes to zero */ + srwi r9,r8,2 /* number of words to zero */ + mtctr r9 + li r0,0 /* zero to clear memory */ + addi r6,r6,-4 /* adjust so we can use stwu */ +.Lloop: + stwu r0,4(r6) /* zero bss */ + bdnz .Lloop + +.Ldone: + + lwz r0,.Lstack(r5) /* stack address or 0 */ + cmplwi 1,r0,0 /* equal to 0? */ + bc 12,6,.Lnostack /* use default stack if == 0 */ + mr sp,r0 /* use user defined stack */ + +.Lnostack: + /* set up initial stack frame */ + addi sp,sp,-4 /* make sure we don't overwrite debug mem */ + lis r0,0 + stw r0,0(sp) /* clear back chain */ + stwu sp,-56(sp) /* push another stack frame */ + + /* Let her rip */ + bl FUNC_NAME(boot_card) + + /* return value from boot_card is argument to exit */ + /* bl FUNC_NAME(exit) */ + trap +.Lstart: + .size _start,.Lstart-_start diff --git a/c/src/lib/libbsp/powerpc/dmv177/start/start.s b/c/src/lib/libbsp/powerpc/dmv177/start/start.s deleted file mode 100644 index f8e4e4e614..0000000000 --- a/c/src/lib/libbsp/powerpc/dmv177/start/start.s +++ /dev/null @@ -1,117 +0,0 @@ -/* - * This is based on the mvme-crt0.S file from libgloss/rs6000. - * crt0.S -- startup file for PowerPC systems. - * - * Copyright (c) 1995 Cygnus Support - * - * The authors hereby grant permission to use, copy, modify, distribute, - * and license this software and its documentation for any purpose, provided - * that existing copyright notices are retained in all copies and that this - * notice is included verbatim in any distributions. No written agreement, - * license, or royalty fee is required for any of the authorized uses. - * Modifications to this software may be copyrighted by their authors - * and need not follow the licensing terms described here, provided that - * the new terms are clearly indicated on the first page of each file where - * they apply. - * - * $Id$ - */ - -#include -#include "ppc-asm.h" - - .file "start.s" - .section ".got2","aw" - .align 2 - -.LCTOC1 = .+32768 - - .extern FUNC_NAME(atexit) - .globl FUNC_NAME(__atexit) - .section ".sdata","aw" - .align 2 -FUNC_NAME(__atexit): /* tell C's eabi-ctor's we have an atexit function */ - .long FUNC_NAME(atexit)@fixup /* and that it is to register __do_global_dtors */ - - .section ".fixup","aw" - .align 2 - .long FUNC_NAME(__atexit) - - .section ".got2","aw" -.Ltable = .-.LCTOC1 - .long .LCTOC1 /* address we think .LCTOC1 is loaded at */ - -.Lbss_start = .-.LCTOC1 - .long __bss_start - -.Lend = .-.LCTOC1 - .long _end - -.Lstack = .-.LCTOC1 /* stack address if set by user */ - .long __stack - - .text -.Lptr: - .long .LCTOC1-.Laddr - - .globl _start - .type _start,@function -_start: - lis r5,0 - mr r4,r5 - ori r4,r4,0x0000 /* 0x2030 */ - mtmsr r4 - -/* Add special purpose register initialization based upon the console driver - * initialization of these registers XXXXX - */ - - bl .Laddr /* get current address */ - -.Laddr: - mflr r4 /* real address of .Laddr */ - lwz r5,(.Lptr-.Laddr)(r4) /* linker generated address of .LCTOC1 */ - add r5,r5,r4 /* correct to real pointer */ - lwz r4,.Ltable(r5) /* get linker's idea of where .Laddr is */ - subf r4,r4,r5 /* calculate difference between where linked and current */ - - /* clear bss */ - lwz r6,.Lbss_start(r5) /* calculate beginning of the BSS */ - lwz r7,.Lend(r5) /* calculate end of the BSS */ - add r6,r6,r4 /* adjust pointers */ - add r7,r7,r4 - - cmplw 1,r6,r7 - bc 4,4,.Ldone - - subf r8,r6,r7 /* number of bytes to zero */ - srwi r9,r8,2 /* number of words to zero */ - mtctr r9 - li r0,0 /* zero to clear memory */ - addi r6,r6,-4 /* adjust so we can use stwu */ -.Lloop: - stwu r0,4(r6) /* zero bss */ - bdnz .Lloop - -.Ldone: - - lwz r0,.Lstack(r5) /* stack address or 0 */ - cmplwi 1,r0,0 /* equal to 0? */ - bc 12,6,.Lnostack /* use default stack if == 0 */ - mr sp,r0 /* use user defined stack */ - -.Lnostack: - /* set up initial stack frame */ - addi sp,sp,-4 /* make sure we don't overwrite debug mem */ - lis r0,0 - stw r0,0(sp) /* clear back chain */ - stwu sp,-56(sp) /* push another stack frame */ - - /* Let her rip */ - bl FUNC_NAME(boot_card) - - /* return value from boot_card is argument to exit */ - /* bl FUNC_NAME(exit) */ - trap -.Lstart: - .size _start,.Lstart-_start diff --git a/c/src/lib/libbsp/powerpc/dmv177/startup/Makefile.in b/c/src/lib/libbsp/powerpc/dmv177/startup/Makefile.in index 0877918685..277f30b51c 100644 --- a/c/src/lib/libbsp/powerpc/dmv177/startup/Makefile.in +++ b/c/src/lib/libbsp/powerpc/dmv177/startup/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES= -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=linkcmds $(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/powerpc/dmv177/timer/Makefile.in b/c/src/lib/libbsp/powerpc/dmv177/timer/Makefile.in index 16665e4de9..0ac1995395 100644 --- a/c/src/lib/libbsp/powerpc/dmv177/timer/Makefile.in +++ b/c/src/lib/libbsp/powerpc/dmv177/timer/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES= -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/powerpc/helas403/dlentry/Makefile.in b/c/src/lib/libbsp/powerpc/helas403/dlentry/Makefile.in index dc40c405f6..5ecb9eaef8 100644 --- a/c/src/lib/libbsp/powerpc/helas403/dlentry/Makefile.in +++ b/c/src/lib/libbsp/powerpc/helas403/dlentry/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=dlentry -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/powerpc/helas403/dlentry/dlentry.S b/c/src/lib/libbsp/powerpc/helas403/dlentry/dlentry.S new file mode 100644 index 0000000000..3944d2bc47 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/helas403/dlentry/dlentry.S @@ -0,0 +1,144 @@ +/* dlentry.s + * + * This file contains the entry code for RTEMS programs starting + * after download to RAM + * + * Author: Thomas Doerfler + * IMD Ingenieurbuero fuer Microcomputertechnik + * + * COPYRIGHT (c) 1998 by IMD + * + * Changes from IMD are covered by the original distributions terms. + * This file has been derived from the papyrus BSP: + * + * This file contains the entry veneer for RTEMS programs + * downloaded to Papyrus. + * + * Author: Andrew Bray + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * $Id$ + */ + +#include "asm.h" + +/* + * The helas403 ELF link scripts support three special sections: + * .entry The actual entry point + * .vectors The section containing the interrupt entry veneers. + */ + +/* + * Downloaded code loads the vectors separately to 0x00000100, + * so .entry can be over 256 bytes. + * + * The other sections are linked in the following order: + * .entry + * .text + * .data + * .bss + * see linker command file for section placement + * + * The initial stack is set to stack.end + * + * All the entry veneer has to do is to clear the BSS. + */ + +/* + * GDB likes to have debugging information for the entry veneer. + * Here was some DWARF information. IMD removed it, because we + * could not check, whether it was still correct. Sorry. + + */ + +#if PPC_ASM == PPC_ASM_ELF + .section .entry +#else + .csect .text[PR] +#endif + + PUBLIC_VAR (download_entry) +SYM(download_entry): + bl .startup +base_addr: + +/*--------------------------------------------------------------------------- + * Parameters from linker + *--------------------------------------------------------------------------*/ +toc_pointer: +#if PPC_ASM == PPC_ASM_ELF + .long s.got +#else + .long TOC[tc0] +#endif +bss_length: + .long bss.size +bss_addr: + .long bss.start +stack_top: + .long stack.end +/*--------------------------------------------------------------------------- + * Reset_entry. + *--------------------------------------------------------------------------*/ +.startup: + /* Get start address, stack grows down from here... */ + mflr r1 + + /* Assume Bank regs set up..., cache etc. */ + bl bssclr + + .extern SYM(__vectors) + + lis r2,__vectors@h /* set EVPR exc. vector prefix */ + mtspr evpr,r2 + + /*------------------------------------------------------------------- + * C_setup. + *------------------------------------------------------------------*/ + lwz r2,toc_pointer-base_addr(r1) /* set r2 to toc */ + lwz r1,stack_top-base_addr(r1) /* set r1 to stack_top */ + + addi r1,r1,-56-4 /* start stack at text_addr - 56 */ + addi r3,r0,0x0 /* clear r3 */ + stw r3, 0(r1) /* Clear stack chain */ + stw r3, 4(r1) + stw r3, 8(r1) + stw r3, 12(r1) + .extern SYM (boot_card) + b SYM (boot_card) /* call the first C routine */ + +/*--------------------------------------------------------------------------- + * bssclr. + *--------------------------------------------------------------------------*/ +bssclr: + /*------------------------------------------------------------------- + * Data move finished, zero out bss. + *------------------------------------------------------------------*/ + lwz r2,bss_addr-base_addr(r1) /* start of bss set by loader */ + lwz r3,bss_length-base_addr(r1) /* bss length */ + rlwinm. r3,r3,30,0x3FFFFFFF /* form length/4 */ + beqlr /* no bss */ + mtctr r3 /* set ctr reg */ + xor r6,r6,r6 /* r6 = 0 */ +clear_bss: + stswi r6,r2,0x4 /* store r6 */ + addi r2,r2,0x4 /* update r2 */ + bdnz clear_bss /* decrement counter and loop */ + blr /* return */ +.L_text_e: + +#if PPC_ABI == PPC_ABI_POWEROPEN + DESCRIPTOR (startup) +#endif diff --git a/c/src/lib/libbsp/powerpc/helas403/dlentry/dlentry.s b/c/src/lib/libbsp/powerpc/helas403/dlentry/dlentry.s deleted file mode 100644 index 3944d2bc47..0000000000 --- a/c/src/lib/libbsp/powerpc/helas403/dlentry/dlentry.s +++ /dev/null @@ -1,144 +0,0 @@ -/* dlentry.s - * - * This file contains the entry code for RTEMS programs starting - * after download to RAM - * - * Author: Thomas Doerfler - * IMD Ingenieurbuero fuer Microcomputertechnik - * - * COPYRIGHT (c) 1998 by IMD - * - * Changes from IMD are covered by the original distributions terms. - * This file has been derived from the papyrus BSP: - * - * This file contains the entry veneer for RTEMS programs - * downloaded to Papyrus. - * - * Author: Andrew Bray - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * $Id$ - */ - -#include "asm.h" - -/* - * The helas403 ELF link scripts support three special sections: - * .entry The actual entry point - * .vectors The section containing the interrupt entry veneers. - */ - -/* - * Downloaded code loads the vectors separately to 0x00000100, - * so .entry can be over 256 bytes. - * - * The other sections are linked in the following order: - * .entry - * .text - * .data - * .bss - * see linker command file for section placement - * - * The initial stack is set to stack.end - * - * All the entry veneer has to do is to clear the BSS. - */ - -/* - * GDB likes to have debugging information for the entry veneer. - * Here was some DWARF information. IMD removed it, because we - * could not check, whether it was still correct. Sorry. - - */ - -#if PPC_ASM == PPC_ASM_ELF - .section .entry -#else - .csect .text[PR] -#endif - - PUBLIC_VAR (download_entry) -SYM(download_entry): - bl .startup -base_addr: - -/*--------------------------------------------------------------------------- - * Parameters from linker - *--------------------------------------------------------------------------*/ -toc_pointer: -#if PPC_ASM == PPC_ASM_ELF - .long s.got -#else - .long TOC[tc0] -#endif -bss_length: - .long bss.size -bss_addr: - .long bss.start -stack_top: - .long stack.end -/*--------------------------------------------------------------------------- - * Reset_entry. - *--------------------------------------------------------------------------*/ -.startup: - /* Get start address, stack grows down from here... */ - mflr r1 - - /* Assume Bank regs set up..., cache etc. */ - bl bssclr - - .extern SYM(__vectors) - - lis r2,__vectors@h /* set EVPR exc. vector prefix */ - mtspr evpr,r2 - - /*------------------------------------------------------------------- - * C_setup. - *------------------------------------------------------------------*/ - lwz r2,toc_pointer-base_addr(r1) /* set r2 to toc */ - lwz r1,stack_top-base_addr(r1) /* set r1 to stack_top */ - - addi r1,r1,-56-4 /* start stack at text_addr - 56 */ - addi r3,r0,0x0 /* clear r3 */ - stw r3, 0(r1) /* Clear stack chain */ - stw r3, 4(r1) - stw r3, 8(r1) - stw r3, 12(r1) - .extern SYM (boot_card) - b SYM (boot_card) /* call the first C routine */ - -/*--------------------------------------------------------------------------- - * bssclr. - *--------------------------------------------------------------------------*/ -bssclr: - /*------------------------------------------------------------------- - * Data move finished, zero out bss. - *------------------------------------------------------------------*/ - lwz r2,bss_addr-base_addr(r1) /* start of bss set by loader */ - lwz r3,bss_length-base_addr(r1) /* bss length */ - rlwinm. r3,r3,30,0x3FFFFFFF /* form length/4 */ - beqlr /* no bss */ - mtctr r3 /* set ctr reg */ - xor r6,r6,r6 /* r6 = 0 */ -clear_bss: - stswi r6,r2,0x4 /* store r6 */ - addi r2,r2,0x4 /* update r2 */ - bdnz clear_bss /* decrement counter and loop */ - blr /* return */ -.L_text_e: - -#if PPC_ABI == PPC_ABI_POWEROPEN - DESCRIPTOR (startup) -#endif diff --git a/c/src/lib/libbsp/powerpc/helas403/flashentry/Makefile.in b/c/src/lib/libbsp/powerpc/helas403/flashentry/Makefile.in index 683f996472..b56cce2ea8 100644 --- a/c/src/lib/libbsp/powerpc/helas403/flashentry/Makefile.in +++ b/c/src/lib/libbsp/powerpc/helas403/flashentry/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=flashentry -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/powerpc/helas403/flashentry/flashentry.S b/c/src/lib/libbsp/powerpc/helas403/flashentry/flashentry.S new file mode 100644 index 0000000000..133e64e650 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/helas403/flashentry/flashentry.S @@ -0,0 +1,469 @@ +/* flashentry.s + * + * This file contains the entry code for RTEMS programs starting + * directly from Flash. + * + * Author: Thomas Doerfler + * IMD Ingenieurbuero fuer Microcomputertechnik + * + * COPYRIGHT (c) 1998 by IMD + * + * Changes from IMD are covered by the original distributions terms. + * This file has been derived from the papyrus BSP: + * + * This file contains the entry veneer for RTEMS programs + * stored in Papyrus' flash ROM. + * + * Author: Andrew Bray + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * $Id$ + */ + +#include "asm.h" +#include + +/*---------------------------------------------------------------------------- + * Reset_entry. + *---------------------------------------------------------------------------*/ +#if PPC_ASM == PPC_ASM_ELF + .section .reset,"ax",@progbits + /* this section MUST be located at absolute address 0xFFFFFFFC + or last word of EPROM */ +#else + .csect .text[PR] +#endif + + ba flash_entry /* this is the first instruction after reset */ + + .previous + +/*---------------------------------------------------------------------------- + * ROM Vector area. + *---------------------------------------------------------------------------*/ +#if PPC_ASM == PPC_ASM_ELF + .section .entry,"ax",@progbits +#else + .csect .text[PR] +#endif + PUBLIC_VAR (flash_entry) +SYM (flash_entry): + bl .startup /* call startup, link reg points to base_addr */ +base_addr: +/*---------------------------------------------------------------------------- + * Parameters from linker + *---------------------------------------------------------------------------*/ +toc_pointer: +#if PPC_ASM == PPC_ASM_ELF + .long s.got +#else + .long TOC[tc0] +#endif +text_length: + .long text.size +text_addr: + .long text.start +copy_src: + .long copy.src +copy_length: + .long copy.size +copy_dest: + .long copy.dest +bss_length: + .long bss.size +bss_addr: + .long bss.start +stack_top: + .long stack.end + +/*---------------------------------------------------------------------------- + * from Reset_entry. + *---------------------------------------------------------------------------*/ +.startup: + /* Get start address, r1 points to label base_addr */ + mflr r1 + + /* Set up Bank regs, cache etc. */ + /* set up bank register BR0 for Flash-EPROM: + * NOTE: bank size should stay 1MByte, this is standard size + * after RESET + * base addr = Fffxxxxx -> 0b11111111........................ + * bank size = 1 MByte -> 0b........000..................... (std) + * bank use = readonly -> 0b...........01................... + * seq. fill = targ frst-> 0b.............0.................. + * burst mode= enable -> 0b..............1................. + * bus width = 8 bit -> 0b...............00............... + * ready pin = disable -> 0b.................0.............. + * first wait= 2 clocks -> 0b..................0010.......... + * burst wait= 2 clocks -> 0b......................10........ + * CSon time = 0 clocks -> 0b........................0....... + * OEon time = 0 clocks -> 0b.........................0...... + * WBon time = 1 clocks -> 0b..........................1..... + * WBoff time= 0 clocks -> 0b...........................0.... + * Hold time = 1 clocks -> 0b............................001. + * ram type = SRAM(ign)-> 0b...............................1 + * value 0b11111111000010100000101000100011 + * 0x F F 0 A 0 A 2 3 + */ + lis r2,0xFF0A + ori r2,r2,0x0A23 + + mtdcr br0,r2 /* write to DCR BR0 */ + + + /*-------------------------------------------------------------------- + * test various RAM configurations (from big to small per bank) + *------------------------------------------------------------------*/ + /*-------------------------------------------------------------------- + * test RAM config 16 MByte (1x4Mx32Bit) + *------------------------------------------------------------------*/ + /* set up bank register BR7 for DRAM: + * base addr = 000xxxxx -> 0b00000000........................ + * bank size = 16MByte -> 0b........100..................... + * bank use = readwrite-> 0b...........11................... + * seq. fill = targ.frst-> 0b.............0.................. + * early RAS = disabled -> 0b..............0................. + * bus width = 32bit -> 0b...............10............... + * adr mux = internal -> 0b.................0.............. + * RAS to CAS= 2 clocks -> 0b..................1............. + * Alt. Rfrsh= normal -> 0b...................0............ + * page mode = enabled -> 0b....................1........... + * first wait= 1 clocks -> 0b.....................01......... + * burst wait= 1 clocks -> 0b.......................01....... + * precharge = 1 clocks -> 0b.........................0...... + * RAS Rfrsh = 2 clocks -> 0b..........................1..... + * Rfrsh Itvl= 512 clks -> 0b...........................1000. + * ram type = DRAM -> 0b...............................0 + * value 0b00000000100110010010101010110000 + * 0x 0 0 9 9 2 A B 0 + */ + lis r2,0x0099 + ori r2,r2,0x2AB0 + mtdcr br7,r2 /* write to DCR BR7*/ + + lis r2,0x0000 /* start address = 0x00000000 */ + lis r3,0x0100 /* size 16 MB = 0x01000000 */ + bl ramacc /* test memory accessibility */ + cmpi 0,0,r4,0 /* memory ok? else test smaller size */ + bne ramcfgt18 + + /*-------------------------------------------------------------------- + * test RAM config 32 MByte (2x4Mx32Bit) + *------------------------------------------------------------------*/ + /* set up bank register BR7 like above + * set up bank register BR6 for DRAM: + * base addr = 010xxxxx -> 0b00010000........................ + * bank size = 16MByte -> 0b........100..................... (for now) + * bank use = readwrite-> 0b...........11................... + * seq. fill = targ.frst-> 0b.............0.................. + * early RAS = disabled -> 0b..............0................. + * bus width = 32bit -> 0b...............10............... + * adr mux = internal -> 0b.................0.............. + * RAS to CAS= 2 clocks -> 0b..................1............. + * Alt. Rfrsh= normal -> 0b...................0............ + * page mode = enabled -> 0b....................1........... + * first wait= 1 clocks -> 0b.....................01......... + * burst wait= 1 clocks -> 0b.......................01....... + * precharge = 1 clocks -> 0b.........................0...... + * RAS Rfrsh = 2 clocks -> 0b..........................1..... + * Rfrsh Itvl= 512 clks -> 0b...........................1000. + * ram type = DRAM -> 0b...............................0 + * value 0b00010000100110010010101010110000 + * 0x 1 0 9 9 2 A B 0 + */ + lis r2,0x1099 + ori r2,r2,0x2AB0 + mtdcr br6,r2 /* write to DCR BR6*/ + + lis r2,0x0100 /* start address = 0x01000000 */ + lis r3,0x0100 /* size 16 MB = 0x01000000 */ + bl ramacc /* test memory accessibility */ + cmpi 0,0,r4,0 /* memory ok? else test smaller size */ + beq ramcfgok /* ok, we found configuration... +/ + + lis r2,0x0000 /* disable BR6, config not ok */ + mtdcr br6,r2 /* write to DCR BR6*/ + b ramcfgok /* and finish configuration */ + +ramcfgt18: + /*-------------------------------------------------------------------- + * test RAM config 8 MByte (1x2Mx32Bit) + *------------------------------------------------------------------*/ + /* set up bank register BR7 for DRAM: + * base addr = 000xxxxx -> 0b00000000........................ + * bank size = 8MByte -> 0b........011..................... + * bank use = readwrite-> 0b...........11................... + * seq. fill = targ.frst-> 0b.............0.................. + * early RAS = disabled -> 0b..............0................. + * bus width = 32bit -> 0b...............10............... + * adr mux = internal -> 0b.................0.............. + * RAS to CAS= 2 clocks -> 0b..................1............. + * Alt. Rfrsh= normal -> 0b...................0............ + * page mode = enabled -> 0b....................1........... + * first wait= 1 clocks -> 0b.....................01......... + * burst wait= 1 clocks -> 0b.......................01....... + * precharge = 1 clocks -> 0b.........................0...... + * RAS Rfrsh = 2 clocks -> 0b..........................1..... + * Rfrsh Itvl= 512 clks -> 0b...........................1000. + * ram type = DRAM -> 0b...............................0 + * value 0b00000000011110010010101010110000 + * 0x 0 0 7 9 2 A B 0 + */ + lis r2,0x0079 + ori r2,r2,0x2AB0 + mtdcr br7,r2 /* write to DCR BR7 */ + + lis r2,0x0000 /* start address = 0x00000000 */ + lis r3,0x0080 /* size 8 MB = 0x00800000 */ + bl ramacc /* test memory accessibility */ + cmpi 0,0,r4,0 /* memory ok? else test smaller size */ + bne ramcfgt14 + + /*-------------------------------------------------------------------- + * test RAM config 16 MByte (2x2Mx32Bit) + *------------------------------------------------------------------*/ + /* set up bank register BR7 like above + * set up bank register BR6 for DRAM: + * base addr = 008xxxxx -> 0b00001000........................ + * bank size = 08MByte -> 0b........011..................... (for now) + * bank use = readwrite-> 0b...........11................... + * seq. fill = targ.frst-> 0b.............0.................. + * early RAS = disabled -> 0b..............0................. + * bus width = 32bit -> 0b...............10............... + * adr mux = internal -> 0b.................0.............. + * RAS to CAS= 2 clocks -> 0b..................1............. + * Alt. Rfrsh= normal -> 0b...................0............ + * page mode = enabled -> 0b....................1........... + * first wait= 1 clocks -> 0b.....................01......... + * burst wait= 1 clocks -> 0b.......................01....... + * precharge = 1 clocks -> 0b.........................0...... + * RAS Rfrsh = 2 clocks -> 0b..........................1..... + * Rfrsh Itvl= 512 clks -> 0b...........................1000. + * ram type = DRAM -> 0b...............................0 + * value 0b00001000011110010010101010110000 + * 0x 0 8 7 9 2 A B 0 + */ + lis r2,0x0879 + ori r2,r2,0x2AB0 + mtdcr br6,r2 /* write to DCR BR6*/ + + lis r2,0x0080 /* start address = 0x00800000 */ + lis r3,0x0080 /* size 8 MB = 0x00800000 */ + bl ramacc /* test memory accessibility */ + cmpi 0,0,r4,0 /* memory ok? else test smaller size */ + beq ramcfgok /* ok, we found configuration... +/ + + lis r2,0x0000 /* disable BR6, config not ok */ + mtdcr br6,r2 /* write to DCR BR6*/ + b ramcfgok /* and finish configuration */ + +ramcfgt14: + /*-------------------------------------------------------------------- + * test RAM config 4 MByte (1x1Mx32Bit) + *------------------------------------------------------------------*/ + /* set up bank register BR7 for DRAM: + * base addr = 000xxxxx -> 0b00000000........................ + * bank size = 4MByte -> 0b........010..................... + * bank use = readwrite-> 0b...........11................... + * seq. fill = targ.frst-> 0b.............0.................. + * early RAS = disabled -> 0b..............0................. + * bus width = 32bit -> 0b...............10............... + * adr mux = internal -> 0b.................0.............. + * RAS to CAS= 2 clocks -> 0b..................1............. + * Alt. Rfrsh= normal -> 0b...................0............ + * page mode = enabled -> 0b....................1........... + * first wait= 1 clocks -> 0b.....................01......... + * burst wait= 1 clocks -> 0b.......................01....... + * precharge = 1 clocks -> 0b.........................0...... + * RAS Rfrsh = 2 clocks -> 0b..........................1..... + * Rfrsh Itvl= 512 clks -> 0b...........................1000. + * ram type = DRAM -> 0b...............................0 + * value 0b00000000010110010010101010110000 + * 0x 0 0 5 9 2 A B 0 + */ + /* + * FIXME: this is the minimum size supported, should test and + * report error, when failed + */ + lis r2,0x0059 + ori r2,r2,0x2AB0 + mtdcr br7,r2 /* write to DCR BR7*/ + + /*-------------------------------------------------------------------- + * test RAM config 8 MByte (2x1Mx32Bit) + *------------------------------------------------------------------*/ + /* set up bank register BR7 like above + * set up bank register BR6 for DRAM: + * base addr = 004xxxxx -> 0b00000100........................ + * bank size = 4MByte -> 0b........010..................... (for now) + * bank use = readwrite-> 0b...........11................... + * seq. fill = targ.frst-> 0b.............0.................. + * early RAS = disabled -> 0b..............0................. + * bus width = 32bit -> 0b...............10............... + * adr mux = internal -> 0b.................0.............. + * RAS to CAS= 2 clocks -> 0b..................1............. + * Alt. Rfrsh= normal -> 0b...................0............ + * page mode = enabled -> 0b....................1........... + * first wait= 1 clocks -> 0b.....................01......... + * burst wait= 1 clocks -> 0b.......................01....... + * precharge = 1 clocks -> 0b.........................0...... + * RAS Rfrsh = 2 clocks -> 0b..........................1..... + * Rfrsh Itvl= 512 clks -> 0b...........................1000. + * ram type = DRAM -> 0b...............................0 + * value 0b00000100010110010010101010110000 + * 0x 0 4 5 9 2 A B 0 + */ + lis r2,0x0459 + ori r2,r2,0x2AB0 + mtdcr br6,r2 /* write to DCR BR6*/ + + lis r2,0x0040 /* start address = 0x00400000 */ + lis r3,0x0040 /* size 4 MB = 0x00400000 */ + bl ramacc /* test memory accessibility */ + cmpi 0,0,r4,0 /* memory ok? else test smaller size */ + beq ramcfgok /* ok, we found configuration... +/ + + lis r2,0x0000 /* disable BR6, config not ok */ + mtdcr br6,r2 /* write to DCR BR6*/ + b ramcfgok /* and finish configuration */ + +ramcfgok: + /*-------------------------------------------------------------------- + * init the DRAM where STACK+ DATA+ BBS will be placed. If this is OK + * we will return here. + *-------------------------------------------------------------------*/ + bl rom2ram + + /* clear caches */ + addi r2,0,PPC_I_CACHE/PPC_CACHE_ALIGNMENT + mtctr r2 /* count the loops needed... */ + xor r2,r2,r2 /* start at adr zero */ +icinvlp: + iccci 0,r2 + addi r2,r2,PPC_CACHE_ALIGNMENT + bdnz icinvlp + + addi r2,r0,PPC_D_CACHE/PPC_CACHE_ALIGNMENT + mtctr r2 /* count the loops needed... */ + xor r2,r2,r2 /* start at adr 0 */ +dcinvlp: + dccci 0,r2 + addi r2,r2,PPC_CACHE_ALIGNMENT + bdnz dcinvlp + /*-------------------------------------------------------------------- + * Enable two 128MB cachable regions. + * FEPROM is cachable at 0xFFF00000..0xFFFFFFFF + * DRAM is cachable at 0x00000000..0x00FFFFFF + * FEPROM is noncachable at 0x7FF00000..0x7FFFFFFF + * DRAM is noncachable at 0x80000000..0x80FFFFFF + *-------------------------------------------------------------------*/ + addis r2,r0,0x8000 + addi r2,r2,0x0001 + + mtspr iccr, r2 /* ICCR */ + mtspr dccr, r2 /* DCCR */ + + .extern SYM(__vectors) + + lis r2,__vectors@h /* set EVPR exc. vector prefix */ + mtspr evpr,r2 + + lis r2,0x0000 + ori r2,r2,0x0000 + mtmsr r2 /* set default msr */ + lis r2,0x0000 /* do not allow critical IRQ */ + ori r2,r2,0x0000 + mtdcr exier, r2 /* disable all external IRQs */ + + addi r2,r0,-1 /* r2 = 0xffffffff */ + mtdcr exisr, r2 /* clear all pendingdisable IRQs */ + + /*-------------------------------------------------------------------- + * C_setup. + *-------------------------------------------------------------------*/ + + lwz r2,toc_pointer-base_addr(r1) /* set r2 to toc */ + lwz r1,stack_top-base_addr(r1) /* set r1 to stack_top */ + + addi r1,r1,-56 /* start stack at data_addr - 56 */ + addi r3,r0,0x0 /* clear r3 */ + stw r3, 0(r1) /* Clear stack chain */ + stw r3, 4(r1) + stw r3, 8(r1) + stw r3, 12(r1) + .extern SYM (boot_card) + b SYM (boot_card) /* call the first C routine */ + +/*---------------------------------------------------------------------------- + * Rom2ram. + *---------------------------------------------------------------------------*/ +rom2ram: + lwz r2,copy_dest-base_addr(r1) /* start of data set by loader */ + lwz r3,copy_length-base_addr(r1) /* data length */ + rlwinm r3,r3,30,0x3FFFFFFF /* form length/4 */ + mtctr r3 /* set ctr reg */ + /*-------------------------------------------------------------------- + * Calculate offset of data in image. + *-------------------------------------------------------------------*/ + lwz r4,copy_src-base_addr(r1) /* get start of copy area */ +move_data: + lswi r6,r4,0x4 /* load r6 */ + stswi r6,r2,0x4 /* store r6 */ + addi r4,r4,0x4 /* update r4 */ + addi r2,r2,0x4 /* update r2 */ + bdnz move_data /* decrement counter and loop */ + /*-------------------------------------------------------------------- + * Data move finished, zero out bss. + *-------------------------------------------------------------------*/ + lwz r2,bss_addr-base_addr(r1) /* start of bss set by loader */ + lwz r3,bss_length-base_addr(r1) /* bss length */ + rlwinm. r3,r3,30,0x3FFFFFFF /* form length/4 */ + beqlr /* no bss */ + mtctr r3 /* set ctr reg */ + xor r6,r6,r6 /* r6 = 0 */ +clear_bss: + stswi r6,r2,0x4 /* store r6 */ + addi r2,r2,0x4 /* update r2 */ + bdnz clear_bss /* decrement counter and loop */ + blr /* return */ + +/*---------------------------------------------------------------------------- + * ramacc test accessibility of RAM + * input: r2 = start address, r3 = length (in byte) + * output: r4 = 0 -> ok, !=0 -> fail + *---------------------------------------------------------------------------*/ +ramacc: + xor r4,r4,r4 /* r4 = 0 */ + stw r4,0(r2) /* init ram at start address */ + addi r4,r0,0x04 /* set start shift */ +ramaccf1: + cmp 0,0,r4,r3 /* compare with length */ + bge ramaccfx /* r4 >= r3? then finished */ + add r5,r4,r2 /* get next address to fill */ + stw r4,0(r5) /* store new pattern */ + add r4,r4,r4 /* r4 = r4*2 */ + b ramaccf1 /* and then next loop */ + +ramaccfx: + lwz r4,0(r2) /* get memory at start adr */ + blr + + +#if PPC_ABI == PPC_ABI_POWEROPEN + DESCRIPTOR (startup) +#endif + + + diff --git a/c/src/lib/libbsp/powerpc/helas403/flashentry/flashentry.s b/c/src/lib/libbsp/powerpc/helas403/flashentry/flashentry.s deleted file mode 100644 index 133e64e650..0000000000 --- a/c/src/lib/libbsp/powerpc/helas403/flashentry/flashentry.s +++ /dev/null @@ -1,469 +0,0 @@ -/* flashentry.s - * - * This file contains the entry code for RTEMS programs starting - * directly from Flash. - * - * Author: Thomas Doerfler - * IMD Ingenieurbuero fuer Microcomputertechnik - * - * COPYRIGHT (c) 1998 by IMD - * - * Changes from IMD are covered by the original distributions terms. - * This file has been derived from the papyrus BSP: - * - * This file contains the entry veneer for RTEMS programs - * stored in Papyrus' flash ROM. - * - * Author: Andrew Bray - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * $Id$ - */ - -#include "asm.h" -#include - -/*---------------------------------------------------------------------------- - * Reset_entry. - *---------------------------------------------------------------------------*/ -#if PPC_ASM == PPC_ASM_ELF - .section .reset,"ax",@progbits - /* this section MUST be located at absolute address 0xFFFFFFFC - or last word of EPROM */ -#else - .csect .text[PR] -#endif - - ba flash_entry /* this is the first instruction after reset */ - - .previous - -/*---------------------------------------------------------------------------- - * ROM Vector area. - *---------------------------------------------------------------------------*/ -#if PPC_ASM == PPC_ASM_ELF - .section .entry,"ax",@progbits -#else - .csect .text[PR] -#endif - PUBLIC_VAR (flash_entry) -SYM (flash_entry): - bl .startup /* call startup, link reg points to base_addr */ -base_addr: -/*---------------------------------------------------------------------------- - * Parameters from linker - *---------------------------------------------------------------------------*/ -toc_pointer: -#if PPC_ASM == PPC_ASM_ELF - .long s.got -#else - .long TOC[tc0] -#endif -text_length: - .long text.size -text_addr: - .long text.start -copy_src: - .long copy.src -copy_length: - .long copy.size -copy_dest: - .long copy.dest -bss_length: - .long bss.size -bss_addr: - .long bss.start -stack_top: - .long stack.end - -/*---------------------------------------------------------------------------- - * from Reset_entry. - *---------------------------------------------------------------------------*/ -.startup: - /* Get start address, r1 points to label base_addr */ - mflr r1 - - /* Set up Bank regs, cache etc. */ - /* set up bank register BR0 for Flash-EPROM: - * NOTE: bank size should stay 1MByte, this is standard size - * after RESET - * base addr = Fffxxxxx -> 0b11111111........................ - * bank size = 1 MByte -> 0b........000..................... (std) - * bank use = readonly -> 0b...........01................... - * seq. fill = targ frst-> 0b.............0.................. - * burst mode= enable -> 0b..............1................. - * bus width = 8 bit -> 0b...............00............... - * ready pin = disable -> 0b.................0.............. - * first wait= 2 clocks -> 0b..................0010.......... - * burst wait= 2 clocks -> 0b......................10........ - * CSon time = 0 clocks -> 0b........................0....... - * OEon time = 0 clocks -> 0b.........................0...... - * WBon time = 1 clocks -> 0b..........................1..... - * WBoff time= 0 clocks -> 0b...........................0.... - * Hold time = 1 clocks -> 0b............................001. - * ram type = SRAM(ign)-> 0b...............................1 - * value 0b11111111000010100000101000100011 - * 0x F F 0 A 0 A 2 3 - */ - lis r2,0xFF0A - ori r2,r2,0x0A23 - - mtdcr br0,r2 /* write to DCR BR0 */ - - - /*-------------------------------------------------------------------- - * test various RAM configurations (from big to small per bank) - *------------------------------------------------------------------*/ - /*-------------------------------------------------------------------- - * test RAM config 16 MByte (1x4Mx32Bit) - *------------------------------------------------------------------*/ - /* set up bank register BR7 for DRAM: - * base addr = 000xxxxx -> 0b00000000........................ - * bank size = 16MByte -> 0b........100..................... - * bank use = readwrite-> 0b...........11................... - * seq. fill = targ.frst-> 0b.............0.................. - * early RAS = disabled -> 0b..............0................. - * bus width = 32bit -> 0b...............10............... - * adr mux = internal -> 0b.................0.............. - * RAS to CAS= 2 clocks -> 0b..................1............. - * Alt. Rfrsh= normal -> 0b...................0............ - * page mode = enabled -> 0b....................1........... - * first wait= 1 clocks -> 0b.....................01......... - * burst wait= 1 clocks -> 0b.......................01....... - * precharge = 1 clocks -> 0b.........................0...... - * RAS Rfrsh = 2 clocks -> 0b..........................1..... - * Rfrsh Itvl= 512 clks -> 0b...........................1000. - * ram type = DRAM -> 0b...............................0 - * value 0b00000000100110010010101010110000 - * 0x 0 0 9 9 2 A B 0 - */ - lis r2,0x0099 - ori r2,r2,0x2AB0 - mtdcr br7,r2 /* write to DCR BR7*/ - - lis r2,0x0000 /* start address = 0x00000000 */ - lis r3,0x0100 /* size 16 MB = 0x01000000 */ - bl ramacc /* test memory accessibility */ - cmpi 0,0,r4,0 /* memory ok? else test smaller size */ - bne ramcfgt18 - - /*-------------------------------------------------------------------- - * test RAM config 32 MByte (2x4Mx32Bit) - *------------------------------------------------------------------*/ - /* set up bank register BR7 like above - * set up bank register BR6 for DRAM: - * base addr = 010xxxxx -> 0b00010000........................ - * bank size = 16MByte -> 0b........100..................... (for now) - * bank use = readwrite-> 0b...........11................... - * seq. fill = targ.frst-> 0b.............0.................. - * early RAS = disabled -> 0b..............0................. - * bus width = 32bit -> 0b...............10............... - * adr mux = internal -> 0b.................0.............. - * RAS to CAS= 2 clocks -> 0b..................1............. - * Alt. Rfrsh= normal -> 0b...................0............ - * page mode = enabled -> 0b....................1........... - * first wait= 1 clocks -> 0b.....................01......... - * burst wait= 1 clocks -> 0b.......................01....... - * precharge = 1 clocks -> 0b.........................0...... - * RAS Rfrsh = 2 clocks -> 0b..........................1..... - * Rfrsh Itvl= 512 clks -> 0b...........................1000. - * ram type = DRAM -> 0b...............................0 - * value 0b00010000100110010010101010110000 - * 0x 1 0 9 9 2 A B 0 - */ - lis r2,0x1099 - ori r2,r2,0x2AB0 - mtdcr br6,r2 /* write to DCR BR6*/ - - lis r2,0x0100 /* start address = 0x01000000 */ - lis r3,0x0100 /* size 16 MB = 0x01000000 */ - bl ramacc /* test memory accessibility */ - cmpi 0,0,r4,0 /* memory ok? else test smaller size */ - beq ramcfgok /* ok, we found configuration... +/ - - lis r2,0x0000 /* disable BR6, config not ok */ - mtdcr br6,r2 /* write to DCR BR6*/ - b ramcfgok /* and finish configuration */ - -ramcfgt18: - /*-------------------------------------------------------------------- - * test RAM config 8 MByte (1x2Mx32Bit) - *------------------------------------------------------------------*/ - /* set up bank register BR7 for DRAM: - * base addr = 000xxxxx -> 0b00000000........................ - * bank size = 8MByte -> 0b........011..................... - * bank use = readwrite-> 0b...........11................... - * seq. fill = targ.frst-> 0b.............0.................. - * early RAS = disabled -> 0b..............0................. - * bus width = 32bit -> 0b...............10............... - * adr mux = internal -> 0b.................0.............. - * RAS to CAS= 2 clocks -> 0b..................1............. - * Alt. Rfrsh= normal -> 0b...................0............ - * page mode = enabled -> 0b....................1........... - * first wait= 1 clocks -> 0b.....................01......... - * burst wait= 1 clocks -> 0b.......................01....... - * precharge = 1 clocks -> 0b.........................0...... - * RAS Rfrsh = 2 clocks -> 0b..........................1..... - * Rfrsh Itvl= 512 clks -> 0b...........................1000. - * ram type = DRAM -> 0b...............................0 - * value 0b00000000011110010010101010110000 - * 0x 0 0 7 9 2 A B 0 - */ - lis r2,0x0079 - ori r2,r2,0x2AB0 - mtdcr br7,r2 /* write to DCR BR7 */ - - lis r2,0x0000 /* start address = 0x00000000 */ - lis r3,0x0080 /* size 8 MB = 0x00800000 */ - bl ramacc /* test memory accessibility */ - cmpi 0,0,r4,0 /* memory ok? else test smaller size */ - bne ramcfgt14 - - /*-------------------------------------------------------------------- - * test RAM config 16 MByte (2x2Mx32Bit) - *------------------------------------------------------------------*/ - /* set up bank register BR7 like above - * set up bank register BR6 for DRAM: - * base addr = 008xxxxx -> 0b00001000........................ - * bank size = 08MByte -> 0b........011..................... (for now) - * bank use = readwrite-> 0b...........11................... - * seq. fill = targ.frst-> 0b.............0.................. - * early RAS = disabled -> 0b..............0................. - * bus width = 32bit -> 0b...............10............... - * adr mux = internal -> 0b.................0.............. - * RAS to CAS= 2 clocks -> 0b..................1............. - * Alt. Rfrsh= normal -> 0b...................0............ - * page mode = enabled -> 0b....................1........... - * first wait= 1 clocks -> 0b.....................01......... - * burst wait= 1 clocks -> 0b.......................01....... - * precharge = 1 clocks -> 0b.........................0...... - * RAS Rfrsh = 2 clocks -> 0b..........................1..... - * Rfrsh Itvl= 512 clks -> 0b...........................1000. - * ram type = DRAM -> 0b...............................0 - * value 0b00001000011110010010101010110000 - * 0x 0 8 7 9 2 A B 0 - */ - lis r2,0x0879 - ori r2,r2,0x2AB0 - mtdcr br6,r2 /* write to DCR BR6*/ - - lis r2,0x0080 /* start address = 0x00800000 */ - lis r3,0x0080 /* size 8 MB = 0x00800000 */ - bl ramacc /* test memory accessibility */ - cmpi 0,0,r4,0 /* memory ok? else test smaller size */ - beq ramcfgok /* ok, we found configuration... +/ - - lis r2,0x0000 /* disable BR6, config not ok */ - mtdcr br6,r2 /* write to DCR BR6*/ - b ramcfgok /* and finish configuration */ - -ramcfgt14: - /*-------------------------------------------------------------------- - * test RAM config 4 MByte (1x1Mx32Bit) - *------------------------------------------------------------------*/ - /* set up bank register BR7 for DRAM: - * base addr = 000xxxxx -> 0b00000000........................ - * bank size = 4MByte -> 0b........010..................... - * bank use = readwrite-> 0b...........11................... - * seq. fill = targ.frst-> 0b.............0.................. - * early RAS = disabled -> 0b..............0................. - * bus width = 32bit -> 0b...............10............... - * adr mux = internal -> 0b.................0.............. - * RAS to CAS= 2 clocks -> 0b..................1............. - * Alt. Rfrsh= normal -> 0b...................0............ - * page mode = enabled -> 0b....................1........... - * first wait= 1 clocks -> 0b.....................01......... - * burst wait= 1 clocks -> 0b.......................01....... - * precharge = 1 clocks -> 0b.........................0...... - * RAS Rfrsh = 2 clocks -> 0b..........................1..... - * Rfrsh Itvl= 512 clks -> 0b...........................1000. - * ram type = DRAM -> 0b...............................0 - * value 0b00000000010110010010101010110000 - * 0x 0 0 5 9 2 A B 0 - */ - /* - * FIXME: this is the minimum size supported, should test and - * report error, when failed - */ - lis r2,0x0059 - ori r2,r2,0x2AB0 - mtdcr br7,r2 /* write to DCR BR7*/ - - /*-------------------------------------------------------------------- - * test RAM config 8 MByte (2x1Mx32Bit) - *------------------------------------------------------------------*/ - /* set up bank register BR7 like above - * set up bank register BR6 for DRAM: - * base addr = 004xxxxx -> 0b00000100........................ - * bank size = 4MByte -> 0b........010..................... (for now) - * bank use = readwrite-> 0b...........11................... - * seq. fill = targ.frst-> 0b.............0.................. - * early RAS = disabled -> 0b..............0................. - * bus width = 32bit -> 0b...............10............... - * adr mux = internal -> 0b.................0.............. - * RAS to CAS= 2 clocks -> 0b..................1............. - * Alt. Rfrsh= normal -> 0b...................0............ - * page mode = enabled -> 0b....................1........... - * first wait= 1 clocks -> 0b.....................01......... - * burst wait= 1 clocks -> 0b.......................01....... - * precharge = 1 clocks -> 0b.........................0...... - * RAS Rfrsh = 2 clocks -> 0b..........................1..... - * Rfrsh Itvl= 512 clks -> 0b...........................1000. - * ram type = DRAM -> 0b...............................0 - * value 0b00000100010110010010101010110000 - * 0x 0 4 5 9 2 A B 0 - */ - lis r2,0x0459 - ori r2,r2,0x2AB0 - mtdcr br6,r2 /* write to DCR BR6*/ - - lis r2,0x0040 /* start address = 0x00400000 */ - lis r3,0x0040 /* size 4 MB = 0x00400000 */ - bl ramacc /* test memory accessibility */ - cmpi 0,0,r4,0 /* memory ok? else test smaller size */ - beq ramcfgok /* ok, we found configuration... +/ - - lis r2,0x0000 /* disable BR6, config not ok */ - mtdcr br6,r2 /* write to DCR BR6*/ - b ramcfgok /* and finish configuration */ - -ramcfgok: - /*-------------------------------------------------------------------- - * init the DRAM where STACK+ DATA+ BBS will be placed. If this is OK - * we will return here. - *-------------------------------------------------------------------*/ - bl rom2ram - - /* clear caches */ - addi r2,0,PPC_I_CACHE/PPC_CACHE_ALIGNMENT - mtctr r2 /* count the loops needed... */ - xor r2,r2,r2 /* start at adr zero */ -icinvlp: - iccci 0,r2 - addi r2,r2,PPC_CACHE_ALIGNMENT - bdnz icinvlp - - addi r2,r0,PPC_D_CACHE/PPC_CACHE_ALIGNMENT - mtctr r2 /* count the loops needed... */ - xor r2,r2,r2 /* start at adr 0 */ -dcinvlp: - dccci 0,r2 - addi r2,r2,PPC_CACHE_ALIGNMENT - bdnz dcinvlp - /*-------------------------------------------------------------------- - * Enable two 128MB cachable regions. - * FEPROM is cachable at 0xFFF00000..0xFFFFFFFF - * DRAM is cachable at 0x00000000..0x00FFFFFF - * FEPROM is noncachable at 0x7FF00000..0x7FFFFFFF - * DRAM is noncachable at 0x80000000..0x80FFFFFF - *-------------------------------------------------------------------*/ - addis r2,r0,0x8000 - addi r2,r2,0x0001 - - mtspr iccr, r2 /* ICCR */ - mtspr dccr, r2 /* DCCR */ - - .extern SYM(__vectors) - - lis r2,__vectors@h /* set EVPR exc. vector prefix */ - mtspr evpr,r2 - - lis r2,0x0000 - ori r2,r2,0x0000 - mtmsr r2 /* set default msr */ - lis r2,0x0000 /* do not allow critical IRQ */ - ori r2,r2,0x0000 - mtdcr exier, r2 /* disable all external IRQs */ - - addi r2,r0,-1 /* r2 = 0xffffffff */ - mtdcr exisr, r2 /* clear all pendingdisable IRQs */ - - /*-------------------------------------------------------------------- - * C_setup. - *-------------------------------------------------------------------*/ - - lwz r2,toc_pointer-base_addr(r1) /* set r2 to toc */ - lwz r1,stack_top-base_addr(r1) /* set r1 to stack_top */ - - addi r1,r1,-56 /* start stack at data_addr - 56 */ - addi r3,r0,0x0 /* clear r3 */ - stw r3, 0(r1) /* Clear stack chain */ - stw r3, 4(r1) - stw r3, 8(r1) - stw r3, 12(r1) - .extern SYM (boot_card) - b SYM (boot_card) /* call the first C routine */ - -/*---------------------------------------------------------------------------- - * Rom2ram. - *---------------------------------------------------------------------------*/ -rom2ram: - lwz r2,copy_dest-base_addr(r1) /* start of data set by loader */ - lwz r3,copy_length-base_addr(r1) /* data length */ - rlwinm r3,r3,30,0x3FFFFFFF /* form length/4 */ - mtctr r3 /* set ctr reg */ - /*-------------------------------------------------------------------- - * Calculate offset of data in image. - *-------------------------------------------------------------------*/ - lwz r4,copy_src-base_addr(r1) /* get start of copy area */ -move_data: - lswi r6,r4,0x4 /* load r6 */ - stswi r6,r2,0x4 /* store r6 */ - addi r4,r4,0x4 /* update r4 */ - addi r2,r2,0x4 /* update r2 */ - bdnz move_data /* decrement counter and loop */ - /*-------------------------------------------------------------------- - * Data move finished, zero out bss. - *-------------------------------------------------------------------*/ - lwz r2,bss_addr-base_addr(r1) /* start of bss set by loader */ - lwz r3,bss_length-base_addr(r1) /* bss length */ - rlwinm. r3,r3,30,0x3FFFFFFF /* form length/4 */ - beqlr /* no bss */ - mtctr r3 /* set ctr reg */ - xor r6,r6,r6 /* r6 = 0 */ -clear_bss: - stswi r6,r2,0x4 /* store r6 */ - addi r2,r2,0x4 /* update r2 */ - bdnz clear_bss /* decrement counter and loop */ - blr /* return */ - -/*---------------------------------------------------------------------------- - * ramacc test accessibility of RAM - * input: r2 = start address, r3 = length (in byte) - * output: r4 = 0 -> ok, !=0 -> fail - *---------------------------------------------------------------------------*/ -ramacc: - xor r4,r4,r4 /* r4 = 0 */ - stw r4,0(r2) /* init ram at start address */ - addi r4,r0,0x04 /* set start shift */ -ramaccf1: - cmp 0,0,r4,r3 /* compare with length */ - bge ramaccfx /* r4 >= r3? then finished */ - add r5,r4,r2 /* get next address to fill */ - stw r4,0(r5) /* store new pattern */ - add r4,r4,r4 /* r4 = r4*2 */ - b ramaccf1 /* and then next loop */ - -ramaccfx: - lwz r4,0(r2) /* get memory at start adr */ - blr - - -#if PPC_ABI == PPC_ABI_POWEROPEN - DESCRIPTOR (startup) -#endif - - - diff --git a/c/src/lib/libbsp/powerpc/papyrus/dlentry/Makefile.in b/c/src/lib/libbsp/powerpc/papyrus/dlentry/Makefile.in index dc40c405f6..5ecb9eaef8 100644 --- a/c/src/lib/libbsp/powerpc/papyrus/dlentry/Makefile.in +++ b/c/src/lib/libbsp/powerpc/papyrus/dlentry/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=dlentry -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/powerpc/papyrus/dlentry/dlentry.S b/c/src/lib/libbsp/powerpc/papyrus/dlentry/dlentry.S new file mode 100644 index 0000000000..b1e1f3a11b --- /dev/null +++ b/c/src/lib/libbsp/powerpc/papyrus/dlentry/dlentry.S @@ -0,0 +1,251 @@ +/* dlentry.s 1.0 - 95/08/08 + * + * This file contains the entry veneer for RTEMS programs + * downloaded to Papyrus. + * + * Author: Andrew Bray + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * $Id$ + */ + +#include "asm.h" + +/* + * The Papyrus ELF link scripts support three special sections: + * .entry The actual entry point, this must contain less + * than 256 bytes of code/data to fit below the + * .vectors section. This always preceeds any other + * code or data. + * .vectors The section containing the interrupt entry veneers. + * .entry2 Any code overflowing from .entry + * .descriptors The PowerOpen function indirection blocks. + */ + +/* + * Downloaded code loads the vectors separately to 0x00000100, + * so .entry can be over 256 bytes. + * + * The other sections are linked in the following order: + * .entry + * .entry2 + * .text + * .descriptors + * .data + * .bss + * usually starting from 0x00020000. + * + * The initial stack is set to run BELOW the code base address. + * + * All the entry veneer has to do is to clear the BSS. + */ + +/* + * GDB likes to have debugging information for the entry veneer. + * Here is some DWARF information. + */ + +#if PPC_ASM == PPC_ASM_ELF + .section .entry,"ax",@progbits +.L_text_b: +.L_LC1: + .previous + +.section .debug_sfnames +.L_sfnames_b: + .byte "/home/andy/powerpc/rtems-3.2.0/c/src/lib/libcpu/ppc/ppc403/dlentry/" + .byte 0 +.L_F0: + .byte "dlentry.s" + .byte 0 + .previous + +.section .line +.L_line_b: + .4byte .L_line_e-.L_line_b + .4byte .L_text_b +.L_LE1: +.L_line_last: + .4byte 0x0 + .2byte 0xffff + .4byte .L_text_e-.L_text_b +.L_line_e: + .previous + +.section .debug_srcinfo +.L_srcinfo_b: + .4byte .L_line_b + .4byte .L_sfnames_b + .4byte .L_text_b + .4byte .L_text_e + .4byte 0xffffffff + .4byte .L_LE1-.L_line_b + .4byte .L_F0-.L_sfnames_b + .4byte .L_line_last-.L_line_b + .4byte 0xffffffff + .previous + +.section .debug_pubnames + .4byte .L_debug_b + .4byte .L_P0 + .byte "download_entry" + .byte 0 + .4byte 0x0 + .byte 0 + .previous + +.section .debug_aranges + .4byte .L_debug_b + .4byte .L_text_b + .4byte .L_text_e-.L_text_b + .4byte 0 + .4byte 0 + .4byte 0 + .4byte 0 + .4byte 0 + .4byte 0 + .4byte 0x0 + .4byte 0x0 + .previous + +.section .debug +.L_debug_b: +.L_D1: + .4byte .L_D1_e-.L_D1 + .2byte 0x11 /* TAG_compile_unit */ + .2byte 0x12 /* AT_sibling */ + .4byte .L_D2 + .2byte 0x38 /* AT_name */ + .byte "dlentry.s" + .byte 0 + .2byte 0x258 /* AT_producer */ + .byte "GAS 2.5.2" + .byte 0 + .2byte 0x111 /* AT_low_pc */ + .4byte .L_text_b + .2byte 0x121 /* AT_high_pc */ + .4byte .L_text_e + .2byte 0x106 /* AT_stmt_list */ + .4byte .L_line_b + .2byte 0x1b8 /* AT_comp_dir */ + .byte "/home/andy/powerpc/rtems-3.2.0/c/src/lib/libcpu/ppc/ppc403/dlentry/" + .byte 0 + .2byte 0x8006 /* AT_sf_names */ + .4byte .L_sfnames_b + .2byte 0x8016 /* AT_src_info */ + .4byte .L_srcinfo_b +.L_D1_e: +.L_P0: +.L_D3: + .4byte .L_D3_e-.L_D3 + .2byte 0x6 /* TAG_global_subroutine */ + .2byte 0x12 /* AT_sibling */ + .4byte .L_D4 + .2byte 0x38 /* AT_name */ + .byte "download_entry" + .byte 0 + .2byte 0x278 /* AT_prototyped */ + .byte 0 + .2byte 0x111 /* AT_low_pc */ + .4byte .L_text_b + .2byte 0x121 /* AT_high_pc */ + .4byte .L_text_e + .2byte 0x8041 /* AT_body_begin */ + .4byte .L_text_b + .2byte 0x8051 /* AT_body_end */ + .4byte .L_text_e +.L_D3_e: + +.L_D4: + .4byte .L_D4_e-.L_D4 + .align 2 +.L_D4_e: +.L_D2: + .previous +#endif + +/*------------------------------------------------------------------------------- + * ROM Vector area. + *------------------------------------------------------------------------------*/ +#if PPC_ASM == PPC_ASM_ELF + .section .entry +#else + .csect .text[PR] +#endif + + PUBLIC_VAR (download_entry) +SYM(download_entry): + bl .startup +base_addr: + +/*------------------------------------------------------------------------------- + * Parameters from linker + *------------------------------------------------------------------------------*/ +toc_pointer: +#if PPC_ASM == PPC_ASM_ELF + .long s.got +#else + .long TOC[tc0] +#endif +bss_length: + .long bss.size +bss_addr: + .long bss.start +/*------------------------------------------------------------------------------- + * Reset_entry. + *------------------------------------------------------------------------------*/ +.startup: + /* Get start address, stack grows down from here... */ + mflr r1 + + /* Assume Bank regs set up..., cache etc. */ + bl bssclr + + /*----------------------------------------------------------------------- + * C_setup. + *----------------------------------------------------------------------*/ + lwz r2,toc_pointer-base_addr(r1) /* set r2 to toc */ + addi r1,r1,-56-4 /* start stack at text_addr - 56 */ + addi r3,r0,0x0 /* clear r3 */ + stw r3, 0(r1) /* Clear stack chain */ + stw r3, 4(r1) + stw r3, 8(r1) + stw r3, 12(r1) + .extern SYM (boot_card) + b SYM (boot_card) /* call the first C routine */ + +/*------------------------------------------------------------------------------- + * bssclr. + *------------------------------------------------------------------------------*/ +bssclr: + /*----------------------------------------------------------------------- + * Data move finished, zero out bss. + *----------------------------------------------------------------------*/ + lwz r2,bss_addr-base_addr(r1) /* start of bss set by loader */ + lwz r3,bss_length-base_addr(r1) /* bss length */ + rlwinm. r3,r3,30,0x3FFFFFFF /* form length/4 */ + beqlr /* no bss */ + mtctr r3 /* set ctr reg */ + xor r6,r6,r6 /* r6 = 0 */ +clear_bss: + stswi r6,r2,0x4 /* store r6 */ + addi r3,r2,0x4 /* update r2 */ + bdnz clear_bss /* decrement counter and loop */ + blr /* return */ +.L_text_e: + +#if PPC_ABI == PPC_ABI_POWEROPEN + DESCRIPTOR (startup) +#endif diff --git a/c/src/lib/libbsp/powerpc/papyrus/dlentry/dlentry.s b/c/src/lib/libbsp/powerpc/papyrus/dlentry/dlentry.s deleted file mode 100644 index b1e1f3a11b..0000000000 --- a/c/src/lib/libbsp/powerpc/papyrus/dlentry/dlentry.s +++ /dev/null @@ -1,251 +0,0 @@ -/* dlentry.s 1.0 - 95/08/08 - * - * This file contains the entry veneer for RTEMS programs - * downloaded to Papyrus. - * - * Author: Andrew Bray - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * $Id$ - */ - -#include "asm.h" - -/* - * The Papyrus ELF link scripts support three special sections: - * .entry The actual entry point, this must contain less - * than 256 bytes of code/data to fit below the - * .vectors section. This always preceeds any other - * code or data. - * .vectors The section containing the interrupt entry veneers. - * .entry2 Any code overflowing from .entry - * .descriptors The PowerOpen function indirection blocks. - */ - -/* - * Downloaded code loads the vectors separately to 0x00000100, - * so .entry can be over 256 bytes. - * - * The other sections are linked in the following order: - * .entry - * .entry2 - * .text - * .descriptors - * .data - * .bss - * usually starting from 0x00020000. - * - * The initial stack is set to run BELOW the code base address. - * - * All the entry veneer has to do is to clear the BSS. - */ - -/* - * GDB likes to have debugging information for the entry veneer. - * Here is some DWARF information. - */ - -#if PPC_ASM == PPC_ASM_ELF - .section .entry,"ax",@progbits -.L_text_b: -.L_LC1: - .previous - -.section .debug_sfnames -.L_sfnames_b: - .byte "/home/andy/powerpc/rtems-3.2.0/c/src/lib/libcpu/ppc/ppc403/dlentry/" - .byte 0 -.L_F0: - .byte "dlentry.s" - .byte 0 - .previous - -.section .line -.L_line_b: - .4byte .L_line_e-.L_line_b - .4byte .L_text_b -.L_LE1: -.L_line_last: - .4byte 0x0 - .2byte 0xffff - .4byte .L_text_e-.L_text_b -.L_line_e: - .previous - -.section .debug_srcinfo -.L_srcinfo_b: - .4byte .L_line_b - .4byte .L_sfnames_b - .4byte .L_text_b - .4byte .L_text_e - .4byte 0xffffffff - .4byte .L_LE1-.L_line_b - .4byte .L_F0-.L_sfnames_b - .4byte .L_line_last-.L_line_b - .4byte 0xffffffff - .previous - -.section .debug_pubnames - .4byte .L_debug_b - .4byte .L_P0 - .byte "download_entry" - .byte 0 - .4byte 0x0 - .byte 0 - .previous - -.section .debug_aranges - .4byte .L_debug_b - .4byte .L_text_b - .4byte .L_text_e-.L_text_b - .4byte 0 - .4byte 0 - .4byte 0 - .4byte 0 - .4byte 0 - .4byte 0 - .4byte 0x0 - .4byte 0x0 - .previous - -.section .debug -.L_debug_b: -.L_D1: - .4byte .L_D1_e-.L_D1 - .2byte 0x11 /* TAG_compile_unit */ - .2byte 0x12 /* AT_sibling */ - .4byte .L_D2 - .2byte 0x38 /* AT_name */ - .byte "dlentry.s" - .byte 0 - .2byte 0x258 /* AT_producer */ - .byte "GAS 2.5.2" - .byte 0 - .2byte 0x111 /* AT_low_pc */ - .4byte .L_text_b - .2byte 0x121 /* AT_high_pc */ - .4byte .L_text_e - .2byte 0x106 /* AT_stmt_list */ - .4byte .L_line_b - .2byte 0x1b8 /* AT_comp_dir */ - .byte "/home/andy/powerpc/rtems-3.2.0/c/src/lib/libcpu/ppc/ppc403/dlentry/" - .byte 0 - .2byte 0x8006 /* AT_sf_names */ - .4byte .L_sfnames_b - .2byte 0x8016 /* AT_src_info */ - .4byte .L_srcinfo_b -.L_D1_e: -.L_P0: -.L_D3: - .4byte .L_D3_e-.L_D3 - .2byte 0x6 /* TAG_global_subroutine */ - .2byte 0x12 /* AT_sibling */ - .4byte .L_D4 - .2byte 0x38 /* AT_name */ - .byte "download_entry" - .byte 0 - .2byte 0x278 /* AT_prototyped */ - .byte 0 - .2byte 0x111 /* AT_low_pc */ - .4byte .L_text_b - .2byte 0x121 /* AT_high_pc */ - .4byte .L_text_e - .2byte 0x8041 /* AT_body_begin */ - .4byte .L_text_b - .2byte 0x8051 /* AT_body_end */ - .4byte .L_text_e -.L_D3_e: - -.L_D4: - .4byte .L_D4_e-.L_D4 - .align 2 -.L_D4_e: -.L_D2: - .previous -#endif - -/*------------------------------------------------------------------------------- - * ROM Vector area. - *------------------------------------------------------------------------------*/ -#if PPC_ASM == PPC_ASM_ELF - .section .entry -#else - .csect .text[PR] -#endif - - PUBLIC_VAR (download_entry) -SYM(download_entry): - bl .startup -base_addr: - -/*------------------------------------------------------------------------------- - * Parameters from linker - *------------------------------------------------------------------------------*/ -toc_pointer: -#if PPC_ASM == PPC_ASM_ELF - .long s.got -#else - .long TOC[tc0] -#endif -bss_length: - .long bss.size -bss_addr: - .long bss.start -/*------------------------------------------------------------------------------- - * Reset_entry. - *------------------------------------------------------------------------------*/ -.startup: - /* Get start address, stack grows down from here... */ - mflr r1 - - /* Assume Bank regs set up..., cache etc. */ - bl bssclr - - /*----------------------------------------------------------------------- - * C_setup. - *----------------------------------------------------------------------*/ - lwz r2,toc_pointer-base_addr(r1) /* set r2 to toc */ - addi r1,r1,-56-4 /* start stack at text_addr - 56 */ - addi r3,r0,0x0 /* clear r3 */ - stw r3, 0(r1) /* Clear stack chain */ - stw r3, 4(r1) - stw r3, 8(r1) - stw r3, 12(r1) - .extern SYM (boot_card) - b SYM (boot_card) /* call the first C routine */ - -/*------------------------------------------------------------------------------- - * bssclr. - *------------------------------------------------------------------------------*/ -bssclr: - /*----------------------------------------------------------------------- - * Data move finished, zero out bss. - *----------------------------------------------------------------------*/ - lwz r2,bss_addr-base_addr(r1) /* start of bss set by loader */ - lwz r3,bss_length-base_addr(r1) /* bss length */ - rlwinm. r3,r3,30,0x3FFFFFFF /* form length/4 */ - beqlr /* no bss */ - mtctr r3 /* set ctr reg */ - xor r6,r6,r6 /* r6 = 0 */ -clear_bss: - stswi r6,r2,0x4 /* store r6 */ - addi r3,r2,0x4 /* update r2 */ - bdnz clear_bss /* decrement counter and loop */ - blr /* return */ -.L_text_e: - -#if PPC_ABI == PPC_ABI_POWEROPEN - DESCRIPTOR (startup) -#endif diff --git a/c/src/lib/libbsp/powerpc/papyrus/flashentry/Makefile.in b/c/src/lib/libbsp/powerpc/papyrus/flashentry/Makefile.in index 683f996472..b56cce2ea8 100644 --- a/c/src/lib/libbsp/powerpc/papyrus/flashentry/Makefile.in +++ b/c/src/lib/libbsp/powerpc/papyrus/flashentry/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=flashentry -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/powerpc/papyrus/flashentry/flashentry.S b/c/src/lib/libbsp/powerpc/papyrus/flashentry/flashentry.S new file mode 100644 index 0000000000..857caa729d --- /dev/null +++ b/c/src/lib/libbsp/powerpc/papyrus/flashentry/flashentry.S @@ -0,0 +1,289 @@ +/* dlentry.s 1.0 - 95/08/08 + * + * This file contains the entry veneer for RTEMS programs + * stored in Papyrus' flash ROM. + * + * Author: Andrew Bray + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * $Id$ + */ + +#include "asm.h" + +/* + * The Papyrus ELF link scripts support three special sections: + * .entry The actual entry point, this must contain less + * than 256 bytes of code/data to fit below the + * .vectors section. This always preceeds any other + * code or data. + * .vectors The section containing the interrupt entry veneers. + * .entry2 Any code overflowing from .entry + * .descriptors The PowerOpen function indirection blocks. + */ + +/* + * Flash sections are linked in the following order: + * .entry + * .vectors + * .entry2 + * .text + * .descriptors + * .data + * .bss + * usually starting from 0xFFF00000. + * + * The initial stack is set to run BELOW the final location of + * the initialised data. + * + * All the entry veneer has to do is to copy the initialised data + * to its final location and clear the BSS. + */ + +/* + * GDB likes to have debugging information for the entry veneer. + * Here is some DWARF information. + */ + +#if PPC_ASM == PPC_ASM_ELF + .section .entry,"ax",@progbits +.L_text_b: +.L_LC1: + .previous + +.section .debug_sfnames +.L_sfnames_b: + .byte "/home/andy/powerpc/rtems-3.2.0/c/src/lib/libcpu/ppc/ppc403/flashentry/" + .byte 0 +.L_F0: + .byte "flashentry.s" + .byte 0 + .previous + +.section .line +.L_line_b: + .4byte .L_line_e-.L_line_b + .4byte .L_text_b +.L_LE1: +.L_line_last: + .4byte 0x0 + .2byte 0xffff + .4byte .L_text_e-.L_text_b +.L_line_e: + .previous + +.section .debug_srcinfo +.L_srcinfo_b: + .4byte .L_line_b + .4byte .L_sfnames_b + .4byte .L_text_b + .4byte .L_text_e + .4byte 0xffffffff + .4byte .L_LE1-.L_line_b + .4byte .L_F0-.L_sfnames_b + .4byte .L_line_last-.L_line_b + .4byte 0xffffffff + .previous + +.section .debug_pubnames + .4byte .L_debug_b + .4byte .L_P0 + .byte "flash_entry" + .byte 0 + .4byte 0x0 + .byte 0 + .previous + +.section .debug_aranges + .4byte .L_debug_b + .4byte .L_text_b + .4byte .L_text_e-.L_text_b + .4byte 0 + .4byte 0 + .4byte 0 + .4byte 0 + .4byte 0 + .4byte 0 + .4byte 0x0 + .4byte 0x0 + .previous + +.section .debug +.L_debug_b: +.L_D1: + .4byte .L_D1_e-.L_D1 + .2byte 0x11 /* TAG_compile_unit */ + .2byte 0x12 /* AT_sibling */ + .4byte .L_D2 + .2byte 0x38 /* AT_name */ + .byte "flashentry.s" + .byte 0 + .2byte 0x258 /* AT_producer */ + .byte "GAS 2.5.2" + .byte 0 + .2byte 0x111 /* AT_low_pc */ + .4byte .L_text_b + .2byte 0x121 /* AT_high_pc */ + .4byte .L_text_e + .2byte 0x106 /* AT_stmt_list */ + .4byte .L_line_b + .2byte 0x1b8 /* AT_comp_dir */ + .byte "/home/andy/powerpc/rtems-3.2.0/c/src/lib/libcpu/ppc/ppc403/dlentry/" + .byte 0 + .2byte 0x8006 /* AT_sf_names */ + .4byte .L_sfnames_b + .2byte 0x8016 /* AT_src_info */ + .4byte .L_srcinfo_b +.L_D1_e: +.L_P0: +.L_D3: + .4byte .L_D3_e-.L_D3 + .2byte 0x6 /* TAG_global_subroutine */ + .2byte 0x12 /* AT_sibling */ + .4byte .L_D4 + .2byte 0x38 /* AT_name */ + .byte "flash_entry" + .byte 0 + .2byte 0x278 /* AT_prototyped */ + .byte 0 + .2byte 0x111 /* AT_low_pc */ + .4byte .L_text_b + .2byte 0x121 /* AT_high_pc */ + .4byte .L_text_e + .2byte 0x8041 /* AT_body_begin */ + .4byte .L_text_b + .2byte 0x8051 /* AT_body_end */ + .4byte .L_text_e +.L_D3_e: + +.L_D4: + .4byte .L_D4_e-.L_D4 + .align 2 +.L_D4_e: +.L_D2: + .previous +#endif + +/*------------------------------------------------------------------------------- + * ROM Vector area. + *------------------------------------------------------------------------------*/ +#if PPC_ASM == PPC_ASM_ELF + .section .entry +#else + .csect .text[PR] +#endif + PUBLIC_VAR (flash_entry) +SYM (flash_entry): + bl .startup +base_addr: + +/*------------------------------------------------------------------------------- + * Parameters from linker + *------------------------------------------------------------------------------*/ +toc_pointer: +#if PPC_ASM == PPC_ASM_ELF + .long s.got +#else + .long TOC[tc0] +#endif +text_length: + .long t.size +text_addr: + .long t.start +data_length: + .long copy.size +data_addr: + .long copy.dest +bss_length: + .long bss.size +bss_addr: + .long bss.start + +/*------------------------------------------------------------------------------- + * Reset_entry. + *------------------------------------------------------------------------------*/ +.startup: + /* Get start address */ + mflr r1 + + /* Assume Bank regs set up..., cache etc. */ + + /*----------------------------------------------------------------------- + * Check the DRAM where STACK+ DATA+ BBS will be placed. If this is OK + * we will return here. + *----------------------------------------------------------------------*/ + bl rom2ram + /*----------------------------------------------------------------------- + * Enable two 128MB cachable regions. + *----------------------------------------------------------------------*/ + addis r2,r0,0x8000 + addi r2,r2,0x0001 + + mtspr 0x3fb, r2 /* ICCR */ + mtspr 0x3fa, r2 /* DCCR */ + + /*----------------------------------------------------------------------- + * C_setup. + *----------------------------------------------------------------------*/ + lwz r2,toc_pointer-base_addr(r1) /* set r2 to toc */ + lwz r1,data_addr-base_addr(r1) /* set r1 to data_addr */ + addi r1,r1,-56 /* start stack at data_addr - 56 */ + addi r3,r0,0x0 /* clear r3 */ + stw r3, 0(r1) /* Clear stack chain */ + stw r3, 4(r1) + stw r3, 8(r1) + stw r3, 12(r1) + .extern SYM (boot_card) + b SYM (boot_card) /* call the first C routine */ + +/*------------------------------------------------------------------------------- + * Rom2ram. + *------------------------------------------------------------------------------*/ +rom2ram: + lwz r2,data_addr-base_addr(r1) /* start of data set by loader */ + lwz r3,data_length-base_addr(r1) /* data length */ + rlwinm r3,r3,30,0x3FFFFFFF /* form length/4 */ + mtctr r3 /* set ctr reg */ + /*----------------------------------------------------------------------- + * Calculate offset of data in image. + *----------------------------------------------------------------------*/ + lwz r5,text_length-base_addr(r1) /* get text length */ + lwz r4,text_addr-base_addr(r1) /* get text length */ + add r4,r4,r5 /* r4 = data pointer */ +move_data: + lswi r6,r4,0x4 /* load r6 */ + stswi r6,r2,0x4 /* store r6 */ + addi r4,r4,0x4 /* update r4 */ + addi r2,r2,0x4 /* update r2 */ + bdnz move_data /* decrement counter and loop */ + /*----------------------------------------------------------------------- + * Data move finished, zero out bss. + *----------------------------------------------------------------------*/ + lwz r2,bss_addr-base_addr(r1) /* start of bss set by loader */ + lwz r3,bss_length-base_addr(r1) /* bss length */ + rlwinm. r3,r3,30,0x3FFFFFFF /* form length/4 */ + beqlr /* no bss */ + mtctr r3 /* set ctr reg */ + xor r6,r6,r6 /* r6 = 0 */ +clear_bss: + stswi r6,r2,0x4 /* store r6 */ + addi r3,r2,0x4 /* update r2 */ + bdnz clear_bss /* decrement counter and loop */ + blr /* return */ +.L_text_e: + +#if PPC_ABI == PPC_ABI_POWEROPEN + DESCRIPTOR (startup) +#endif diff --git a/c/src/lib/libbsp/powerpc/papyrus/flashentry/flashentry.s b/c/src/lib/libbsp/powerpc/papyrus/flashentry/flashentry.s deleted file mode 100644 index 857caa729d..0000000000 --- a/c/src/lib/libbsp/powerpc/papyrus/flashentry/flashentry.s +++ /dev/null @@ -1,289 +0,0 @@ -/* dlentry.s 1.0 - 95/08/08 - * - * This file contains the entry veneer for RTEMS programs - * stored in Papyrus' flash ROM. - * - * Author: Andrew Bray - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * $Id$ - */ - -#include "asm.h" - -/* - * The Papyrus ELF link scripts support three special sections: - * .entry The actual entry point, this must contain less - * than 256 bytes of code/data to fit below the - * .vectors section. This always preceeds any other - * code or data. - * .vectors The section containing the interrupt entry veneers. - * .entry2 Any code overflowing from .entry - * .descriptors The PowerOpen function indirection blocks. - */ - -/* - * Flash sections are linked in the following order: - * .entry - * .vectors - * .entry2 - * .text - * .descriptors - * .data - * .bss - * usually starting from 0xFFF00000. - * - * The initial stack is set to run BELOW the final location of - * the initialised data. - * - * All the entry veneer has to do is to copy the initialised data - * to its final location and clear the BSS. - */ - -/* - * GDB likes to have debugging information for the entry veneer. - * Here is some DWARF information. - */ - -#if PPC_ASM == PPC_ASM_ELF - .section .entry,"ax",@progbits -.L_text_b: -.L_LC1: - .previous - -.section .debug_sfnames -.L_sfnames_b: - .byte "/home/andy/powerpc/rtems-3.2.0/c/src/lib/libcpu/ppc/ppc403/flashentry/" - .byte 0 -.L_F0: - .byte "flashentry.s" - .byte 0 - .previous - -.section .line -.L_line_b: - .4byte .L_line_e-.L_line_b - .4byte .L_text_b -.L_LE1: -.L_line_last: - .4byte 0x0 - .2byte 0xffff - .4byte .L_text_e-.L_text_b -.L_line_e: - .previous - -.section .debug_srcinfo -.L_srcinfo_b: - .4byte .L_line_b - .4byte .L_sfnames_b - .4byte .L_text_b - .4byte .L_text_e - .4byte 0xffffffff - .4byte .L_LE1-.L_line_b - .4byte .L_F0-.L_sfnames_b - .4byte .L_line_last-.L_line_b - .4byte 0xffffffff - .previous - -.section .debug_pubnames - .4byte .L_debug_b - .4byte .L_P0 - .byte "flash_entry" - .byte 0 - .4byte 0x0 - .byte 0 - .previous - -.section .debug_aranges - .4byte .L_debug_b - .4byte .L_text_b - .4byte .L_text_e-.L_text_b - .4byte 0 - .4byte 0 - .4byte 0 - .4byte 0 - .4byte 0 - .4byte 0 - .4byte 0x0 - .4byte 0x0 - .previous - -.section .debug -.L_debug_b: -.L_D1: - .4byte .L_D1_e-.L_D1 - .2byte 0x11 /* TAG_compile_unit */ - .2byte 0x12 /* AT_sibling */ - .4byte .L_D2 - .2byte 0x38 /* AT_name */ - .byte "flashentry.s" - .byte 0 - .2byte 0x258 /* AT_producer */ - .byte "GAS 2.5.2" - .byte 0 - .2byte 0x111 /* AT_low_pc */ - .4byte .L_text_b - .2byte 0x121 /* AT_high_pc */ - .4byte .L_text_e - .2byte 0x106 /* AT_stmt_list */ - .4byte .L_line_b - .2byte 0x1b8 /* AT_comp_dir */ - .byte "/home/andy/powerpc/rtems-3.2.0/c/src/lib/libcpu/ppc/ppc403/dlentry/" - .byte 0 - .2byte 0x8006 /* AT_sf_names */ - .4byte .L_sfnames_b - .2byte 0x8016 /* AT_src_info */ - .4byte .L_srcinfo_b -.L_D1_e: -.L_P0: -.L_D3: - .4byte .L_D3_e-.L_D3 - .2byte 0x6 /* TAG_global_subroutine */ - .2byte 0x12 /* AT_sibling */ - .4byte .L_D4 - .2byte 0x38 /* AT_name */ - .byte "flash_entry" - .byte 0 - .2byte 0x278 /* AT_prototyped */ - .byte 0 - .2byte 0x111 /* AT_low_pc */ - .4byte .L_text_b - .2byte 0x121 /* AT_high_pc */ - .4byte .L_text_e - .2byte 0x8041 /* AT_body_begin */ - .4byte .L_text_b - .2byte 0x8051 /* AT_body_end */ - .4byte .L_text_e -.L_D3_e: - -.L_D4: - .4byte .L_D4_e-.L_D4 - .align 2 -.L_D4_e: -.L_D2: - .previous -#endif - -/*------------------------------------------------------------------------------- - * ROM Vector area. - *------------------------------------------------------------------------------*/ -#if PPC_ASM == PPC_ASM_ELF - .section .entry -#else - .csect .text[PR] -#endif - PUBLIC_VAR (flash_entry) -SYM (flash_entry): - bl .startup -base_addr: - -/*------------------------------------------------------------------------------- - * Parameters from linker - *------------------------------------------------------------------------------*/ -toc_pointer: -#if PPC_ASM == PPC_ASM_ELF - .long s.got -#else - .long TOC[tc0] -#endif -text_length: - .long t.size -text_addr: - .long t.start -data_length: - .long copy.size -data_addr: - .long copy.dest -bss_length: - .long bss.size -bss_addr: - .long bss.start - -/*------------------------------------------------------------------------------- - * Reset_entry. - *------------------------------------------------------------------------------*/ -.startup: - /* Get start address */ - mflr r1 - - /* Assume Bank regs set up..., cache etc. */ - - /*----------------------------------------------------------------------- - * Check the DRAM where STACK+ DATA+ BBS will be placed. If this is OK - * we will return here. - *----------------------------------------------------------------------*/ - bl rom2ram - /*----------------------------------------------------------------------- - * Enable two 128MB cachable regions. - *----------------------------------------------------------------------*/ - addis r2,r0,0x8000 - addi r2,r2,0x0001 - - mtspr 0x3fb, r2 /* ICCR */ - mtspr 0x3fa, r2 /* DCCR */ - - /*----------------------------------------------------------------------- - * C_setup. - *----------------------------------------------------------------------*/ - lwz r2,toc_pointer-base_addr(r1) /* set r2 to toc */ - lwz r1,data_addr-base_addr(r1) /* set r1 to data_addr */ - addi r1,r1,-56 /* start stack at data_addr - 56 */ - addi r3,r0,0x0 /* clear r3 */ - stw r3, 0(r1) /* Clear stack chain */ - stw r3, 4(r1) - stw r3, 8(r1) - stw r3, 12(r1) - .extern SYM (boot_card) - b SYM (boot_card) /* call the first C routine */ - -/*------------------------------------------------------------------------------- - * Rom2ram. - *------------------------------------------------------------------------------*/ -rom2ram: - lwz r2,data_addr-base_addr(r1) /* start of data set by loader */ - lwz r3,data_length-base_addr(r1) /* data length */ - rlwinm r3,r3,30,0x3FFFFFFF /* form length/4 */ - mtctr r3 /* set ctr reg */ - /*----------------------------------------------------------------------- - * Calculate offset of data in image. - *----------------------------------------------------------------------*/ - lwz r5,text_length-base_addr(r1) /* get text length */ - lwz r4,text_addr-base_addr(r1) /* get text length */ - add r4,r4,r5 /* r4 = data pointer */ -move_data: - lswi r6,r4,0x4 /* load r6 */ - stswi r6,r2,0x4 /* store r6 */ - addi r4,r4,0x4 /* update r4 */ - addi r2,r2,0x4 /* update r2 */ - bdnz move_data /* decrement counter and loop */ - /*----------------------------------------------------------------------- - * Data move finished, zero out bss. - *----------------------------------------------------------------------*/ - lwz r2,bss_addr-base_addr(r1) /* start of bss set by loader */ - lwz r3,bss_length-base_addr(r1) /* bss length */ - rlwinm. r3,r3,30,0x3FFFFFFF /* form length/4 */ - beqlr /* no bss */ - mtctr r3 /* set ctr reg */ - xor r6,r6,r6 /* r6 = 0 */ -clear_bss: - stswi r6,r2,0x4 /* store r6 */ - addi r3,r2,0x4 /* update r2 */ - bdnz clear_bss /* decrement counter and loop */ - blr /* return */ -.L_text_e: - -#if PPC_ABI == PPC_ABI_POWEROPEN - DESCRIPTOR (startup) -#endif diff --git a/c/src/lib/libbsp/powerpc/psim/clock/Makefile.in b/c/src/lib/libbsp/powerpc/psim/clock/Makefile.in index be0a454963..b2674e2009 100644 --- a/c/src/lib/libbsp/powerpc/psim/clock/Makefile.in +++ b/c/src/lib/libbsp/powerpc/psim/clock/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES= -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/powerpc/psim/console/Makefile.in b/c/src/lib/libbsp/powerpc/psim/console/Makefile.in index 125410e1c6..2ba8603478 100644 --- a/c/src/lib/libbsp/powerpc/psim/console/Makefile.in +++ b/c/src/lib/libbsp/powerpc/psim/console/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=consupp -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/powerpc/psim/console/consupp.S b/c/src/lib/libbsp/powerpc/psim/console/consupp.S new file mode 100644 index 0000000000..bb9e834fc6 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/psim/console/consupp.S @@ -0,0 +1,33 @@ +/* + * Adapted from the mvme-inbyte.S and mvme-outbyte.S files in libgloss. + * These should work on all targets using the ppcbug monitor. + * + * Copyright (c) 1995 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ + +#include "ppc-asm.h" + + .file "support.s" + .text +FUNC_START(outbyte) + li r10,0x20 + sc + blr +FUNC_END(outbyte) + + .text +FUNC_START(inbyte) + li r10,0x0 + sc + blr +FUNC_END(inbyte) diff --git a/c/src/lib/libbsp/powerpc/psim/console/consupp.s b/c/src/lib/libbsp/powerpc/psim/console/consupp.s deleted file mode 100644 index bb9e834fc6..0000000000 --- a/c/src/lib/libbsp/powerpc/psim/console/consupp.s +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Adapted from the mvme-inbyte.S and mvme-outbyte.S files in libgloss. - * These should work on all targets using the ppcbug monitor. - * - * Copyright (c) 1995 Cygnus Support - * - * The authors hereby grant permission to use, copy, modify, distribute, - * and license this software and its documentation for any purpose, provided - * that existing copyright notices are retained in all copies and that this - * notice is included verbatim in any distributions. No written agreement, - * license, or royalty fee is required for any of the authorized uses. - * Modifications to this software may be copyrighted by their authors - * and need not follow the licensing terms described here, provided that - * the new terms are clearly indicated on the first page of each file where - * they apply. - */ - -#include "ppc-asm.h" - - .file "support.s" - .text -FUNC_START(outbyte) - li r10,0x20 - sc - blr -FUNC_END(outbyte) - - .text -FUNC_START(inbyte) - li r10,0x0 - sc - blr -FUNC_END(inbyte) diff --git a/c/src/lib/libbsp/powerpc/psim/start/Makefile.in b/c/src/lib/libbsp/powerpc/psim/start/Makefile.in index 35377e94f1..48d2c854c3 100644 --- a/c/src/lib/libbsp/powerpc/psim/start/Makefile.in +++ b/c/src/lib/libbsp/powerpc/psim/start/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=startsim -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/powerpc/psim/start/start.S b/c/src/lib/libbsp/powerpc/psim/start/start.S new file mode 100644 index 0000000000..f94a3ca330 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/psim/start/start.S @@ -0,0 +1,106 @@ +/* + * This is based on the mvme-crt0.S file from libgloss/rs6000. + * crt0.S -- startup file for PowerPC systems. + * + * Copyright (c) 1995 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + * + * $Id$ + */ + +#include "ppc-asm.h" + + .file "startsim.s" + .section ".got2","aw" + .align 2 + +.LCTOC1 = .+32768 + + .extern FUNC_NAME(atexit) + .globl FUNC_NAME(__atexit) + .section ".sdata","aw" + .align 2 +FUNC_NAME(__atexit): /* tell C's eabi-ctor's we have an atexit function */ + .long FUNC_NAME(atexit)@fixup /* and that it is to register __do_global_dtors */ + + .section ".fixup","aw" + .align 2 + .long FUNC_NAME(__atexit) + + .section ".got2","aw" +.Ltable = .-.LCTOC1 + .long .LCTOC1 /* address we think .LCTOC1 is loaded at */ + +.Lbss_start = .-.LCTOC1 + .long __bss_start + +.Lend = .-.LCTOC1 + .long _end + +.Lstack = .-.LCTOC1 /* stack address if set by user */ + .long __stack + + .text +.Lptr: + .long .LCTOC1-.Laddr + + .globl _start + .type _start,@function +_start: + bl .Laddr /* get current address */ +.Laddr: + mflr r4 /* real address of .Laddr */ + lwz r5,(.Lptr-.Laddr)(r4) /* linker generated address of .LCTOC1 */ + add r5,r5,r4 /* correct to real pointer */ + lwz r4,.Ltable(r5) /* get linker's idea of where .Laddr is */ + subf r4,r4,r5 /* calculate difference between where linked and current */ + + /* clear bss */ + lwz r6,.Lbss_start(r5) /* calculate beginning of the BSS */ + lwz r7,.Lend(r5) /* calculate end of the BSS */ + add r6,r6,r4 /* adjust pointers */ + add r7,r7,r4 + + cmplw 1,r6,r7 + bc 4,4,.Ldone + + subf r8,r6,r7 /* number of bytes to zero */ + srwi r9,r8,2 /* number of words to zero */ + mtctr r9 + li r0,0 /* zero to clear memory */ + addi r6,r6,-4 /* adjust so we can use stwu */ +.Lloop: + stwu r0,4(r6) /* zero bss */ + bdnz .Lloop + +.Ldone: + + lwz r0,.Lstack(r5) /* stack address or 0 */ + cmplwi 1,r0,0 /* equal to 0? */ + bc 12,6,.Lnostack /* use default stack if == 0 */ + mr sp,r0 /* use user defined stack */ + +.Lnostack: + /* set up initial stack frame */ + addi sp,sp,-4 /* make sure we don't overwrite debug mem */ + lis r0,0 + stw r0,0(sp) /* clear back chain */ + stwu sp,-56(sp) /* push another stack frame */ + + /* Let her rip */ + bl FUNC_NAME(boot_card) + + /* return value from boot_card is argument to exit */ + bl FUNC_NAME(exit) + trap +.Lstart: + .size _start,.Lstart-_start diff --git a/c/src/lib/libbsp/powerpc/psim/start/startsim.s b/c/src/lib/libbsp/powerpc/psim/start/startsim.s deleted file mode 100644 index f94a3ca330..0000000000 --- a/c/src/lib/libbsp/powerpc/psim/start/startsim.s +++ /dev/null @@ -1,106 +0,0 @@ -/* - * This is based on the mvme-crt0.S file from libgloss/rs6000. - * crt0.S -- startup file for PowerPC systems. - * - * Copyright (c) 1995 Cygnus Support - * - * The authors hereby grant permission to use, copy, modify, distribute, - * and license this software and its documentation for any purpose, provided - * that existing copyright notices are retained in all copies and that this - * notice is included verbatim in any distributions. No written agreement, - * license, or royalty fee is required for any of the authorized uses. - * Modifications to this software may be copyrighted by their authors - * and need not follow the licensing terms described here, provided that - * the new terms are clearly indicated on the first page of each file where - * they apply. - * - * $Id$ - */ - -#include "ppc-asm.h" - - .file "startsim.s" - .section ".got2","aw" - .align 2 - -.LCTOC1 = .+32768 - - .extern FUNC_NAME(atexit) - .globl FUNC_NAME(__atexit) - .section ".sdata","aw" - .align 2 -FUNC_NAME(__atexit): /* tell C's eabi-ctor's we have an atexit function */ - .long FUNC_NAME(atexit)@fixup /* and that it is to register __do_global_dtors */ - - .section ".fixup","aw" - .align 2 - .long FUNC_NAME(__atexit) - - .section ".got2","aw" -.Ltable = .-.LCTOC1 - .long .LCTOC1 /* address we think .LCTOC1 is loaded at */ - -.Lbss_start = .-.LCTOC1 - .long __bss_start - -.Lend = .-.LCTOC1 - .long _end - -.Lstack = .-.LCTOC1 /* stack address if set by user */ - .long __stack - - .text -.Lptr: - .long .LCTOC1-.Laddr - - .globl _start - .type _start,@function -_start: - bl .Laddr /* get current address */ -.Laddr: - mflr r4 /* real address of .Laddr */ - lwz r5,(.Lptr-.Laddr)(r4) /* linker generated address of .LCTOC1 */ - add r5,r5,r4 /* correct to real pointer */ - lwz r4,.Ltable(r5) /* get linker's idea of where .Laddr is */ - subf r4,r4,r5 /* calculate difference between where linked and current */ - - /* clear bss */ - lwz r6,.Lbss_start(r5) /* calculate beginning of the BSS */ - lwz r7,.Lend(r5) /* calculate end of the BSS */ - add r6,r6,r4 /* adjust pointers */ - add r7,r7,r4 - - cmplw 1,r6,r7 - bc 4,4,.Ldone - - subf r8,r6,r7 /* number of bytes to zero */ - srwi r9,r8,2 /* number of words to zero */ - mtctr r9 - li r0,0 /* zero to clear memory */ - addi r6,r6,-4 /* adjust so we can use stwu */ -.Lloop: - stwu r0,4(r6) /* zero bss */ - bdnz .Lloop - -.Ldone: - - lwz r0,.Lstack(r5) /* stack address or 0 */ - cmplwi 1,r0,0 /* equal to 0? */ - bc 12,6,.Lnostack /* use default stack if == 0 */ - mr sp,r0 /* use user defined stack */ - -.Lnostack: - /* set up initial stack frame */ - addi sp,sp,-4 /* make sure we don't overwrite debug mem */ - lis r0,0 - stw r0,0(sp) /* clear back chain */ - stwu sp,-56(sp) /* push another stack frame */ - - /* Let her rip */ - bl FUNC_NAME(boot_card) - - /* return value from boot_card is argument to exit */ - bl FUNC_NAME(exit) - trap -.Lstart: - .size _start,.Lstart-_start diff --git a/c/src/lib/libbsp/powerpc/psim/startsim/Makefile.in b/c/src/lib/libbsp/powerpc/psim/startsim/Makefile.in index 35377e94f1..48d2c854c3 100644 --- a/c/src/lib/libbsp/powerpc/psim/startsim/Makefile.in +++ b/c/src/lib/libbsp/powerpc/psim/startsim/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=startsim -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/powerpc/psim/startsim/startsim.S b/c/src/lib/libbsp/powerpc/psim/startsim/startsim.S new file mode 100644 index 0000000000..f94a3ca330 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/psim/startsim/startsim.S @@ -0,0 +1,106 @@ +/* + * This is based on the mvme-crt0.S file from libgloss/rs6000. + * crt0.S -- startup file for PowerPC systems. + * + * Copyright (c) 1995 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + * + * $Id$ + */ + +#include "ppc-asm.h" + + .file "startsim.s" + .section ".got2","aw" + .align 2 + +.LCTOC1 = .+32768 + + .extern FUNC_NAME(atexit) + .globl FUNC_NAME(__atexit) + .section ".sdata","aw" + .align 2 +FUNC_NAME(__atexit): /* tell C's eabi-ctor's we have an atexit function */ + .long FUNC_NAME(atexit)@fixup /* and that it is to register __do_global_dtors */ + + .section ".fixup","aw" + .align 2 + .long FUNC_NAME(__atexit) + + .section ".got2","aw" +.Ltable = .-.LCTOC1 + .long .LCTOC1 /* address we think .LCTOC1 is loaded at */ + +.Lbss_start = .-.LCTOC1 + .long __bss_start + +.Lend = .-.LCTOC1 + .long _end + +.Lstack = .-.LCTOC1 /* stack address if set by user */ + .long __stack + + .text +.Lptr: + .long .LCTOC1-.Laddr + + .globl _start + .type _start,@function +_start: + bl .Laddr /* get current address */ +.Laddr: + mflr r4 /* real address of .Laddr */ + lwz r5,(.Lptr-.Laddr)(r4) /* linker generated address of .LCTOC1 */ + add r5,r5,r4 /* correct to real pointer */ + lwz r4,.Ltable(r5) /* get linker's idea of where .Laddr is */ + subf r4,r4,r5 /* calculate difference between where linked and current */ + + /* clear bss */ + lwz r6,.Lbss_start(r5) /* calculate beginning of the BSS */ + lwz r7,.Lend(r5) /* calculate end of the BSS */ + add r6,r6,r4 /* adjust pointers */ + add r7,r7,r4 + + cmplw 1,r6,r7 + bc 4,4,.Ldone + + subf r8,r6,r7 /* number of bytes to zero */ + srwi r9,r8,2 /* number of words to zero */ + mtctr r9 + li r0,0 /* zero to clear memory */ + addi r6,r6,-4 /* adjust so we can use stwu */ +.Lloop: + stwu r0,4(r6) /* zero bss */ + bdnz .Lloop + +.Ldone: + + lwz r0,.Lstack(r5) /* stack address or 0 */ + cmplwi 1,r0,0 /* equal to 0? */ + bc 12,6,.Lnostack /* use default stack if == 0 */ + mr sp,r0 /* use user defined stack */ + +.Lnostack: + /* set up initial stack frame */ + addi sp,sp,-4 /* make sure we don't overwrite debug mem */ + lis r0,0 + stw r0,0(sp) /* clear back chain */ + stwu sp,-56(sp) /* push another stack frame */ + + /* Let her rip */ + bl FUNC_NAME(boot_card) + + /* return value from boot_card is argument to exit */ + bl FUNC_NAME(exit) + trap +.Lstart: + .size _start,.Lstart-_start diff --git a/c/src/lib/libbsp/powerpc/psim/startsim/startsim.s b/c/src/lib/libbsp/powerpc/psim/startsim/startsim.s deleted file mode 100644 index f94a3ca330..0000000000 --- a/c/src/lib/libbsp/powerpc/psim/startsim/startsim.s +++ /dev/null @@ -1,106 +0,0 @@ -/* - * This is based on the mvme-crt0.S file from libgloss/rs6000. - * crt0.S -- startup file for PowerPC systems. - * - * Copyright (c) 1995 Cygnus Support - * - * The authors hereby grant permission to use, copy, modify, distribute, - * and license this software and its documentation for any purpose, provided - * that existing copyright notices are retained in all copies and that this - * notice is included verbatim in any distributions. No written agreement, - * license, or royalty fee is required for any of the authorized uses. - * Modifications to this software may be copyrighted by their authors - * and need not follow the licensing terms described here, provided that - * the new terms are clearly indicated on the first page of each file where - * they apply. - * - * $Id$ - */ - -#include "ppc-asm.h" - - .file "startsim.s" - .section ".got2","aw" - .align 2 - -.LCTOC1 = .+32768 - - .extern FUNC_NAME(atexit) - .globl FUNC_NAME(__atexit) - .section ".sdata","aw" - .align 2 -FUNC_NAME(__atexit): /* tell C's eabi-ctor's we have an atexit function */ - .long FUNC_NAME(atexit)@fixup /* and that it is to register __do_global_dtors */ - - .section ".fixup","aw" - .align 2 - .long FUNC_NAME(__atexit) - - .section ".got2","aw" -.Ltable = .-.LCTOC1 - .long .LCTOC1 /* address we think .LCTOC1 is loaded at */ - -.Lbss_start = .-.LCTOC1 - .long __bss_start - -.Lend = .-.LCTOC1 - .long _end - -.Lstack = .-.LCTOC1 /* stack address if set by user */ - .long __stack - - .text -.Lptr: - .long .LCTOC1-.Laddr - - .globl _start - .type _start,@function -_start: - bl .Laddr /* get current address */ -.Laddr: - mflr r4 /* real address of .Laddr */ - lwz r5,(.Lptr-.Laddr)(r4) /* linker generated address of .LCTOC1 */ - add r5,r5,r4 /* correct to real pointer */ - lwz r4,.Ltable(r5) /* get linker's idea of where .Laddr is */ - subf r4,r4,r5 /* calculate difference between where linked and current */ - - /* clear bss */ - lwz r6,.Lbss_start(r5) /* calculate beginning of the BSS */ - lwz r7,.Lend(r5) /* calculate end of the BSS */ - add r6,r6,r4 /* adjust pointers */ - add r7,r7,r4 - - cmplw 1,r6,r7 - bc 4,4,.Ldone - - subf r8,r6,r7 /* number of bytes to zero */ - srwi r9,r8,2 /* number of words to zero */ - mtctr r9 - li r0,0 /* zero to clear memory */ - addi r6,r6,-4 /* adjust so we can use stwu */ -.Lloop: - stwu r0,4(r6) /* zero bss */ - bdnz .Lloop - -.Ldone: - - lwz r0,.Lstack(r5) /* stack address or 0 */ - cmplwi 1,r0,0 /* equal to 0? */ - bc 12,6,.Lnostack /* use default stack if == 0 */ - mr sp,r0 /* use user defined stack */ - -.Lnostack: - /* set up initial stack frame */ - addi sp,sp,-4 /* make sure we don't overwrite debug mem */ - lis r0,0 - stw r0,0(sp) /* clear back chain */ - stwu sp,-56(sp) /* push another stack frame */ - - /* Let her rip */ - bl FUNC_NAME(boot_card) - - /* return value from boot_card is argument to exit */ - bl FUNC_NAME(exit) - trap -.Lstart: - .size _start,.Lstart-_start diff --git a/c/src/lib/libbsp/powerpc/psim/startup/Makefile.in b/c/src/lib/libbsp/powerpc/psim/startup/Makefile.in index 8ae332fa12..15afe54b35 100644 --- a/c/src/lib/libbsp/powerpc/psim/startup/Makefile.in +++ b/c/src/lib/libbsp/powerpc/psim/startup/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES= -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=linkcmds device-tree $(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/powerpc/psim/timer/Makefile.in b/c/src/lib/libbsp/powerpc/psim/timer/Makefile.in index 16665e4de9..0ac1995395 100644 --- a/c/src/lib/libbsp/powerpc/psim/timer/Makefile.in +++ b/c/src/lib/libbsp/powerpc/psim/timer/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES= -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/powerpc/psim/vectors/Makefile.in b/c/src/lib/libbsp/powerpc/psim/vectors/Makefile.in index 031b7ca193..8034ba90e3 100644 --- a/c/src/lib/libbsp/powerpc/psim/vectors/Makefile.in +++ b/c/src/lib/libbsp/powerpc/psim/vectors/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=align_h vectors -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/powerpc/psim/vectors/align_h.S b/c/src/lib/libbsp/powerpc/psim/vectors/align_h.S new file mode 100644 index 0000000000..d16298343d --- /dev/null +++ b/c/src/lib/libbsp/powerpc/psim/vectors/align_h.S @@ -0,0 +1,434 @@ +/* align_h.s 1.1 - 95/12/04 + * + * This file contains the assembly code for the PowerPC 403 + * alignment exception handler for RTEMS. + * + * Based upon IBM provided code with the following release: + * + * This source code has been made available to you by IBM on an AS-IS + * basis. Anyone receiving this source is licensed under IBM + * copyrights to use it in any way he or she deems fit, including + * copying it, modifying it, compiling it, and redistributing it either + * with or without modifications. No license under IBM patents or + * patent applications is to be implied by the copyright license. + * + * Any user of this software should understand that IBM cannot provide + * technical support for this software and will not be responsible for + * any consequences resulting from the use of this software. + * + * Any person who transfers this source code or any derivative work + * must include the IBM copyright notice, this paragraph, and the + * preceding two paragraphs in the transferred software. + * + * COPYRIGHT I B M CORPORATION 1995 + * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M + * + * Modifications: + * + * Author: Andrew Bray + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * $Id$ + */ + +#include "asm.h" +#include "bsp.h" + +.set CACHE_SIZE,16 # cache line size of 32 bytes +.set CACHE_SIZE_L2,4 # cache line size, log 2 + +.set Open_gpr0,0 +.set Open_gpr1,4 +.set Open_gpr2,8 +.set Open_gpr3,12 +.set Open_gpr4,16 +.set Open_gpr5,20 +.set Open_gpr6,24 +.set Open_gpr7,28 +.set Open_gpr8,32 +.set Open_gpr9,36 +.set Open_gpr10,40 +.set Open_gpr11,44 +.set Open_gpr12,48 +.set Open_gpr13,52 +.set Open_gpr14,56 +.set Open_gpr15,60 +.set Open_gpr16,64 +.set Open_gpr17,68 +.set Open_gpr18,72 +.set Open_gpr19,76 +.set Open_gpr20,80 +.set Open_gpr21,84 +.set Open_gpr22,88 +.set Open_gpr23,92 +.set Open_gpr24,96 +.set Open_gpr25,100 +.set Open_gpr26,104 +.set Open_gpr27,108 +.set Open_gpr28,112 +.set Open_gpr29,116 +.set Open_gpr30,120 +.set Open_gpr31,124 +.set Open_xer,128 +.set Open_lr,132 +.set Open_ctr,136 +.set Open_cr,140 +.set Open_srr2,144 +.set Open_srr3,148 +.set Open_srr0,152 +.set Open_srr1,156 + + +/* + * This code makes several assumptions for processing efficiency + * * General purpose registers are continuous in the image, beginning with + * Open_gpr0 + * * Hash table is highly dependent on opcodes - opcode changes *will* + * require rework of the instruction decode mechanism. + */ + + .text + .globl align_h + + .align CACHE_SIZE_L2 +align_h: + /*----------------------------------------------------------------------- + * Store GPRs in Open Reg save area + * Set up r2 as base reg, r1 pointing to Open Reg save area + *----------------------------------------------------------------------*/ + stmw r0,ALIGN_REGS(r0) + li r1,ALIGN_REGS + /*----------------------------------------------------------------------- + * Store special purpose registers in reg save area + *----------------------------------------------------------------------*/ + mfxer r7 + mflr r8 + mfcr r9 + mfctr r10 + stw r7,Open_xer(r1) + stw r8,Open_lr(r1) + stw r9,Open_cr(r1) + stw r10,Open_ctr(r1) + mfspr r7, srr2 /* SRR 2 */ + mfspr r8, srr3 /* SRR 3 */ + mfspr r9, srr0 /* SRR 0 */ + mfspr r10, srr1 /* SRR 1 */ + stw r7,Open_srr2(r1) + stw r8,Open_srr3(r1) + stw r9,Open_srr0(r1) + stw r10,Open_srr1(r1) + +/* Set up common registers */ + mfspr r5, dear /* DEAR: R5 is data exception address */ + lwz r9,Open_srr0(r1) /* get faulting instruction */ + addi r7,r9,4 /* bump instruction */ + stw r7,Open_srr0(r1) /* restore to image */ + lwz r9, 0(r9) /* retrieve actual instruction */ + rlwinm r6,r9,18,25,29 /* r6 is RA * 4 field from instruction */ + rlwinm r7,r9,6,26,31 /* r7 is primary opcode */ + bl ref_point /* establish addressibility */ +ref_point: + mflr r11 /* r11 is the anchor point for ref_point */ + addi r10, r7, -31 /* r10 = r7 - 31 */ + rlwinm r10,r10,2,2,31 /* r10 *= 4 */ + add r10, r10, r11 /* r10 += anchor point */ + lwz r10, primary_jt-ref_point(r10) + mtlr r10 + rlwinm r8,r9,13,25,29 /* r8 is RD * 4 */ + la r7,Open_gpr0(r1) /* r7 is address of GPR 0 in list */ + blr +primary_jt: + .long xform + .long lwz + .long lwzu + .long 0 + .long 0 + .long stw + .long stwu + .long 0 + .long 0 + .long lhz + .long lhzu + .long lha + .long lhau + .long sth + .long sthu + .long lmw + .long stmw +/* + * handlers + */ +/* + * xform instructions require an additional decode. Fortunately, a relatively + * simple hash step breaks the instructions out with no collisions + */ +xform: + rlwinm r7,r9,31,22,31 /* r7 is secondary opcode */ + rlwinm r10,r7,27,5,31 /* r10 = r7 >> 5 */ + add r10,r7,r10 /* r10 = r7 + r10 */ + rlwinm r10,r10,2,25,29 /* r10 = (r10 & 0x1F) * 4 */ + add r10,r10,r11 /* r10 += anchor point */ + lwz r10, secondary_ht-ref_point(r10) + mtlr r10 + la r7,Open_gpr0(r1) /* r7 is address of GPR 0 in list */ + rlwinm r8,r9,13,25,29 /* r8 is RD * 4 */ + blrl + +secondary_ht: + .long lhzux /* b 0 0x137 */ + .long lhax /* b 1 0x157 */ + .long lhaux /* b 2 0x177 */ + .long sthx /* b 3 0x197 */ + .long sthux /* b 4 0x1b7 */ + .long 0 /* b 5 */ + .long lwbrx /* b 6 0x216 */ + .long 0 /* b 7 */ + .long 0 /* b 8 */ + .long 0 /* b 9 */ + .long stwbrx /* b A 0x296 */ + .long 0 /* b B */ + .long 0 /* b C */ + .long 0 /* b D */ + .long lhbrx /* b E 0x316 */ + .long 0 /* b F */ + .long 0 /* b 10 */ + .long 0 /* b 11 */ + .long sthbrx /* b 12 0x396 */ + .long 0 /* b 13 */ + .long lwarx /* b 14 0x014 */ + .long dcbz /* b 15 0x3f6 */ + .long 0 /* b 16 */ + .long lwzx /* b 17 0x017 */ + .long lwzux /* b 18 0x037 */ + .long 0 /* b 19 */ + .long stwcx /* b 1A 0x096 */ + .long stwx /* b 1B 0x097 */ + .long stwux /* b 1C 0x0B7 */ + .long 0 /* b 1D */ + .long 0 /* b 1E */ + .long lhzx /* b 1F 0x117 */ + +/* + * for all handlers + * r4 - Addressability to interrupt context + * r5 - DEAR address (faulting data address) + * r6 - RA field * 4 + * r7 - Address of GPR 0 in image + * r8 - RD field * 4 + * r9 - Failing instruction + */ + +/* Load halfword algebraic with update */ +lhau: +/* Load halfword algebraic with update indexed */ +lhaux: + stwx r5,r7,r6 /* update RA with effective addr */ + +/* Load halfword algebraic */ +lha: +/* Load halfword algebraic indexed */ +lhax: + lswi r10,r5,2 /* load two bytes into r10 */ + srawi r10,r10,16 /* shift right 2 bytes, extending sign */ + stwx r10,r7,r8 /* update reg image */ + b align_complete /* return */ + +/* Load Half Word Byte-Reversed Indexed */ +lhbrx: + lswi r10,r5,2 /* load two bytes from DEAR into r10 */ + rlwinm r10,r10,0,0,15 /* mask off lower 2 bytes */ + stwbrx r10,r7,r8 /* store reversed in reg image */ + b align_complete /* return */ + +/* Load Half Word and Zero with Update */ +lhzu: +/* Load Half Word and Zero with Update Indexed */ +lhzux: + stwx r5,r7,r6 /* update RA with effective addr */ + +/* Load Half Word and Zero */ +lhz: +/* Load Half Word and Zero Indexed */ +lhzx: + lswi r10,r5,2 /* load two bytes from DEAR into r10 */ + rlwinm r10,r10,16,16,31 /* shift right 2 bytes, with zero fill */ + stwx r10,r7,r8 /* update reg image */ + b align_complete /* return */ + +/* + * Load Multiple Word + */ +lmw: + lwzx r9,r6,r7 /* R9 contains saved value of RA */ + addi r10,r7,32*4 /* r10 points to r31 in image + 4 */ + rlwinm r8,r8,30,2,31 /* r8 >>= 2 (recovers RT) */ + subfic r8,r8,32 /* r8 is reg count to load */ + mtctr r8 /* load counter */ + addi r8,r8,-1 /* r8-- */ + rlwinm r8,r8,2,2,31 /* r8 *= 4 */ + add r5,r5,r8 /* update DEAR to point to last reg */ +lwmloop: + lswi r11,r5,4 /* load r11 with 4 bytes from DEAR */ + stwu r11,-4(r10) /* load image and decrement pointer */ + addi r5,r5,-4 /* decrement effective address */ + bdnz lwmloop + stwx r9,r6,r7 /* restore RA (in case it was trashed) */ + b align_complete /* return */ + +/* + * Load Word and Reserve Indexed + */ +lwarx: + lswi r10,r5,4 /* load four bytes from DEAR into r10 */ + stwx r10,r7,r8 /* update reg image */ + rlwinm r5,r5,0,0,29 /* Word align address */ + lwarx r10,0,r5 /* Set reservation */ + b align_complete /* return */ + +/* + * Load Word Byte-Reversed Indexed + */ +lwbrx: + lswi r10,r5,4 /* load four bytes from DEAR into r10 */ + stwbrx r10,r7,r8 /* store reversed in reg image */ + b align_complete /* return */ + +/* Load Word and Zero with Update */ +lwzu: +/* Load Word and Zero with Update Indexed */ +lwzux: + stwx r5,r7,r6 /* update RA with effective addr */ + +/* Load Word and Zero */ +lwz: +/* Load Word and Zero Indexed */ +lwzx: + lswi r10,r5,4 /* load four bytes from DEAR into r10 */ + stwx r10,r7,r8 /* update reg image */ + b align_complete /* return */ + +/* Store instructions */ + +/* */ +/* Store Half Word and Update */ +sthu: +/* Store Half Word and Update Indexed */ +sthux: + stwx r5,r7,r6 /* Update RA with effective address */ + +/* Store Half Word */ +sth: +/* Store Half Word Indexed */ +sthx: + lwzx r10,r8,r7 /* retrieve source register value */ + rlwinm r10,r10,16,0,15 /* move two bytes to high end of reg */ + stswi r10,r5,2 /* store bytes to DEAR address */ + b align_complete /* return */ + +/* */ +/* Store Half Word Byte-Reversed Indexed */ +sthbrx: + lwbrx r10,r8,r7 /* retrieve src reg value byte reversed */ + stswi r10,r5,2 /* move two bytes to DEAR address */ + b align_complete /* return */ + +/* */ +/* Store Multiple Word */ +stmw: + addi r10,r7,32*4 /* r10 points to r31 in image + 4 */ + rlwinm r8,r8,30,2,31 /* r8 >>= 2 (recovers RT) */ + subfic r8,r8,32 /* r8 is reg count to load */ + mtctr r8 /* load counter */ + addi r8,r8,-1 /* r8-- */ + rlwinm r8,r8,2,2,31 /* r8 *= 4 */ + add r5,r5,r8 /* update DEAR to point to last reg */ +stmloop: + lwzu r11,-4(r10) /* get register value */ + stswi r11,r5,4 /* output to DEAR address */ + addi r5,r5,-4 /* decrement effective address */ + bdnz stmloop + b align_complete /* return */ + +/* */ +/* Store Word and Update */ +stwu: +/* Store Word and Update Indexed */ +stwux: + stwx r5,r7,r6 /* Update RA with effective address */ + +/* Store Word */ +stw: +/* Store Word Indexed */ +stwx: + lwzx r10,r8,r7 /* retrieve source register value */ + stswi r10,r5,4 /* store bytes to DEAR address */ + b align_complete /* return */ + +/* */ +/* Store Word Byte-Reversed Indexed */ +stwbrx: + lwbrx r10,r8,r7 /* retrieve src reg value byte reversed */ + stswi r10,r5,4 /* move two bytes to DEAR address */ + b align_complete /* return */ + +/* */ +/* Store Word Conditional Indexed */ +stwcx: + rlwinm r10,r5,0,0,29 /* r10 = word aligned DEAR */ + lwz r11,0(r10) /* save original value of store */ + stwcx. r11,r0,r10 /* attempt store to address */ + bne stwcx_moveon /* store failed, move on */ + stw r11,0(r10) /* repair damage */ + lwzx r9,r7,r8 /* get register value */ + stswi r10,r5,4 /* store bytes to DEAR address */ +stwcx_moveon: + mfcr r11 /* get condition reg */ + lwz r9,Open_cr(r1) /* get condition reg image */ + rlwimi r9,r11,0,0,2 /* insert 3 CR bits into cr image */ + lwz r11,Open_xer(r1) /* get XER reg */ + rlwimi r9,r11,29,2,2 /* insert XER SO bit into cr image */ + stw r9,Open_cr(r1) /* store cr image */ + b align_complete /* return */ + +/* */ +/* Data Cache Block Zero */ +dcbz: + rlwinm r5,r5,0,0,31-CACHE_SIZE_L2 + /* get address to nearest Cache line */ + addi r5,r5,-4 /* adjust by a word */ + addi r10,r0,CACHE_SIZE/4 /* set counter value */ + mtctr r10 + addi r11,r0,0 /* r11 = 0 */ +dcbz_loop: + stwu r11,4(r5) /* store a word and update EA */ + bdnz dcbz_loop + b align_complete /* return */ + +align_complete: + /*----------------------------------------------------------------------- + * Restore regs and return from the interrupt + *----------------------------------------------------------------------*/ + lmw r24,Open_xer+ALIGN_REGS(r0) + mtxer r24 + mtlr r25 + mtctr r26 + mtcrf 0xFF, r27 + mtspr srr2, r28 /* SRR 2 */ + mtspr srr3, r29 /* SRR 3 */ + mtspr srr0, r30 /* SRR 0 */ + mtspr srr1, r31 /* SRR 1 */ + lmw r1,Open_gpr1+ALIGN_REGS(r0) + lwz r0,Open_gpr0+ALIGN_REGS(r0) + rfi diff --git a/c/src/lib/libbsp/powerpc/psim/vectors/align_h.s b/c/src/lib/libbsp/powerpc/psim/vectors/align_h.s deleted file mode 100644 index d16298343d..0000000000 --- a/c/src/lib/libbsp/powerpc/psim/vectors/align_h.s +++ /dev/null @@ -1,434 +0,0 @@ -/* align_h.s 1.1 - 95/12/04 - * - * This file contains the assembly code for the PowerPC 403 - * alignment exception handler for RTEMS. - * - * Based upon IBM provided code with the following release: - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - * - * Modifications: - * - * Author: Andrew Bray - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * $Id$ - */ - -#include "asm.h" -#include "bsp.h" - -.set CACHE_SIZE,16 # cache line size of 32 bytes -.set CACHE_SIZE_L2,4 # cache line size, log 2 - -.set Open_gpr0,0 -.set Open_gpr1,4 -.set Open_gpr2,8 -.set Open_gpr3,12 -.set Open_gpr4,16 -.set Open_gpr5,20 -.set Open_gpr6,24 -.set Open_gpr7,28 -.set Open_gpr8,32 -.set Open_gpr9,36 -.set Open_gpr10,40 -.set Open_gpr11,44 -.set Open_gpr12,48 -.set Open_gpr13,52 -.set Open_gpr14,56 -.set Open_gpr15,60 -.set Open_gpr16,64 -.set Open_gpr17,68 -.set Open_gpr18,72 -.set Open_gpr19,76 -.set Open_gpr20,80 -.set Open_gpr21,84 -.set Open_gpr22,88 -.set Open_gpr23,92 -.set Open_gpr24,96 -.set Open_gpr25,100 -.set Open_gpr26,104 -.set Open_gpr27,108 -.set Open_gpr28,112 -.set Open_gpr29,116 -.set Open_gpr30,120 -.set Open_gpr31,124 -.set Open_xer,128 -.set Open_lr,132 -.set Open_ctr,136 -.set Open_cr,140 -.set Open_srr2,144 -.set Open_srr3,148 -.set Open_srr0,152 -.set Open_srr1,156 - - -/* - * This code makes several assumptions for processing efficiency - * * General purpose registers are continuous in the image, beginning with - * Open_gpr0 - * * Hash table is highly dependent on opcodes - opcode changes *will* - * require rework of the instruction decode mechanism. - */ - - .text - .globl align_h - - .align CACHE_SIZE_L2 -align_h: - /*----------------------------------------------------------------------- - * Store GPRs in Open Reg save area - * Set up r2 as base reg, r1 pointing to Open Reg save area - *----------------------------------------------------------------------*/ - stmw r0,ALIGN_REGS(r0) - li r1,ALIGN_REGS - /*----------------------------------------------------------------------- - * Store special purpose registers in reg save area - *----------------------------------------------------------------------*/ - mfxer r7 - mflr r8 - mfcr r9 - mfctr r10 - stw r7,Open_xer(r1) - stw r8,Open_lr(r1) - stw r9,Open_cr(r1) - stw r10,Open_ctr(r1) - mfspr r7, srr2 /* SRR 2 */ - mfspr r8, srr3 /* SRR 3 */ - mfspr r9, srr0 /* SRR 0 */ - mfspr r10, srr1 /* SRR 1 */ - stw r7,Open_srr2(r1) - stw r8,Open_srr3(r1) - stw r9,Open_srr0(r1) - stw r10,Open_srr1(r1) - -/* Set up common registers */ - mfspr r5, dear /* DEAR: R5 is data exception address */ - lwz r9,Open_srr0(r1) /* get faulting instruction */ - addi r7,r9,4 /* bump instruction */ - stw r7,Open_srr0(r1) /* restore to image */ - lwz r9, 0(r9) /* retrieve actual instruction */ - rlwinm r6,r9,18,25,29 /* r6 is RA * 4 field from instruction */ - rlwinm r7,r9,6,26,31 /* r7 is primary opcode */ - bl ref_point /* establish addressibility */ -ref_point: - mflr r11 /* r11 is the anchor point for ref_point */ - addi r10, r7, -31 /* r10 = r7 - 31 */ - rlwinm r10,r10,2,2,31 /* r10 *= 4 */ - add r10, r10, r11 /* r10 += anchor point */ - lwz r10, primary_jt-ref_point(r10) - mtlr r10 - rlwinm r8,r9,13,25,29 /* r8 is RD * 4 */ - la r7,Open_gpr0(r1) /* r7 is address of GPR 0 in list */ - blr -primary_jt: - .long xform - .long lwz - .long lwzu - .long 0 - .long 0 - .long stw - .long stwu - .long 0 - .long 0 - .long lhz - .long lhzu - .long lha - .long lhau - .long sth - .long sthu - .long lmw - .long stmw -/* - * handlers - */ -/* - * xform instructions require an additional decode. Fortunately, a relatively - * simple hash step breaks the instructions out with no collisions - */ -xform: - rlwinm r7,r9,31,22,31 /* r7 is secondary opcode */ - rlwinm r10,r7,27,5,31 /* r10 = r7 >> 5 */ - add r10,r7,r10 /* r10 = r7 + r10 */ - rlwinm r10,r10,2,25,29 /* r10 = (r10 & 0x1F) * 4 */ - add r10,r10,r11 /* r10 += anchor point */ - lwz r10, secondary_ht-ref_point(r10) - mtlr r10 - la r7,Open_gpr0(r1) /* r7 is address of GPR 0 in list */ - rlwinm r8,r9,13,25,29 /* r8 is RD * 4 */ - blrl - -secondary_ht: - .long lhzux /* b 0 0x137 */ - .long lhax /* b 1 0x157 */ - .long lhaux /* b 2 0x177 */ - .long sthx /* b 3 0x197 */ - .long sthux /* b 4 0x1b7 */ - .long 0 /* b 5 */ - .long lwbrx /* b 6 0x216 */ - .long 0 /* b 7 */ - .long 0 /* b 8 */ - .long 0 /* b 9 */ - .long stwbrx /* b A 0x296 */ - .long 0 /* b B */ - .long 0 /* b C */ - .long 0 /* b D */ - .long lhbrx /* b E 0x316 */ - .long 0 /* b F */ - .long 0 /* b 10 */ - .long 0 /* b 11 */ - .long sthbrx /* b 12 0x396 */ - .long 0 /* b 13 */ - .long lwarx /* b 14 0x014 */ - .long dcbz /* b 15 0x3f6 */ - .long 0 /* b 16 */ - .long lwzx /* b 17 0x017 */ - .long lwzux /* b 18 0x037 */ - .long 0 /* b 19 */ - .long stwcx /* b 1A 0x096 */ - .long stwx /* b 1B 0x097 */ - .long stwux /* b 1C 0x0B7 */ - .long 0 /* b 1D */ - .long 0 /* b 1E */ - .long lhzx /* b 1F 0x117 */ - -/* - * for all handlers - * r4 - Addressability to interrupt context - * r5 - DEAR address (faulting data address) - * r6 - RA field * 4 - * r7 - Address of GPR 0 in image - * r8 - RD field * 4 - * r9 - Failing instruction - */ - -/* Load halfword algebraic with update */ -lhau: -/* Load halfword algebraic with update indexed */ -lhaux: - stwx r5,r7,r6 /* update RA with effective addr */ - -/* Load halfword algebraic */ -lha: -/* Load halfword algebraic indexed */ -lhax: - lswi r10,r5,2 /* load two bytes into r10 */ - srawi r10,r10,16 /* shift right 2 bytes, extending sign */ - stwx r10,r7,r8 /* update reg image */ - b align_complete /* return */ - -/* Load Half Word Byte-Reversed Indexed */ -lhbrx: - lswi r10,r5,2 /* load two bytes from DEAR into r10 */ - rlwinm r10,r10,0,0,15 /* mask off lower 2 bytes */ - stwbrx r10,r7,r8 /* store reversed in reg image */ - b align_complete /* return */ - -/* Load Half Word and Zero with Update */ -lhzu: -/* Load Half Word and Zero with Update Indexed */ -lhzux: - stwx r5,r7,r6 /* update RA with effective addr */ - -/* Load Half Word and Zero */ -lhz: -/* Load Half Word and Zero Indexed */ -lhzx: - lswi r10,r5,2 /* load two bytes from DEAR into r10 */ - rlwinm r10,r10,16,16,31 /* shift right 2 bytes, with zero fill */ - stwx r10,r7,r8 /* update reg image */ - b align_complete /* return */ - -/* - * Load Multiple Word - */ -lmw: - lwzx r9,r6,r7 /* R9 contains saved value of RA */ - addi r10,r7,32*4 /* r10 points to r31 in image + 4 */ - rlwinm r8,r8,30,2,31 /* r8 >>= 2 (recovers RT) */ - subfic r8,r8,32 /* r8 is reg count to load */ - mtctr r8 /* load counter */ - addi r8,r8,-1 /* r8-- */ - rlwinm r8,r8,2,2,31 /* r8 *= 4 */ - add r5,r5,r8 /* update DEAR to point to last reg */ -lwmloop: - lswi r11,r5,4 /* load r11 with 4 bytes from DEAR */ - stwu r11,-4(r10) /* load image and decrement pointer */ - addi r5,r5,-4 /* decrement effective address */ - bdnz lwmloop - stwx r9,r6,r7 /* restore RA (in case it was trashed) */ - b align_complete /* return */ - -/* - * Load Word and Reserve Indexed - */ -lwarx: - lswi r10,r5,4 /* load four bytes from DEAR into r10 */ - stwx r10,r7,r8 /* update reg image */ - rlwinm r5,r5,0,0,29 /* Word align address */ - lwarx r10,0,r5 /* Set reservation */ - b align_complete /* return */ - -/* - * Load Word Byte-Reversed Indexed - */ -lwbrx: - lswi r10,r5,4 /* load four bytes from DEAR into r10 */ - stwbrx r10,r7,r8 /* store reversed in reg image */ - b align_complete /* return */ - -/* Load Word and Zero with Update */ -lwzu: -/* Load Word and Zero with Update Indexed */ -lwzux: - stwx r5,r7,r6 /* update RA with effective addr */ - -/* Load Word and Zero */ -lwz: -/* Load Word and Zero Indexed */ -lwzx: - lswi r10,r5,4 /* load four bytes from DEAR into r10 */ - stwx r10,r7,r8 /* update reg image */ - b align_complete /* return */ - -/* Store instructions */ - -/* */ -/* Store Half Word and Update */ -sthu: -/* Store Half Word and Update Indexed */ -sthux: - stwx r5,r7,r6 /* Update RA with effective address */ - -/* Store Half Word */ -sth: -/* Store Half Word Indexed */ -sthx: - lwzx r10,r8,r7 /* retrieve source register value */ - rlwinm r10,r10,16,0,15 /* move two bytes to high end of reg */ - stswi r10,r5,2 /* store bytes to DEAR address */ - b align_complete /* return */ - -/* */ -/* Store Half Word Byte-Reversed Indexed */ -sthbrx: - lwbrx r10,r8,r7 /* retrieve src reg value byte reversed */ - stswi r10,r5,2 /* move two bytes to DEAR address */ - b align_complete /* return */ - -/* */ -/* Store Multiple Word */ -stmw: - addi r10,r7,32*4 /* r10 points to r31 in image + 4 */ - rlwinm r8,r8,30,2,31 /* r8 >>= 2 (recovers RT) */ - subfic r8,r8,32 /* r8 is reg count to load */ - mtctr r8 /* load counter */ - addi r8,r8,-1 /* r8-- */ - rlwinm r8,r8,2,2,31 /* r8 *= 4 */ - add r5,r5,r8 /* update DEAR to point to last reg */ -stmloop: - lwzu r11,-4(r10) /* get register value */ - stswi r11,r5,4 /* output to DEAR address */ - addi r5,r5,-4 /* decrement effective address */ - bdnz stmloop - b align_complete /* return */ - -/* */ -/* Store Word and Update */ -stwu: -/* Store Word and Update Indexed */ -stwux: - stwx r5,r7,r6 /* Update RA with effective address */ - -/* Store Word */ -stw: -/* Store Word Indexed */ -stwx: - lwzx r10,r8,r7 /* retrieve source register value */ - stswi r10,r5,4 /* store bytes to DEAR address */ - b align_complete /* return */ - -/* */ -/* Store Word Byte-Reversed Indexed */ -stwbrx: - lwbrx r10,r8,r7 /* retrieve src reg value byte reversed */ - stswi r10,r5,4 /* move two bytes to DEAR address */ - b align_complete /* return */ - -/* */ -/* Store Word Conditional Indexed */ -stwcx: - rlwinm r10,r5,0,0,29 /* r10 = word aligned DEAR */ - lwz r11,0(r10) /* save original value of store */ - stwcx. r11,r0,r10 /* attempt store to address */ - bne stwcx_moveon /* store failed, move on */ - stw r11,0(r10) /* repair damage */ - lwzx r9,r7,r8 /* get register value */ - stswi r10,r5,4 /* store bytes to DEAR address */ -stwcx_moveon: - mfcr r11 /* get condition reg */ - lwz r9,Open_cr(r1) /* get condition reg image */ - rlwimi r9,r11,0,0,2 /* insert 3 CR bits into cr image */ - lwz r11,Open_xer(r1) /* get XER reg */ - rlwimi r9,r11,29,2,2 /* insert XER SO bit into cr image */ - stw r9,Open_cr(r1) /* store cr image */ - b align_complete /* return */ - -/* */ -/* Data Cache Block Zero */ -dcbz: - rlwinm r5,r5,0,0,31-CACHE_SIZE_L2 - /* get address to nearest Cache line */ - addi r5,r5,-4 /* adjust by a word */ - addi r10,r0,CACHE_SIZE/4 /* set counter value */ - mtctr r10 - addi r11,r0,0 /* r11 = 0 */ -dcbz_loop: - stwu r11,4(r5) /* store a word and update EA */ - bdnz dcbz_loop - b align_complete /* return */ - -align_complete: - /*----------------------------------------------------------------------- - * Restore regs and return from the interrupt - *----------------------------------------------------------------------*/ - lmw r24,Open_xer+ALIGN_REGS(r0) - mtxer r24 - mtlr r25 - mtctr r26 - mtcrf 0xFF, r27 - mtspr srr2, r28 /* SRR 2 */ - mtspr srr3, r29 /* SRR 3 */ - mtspr srr0, r30 /* SRR 0 */ - mtspr srr1, r31 /* SRR 1 */ - lmw r1,Open_gpr1+ALIGN_REGS(r0) - lwz r0,Open_gpr0+ALIGN_REGS(r0) - rfi diff --git a/c/src/lib/libbsp/powerpc/psim/vectors/vectors.S b/c/src/lib/libbsp/powerpc/psim/vectors/vectors.S new file mode 100644 index 0000000000..448e9117e2 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/psim/vectors/vectors.S @@ -0,0 +1,123 @@ +/* vectors.s 1.1 - 95/12/04 + * + * This file contains the assembly code for the PowerPC + * interrupt vectors for RTEMS. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +/* + * The issue with this file is getting it loaded at the right place. + * The first vector MUST be at address 0x????0100. + * How this is achieved is dependant on the tool chain. + * + * However the basic mechanism for ELF assemblers is to create a + * section called ".vectors", which will be loaded to an address + * between 0x????0000 and 0x????0100 (inclusive) via a link script. + * + * The basic mechanism for XCOFF assemblers is to place it in the + * normal text section, and arrange for this file to be located + * at an appropriate position on the linker command line. + * + * The variable 'PPC_VECTOR_FILE_BASE' must be defined to be the + * offset from 0x????0000 to the first location in the file. This + * will usually be 0x0000 or 0x0100. + */ + +#include "asm.h" + +#ifndef PPC_VECTOR_FILE_BASE +#error "PPC_VECTOR_FILE_BASE is not defined." +#endif + + /* Where this file will be loaded */ + .set file_base, PPC_VECTOR_FILE_BASE + + /* Offset to store reg 0 */ + + .set IP_LINK, 0 +#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) + .set IP_0, (IP_LINK + 56) +#else + .set IP_0, (IP_LINK + 8) +#endif + .set IP_2, (IP_0 + 4) + + .set IP_3, (IP_2 + 4) + .set IP_4, (IP_3 + 4) + .set IP_5, (IP_4 + 4) + .set IP_6, (IP_5 + 4) + + .set IP_7, (IP_6 + 4) + .set IP_8, (IP_7 + 4) + .set IP_9, (IP_8 + 4) + .set IP_10, (IP_9 + 4) + + .set IP_11, (IP_10 + 4) + .set IP_12, (IP_11 + 4) + .set IP_13, (IP_12 + 4) + .set IP_28, (IP_13 + 4) + + .set IP_29, (IP_28 + 4) + .set IP_30, (IP_29 + 4) + .set IP_31, (IP_30 + 4) + .set IP_CR, (IP_31 + 4) + + .set IP_CTR, (IP_CR + 4) + .set IP_XER, (IP_CTR + 4) + .set IP_LR, (IP_XER + 4) + .set IP_PC, (IP_LR + 4) + + .set IP_MSR, (IP_PC + 4) + + .set IP_END, (IP_MSR + 16) + + /* Vector offsets */ + .set begin_vector,0xFFF00000 + .set crit_vector,0xFFF00100 + .set mach_vector,0xFFF00200 + .set prot_vector,0xFFF00300 + .set ext_vector,0xFFF00500 + .set align_vector,0xFFF00600 + .set prog_vector,0xFFF00700 + .set dec_vector,0xFFF00900 + .set sys_vector,0xFFF00C00 + .set pit_vector,0xFFF01000 + .set fit_vector,0xFFF01010 + .set wadt_vector,0xFFF01020 + .set debug_vector,0xFFF02000 + +/* Go to the right section */ +#if PPC_ASM == PPC_ASM_ELF + .section .vectors,"awx",@progbits +#elif PPC_ASM == PPC_ASM_XCOFF + .csect .text[PR] +#endif + + PUBLIC_VAR (__vectors) +SYM (__vectors): + +/* Decrementer interrupt */ + .org dec_vector - file_base +#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) +#if (PPC_HAS_FPU) + stwu r1, -(20*4 + 18*8 + IP_END)(r1) +#else + stwu r1, -(20*4 + IP_END)(r1) +#endif +#else + stwu r1, -(IP_END)(r1) +#endif + stw r0, IP_0(r1) + + li r0, PPC_IRQ_DECREMENTER + b PROC (_ISR_Handler) + diff --git a/c/src/lib/libbsp/powerpc/psim/vectors/vectors.s b/c/src/lib/libbsp/powerpc/psim/vectors/vectors.s deleted file mode 100644 index 448e9117e2..0000000000 --- a/c/src/lib/libbsp/powerpc/psim/vectors/vectors.s +++ /dev/null @@ -1,123 +0,0 @@ -/* vectors.s 1.1 - 95/12/04 - * - * This file contains the assembly code for the PowerPC - * interrupt vectors for RTEMS. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -/* - * The issue with this file is getting it loaded at the right place. - * The first vector MUST be at address 0x????0100. - * How this is achieved is dependant on the tool chain. - * - * However the basic mechanism for ELF assemblers is to create a - * section called ".vectors", which will be loaded to an address - * between 0x????0000 and 0x????0100 (inclusive) via a link script. - * - * The basic mechanism for XCOFF assemblers is to place it in the - * normal text section, and arrange for this file to be located - * at an appropriate position on the linker command line. - * - * The variable 'PPC_VECTOR_FILE_BASE' must be defined to be the - * offset from 0x????0000 to the first location in the file. This - * will usually be 0x0000 or 0x0100. - */ - -#include "asm.h" - -#ifndef PPC_VECTOR_FILE_BASE -#error "PPC_VECTOR_FILE_BASE is not defined." -#endif - - /* Where this file will be loaded */ - .set file_base, PPC_VECTOR_FILE_BASE - - /* Offset to store reg 0 */ - - .set IP_LINK, 0 -#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) - .set IP_0, (IP_LINK + 56) -#else - .set IP_0, (IP_LINK + 8) -#endif - .set IP_2, (IP_0 + 4) - - .set IP_3, (IP_2 + 4) - .set IP_4, (IP_3 + 4) - .set IP_5, (IP_4 + 4) - .set IP_6, (IP_5 + 4) - - .set IP_7, (IP_6 + 4) - .set IP_8, (IP_7 + 4) - .set IP_9, (IP_8 + 4) - .set IP_10, (IP_9 + 4) - - .set IP_11, (IP_10 + 4) - .set IP_12, (IP_11 + 4) - .set IP_13, (IP_12 + 4) - .set IP_28, (IP_13 + 4) - - .set IP_29, (IP_28 + 4) - .set IP_30, (IP_29 + 4) - .set IP_31, (IP_30 + 4) - .set IP_CR, (IP_31 + 4) - - .set IP_CTR, (IP_CR + 4) - .set IP_XER, (IP_CTR + 4) - .set IP_LR, (IP_XER + 4) - .set IP_PC, (IP_LR + 4) - - .set IP_MSR, (IP_PC + 4) - - .set IP_END, (IP_MSR + 16) - - /* Vector offsets */ - .set begin_vector,0xFFF00000 - .set crit_vector,0xFFF00100 - .set mach_vector,0xFFF00200 - .set prot_vector,0xFFF00300 - .set ext_vector,0xFFF00500 - .set align_vector,0xFFF00600 - .set prog_vector,0xFFF00700 - .set dec_vector,0xFFF00900 - .set sys_vector,0xFFF00C00 - .set pit_vector,0xFFF01000 - .set fit_vector,0xFFF01010 - .set wadt_vector,0xFFF01020 - .set debug_vector,0xFFF02000 - -/* Go to the right section */ -#if PPC_ASM == PPC_ASM_ELF - .section .vectors,"awx",@progbits -#elif PPC_ASM == PPC_ASM_XCOFF - .csect .text[PR] -#endif - - PUBLIC_VAR (__vectors) -SYM (__vectors): - -/* Decrementer interrupt */ - .org dec_vector - file_base -#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) -#if (PPC_HAS_FPU) - stwu r1, -(20*4 + 18*8 + IP_END)(r1) -#else - stwu r1, -(20*4 + IP_END)(r1) -#endif -#else - stwu r1, -(IP_END)(r1) -#endif - stw r0, IP_0(r1) - - li r0, PPC_IRQ_DECREMENTER - b PROC (_ISR_Handler) - diff --git a/c/src/lib/libbsp/powerpc/psim/wrapup/Makefile.in b/c/src/lib/libbsp/powerpc/psim/wrapup/Makefile.in index bae5c6a1ba..db5b9212a9 100644 --- a/c/src/lib/libbsp/powerpc/psim/wrapup/Makefile.in +++ b/c/src/lib/libbsp/powerpc/psim/wrapup/Makefile.in @@ -13,6 +13,9 @@ BSP_PIECES=startup clock console timer vectors CPU_PIECES= GENERIC_PIECES= +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/lib.cfg + ifeq ($(HAS_MP),yes) GENERIC_PIECES += shmdr BSP_PIECES += shmsupp @@ -26,9 +29,6 @@ OBJS=$(foreach piece, $(BSP_PIECES), ../$(piece)/$(ARCH)/$(piece).rel) \ ../../../$(piece)/$(ARCH)/$(piece).rel) LIB=$(ARCH)/libbsp.a -include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg -include $(RTEMS_ROOT)/make/lib.cfg - # # (OPTIONAL) Add local stuff here using += # diff --git a/c/src/lib/libbsp/sh/gensh1/scitab/Makefile.in b/c/src/lib/libbsp/sh/gensh1/scitab/Makefile.in index 18c68db138..06d8574f93 100644 --- a/c/src/lib/libbsp/sh/gensh1/scitab/Makefile.in +++ b/c/src/lib/libbsp/sh/gensh1/scitab/Makefile.in @@ -16,10 +16,10 @@ C_FILES=$(C_PIECES:%=%.c) C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES= -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/sh/gensh1/start/Makefile.in b/c/src/lib/libbsp/sh/gensh1/start/Makefile.in index b5d382a468..327b4f3b5e 100644 --- a/c/src/lib/libbsp/sh/gensh1/start/Makefile.in +++ b/c/src/lib/libbsp/sh/gensh1/start/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=start -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/sh/gensh1/start/start.S b/c/src/lib/libbsp/sh/gensh1/start/start.S new file mode 100644 index 0000000000..9deeb53fed --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh1/start/start.S @@ -0,0 +1,94 @@ +/* + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include "asm.h" + + BEGIN_CODE + PUBLIC(start) +SYM (start): + ! install the stack pointer + mov.l stack_k,r15 + + ! zero out bss + mov.l edata_k,r0 + mov.l end_k,r1 + mov #0,r2 +0: + mov.l r2,@r0 + add #4,r0 + cmp/ge r0,r1 + bt 0b + + ! copy the vector table from rom to ram + mov.l vects_k,r0 ! vectab + mov #0,r1 ! address of boot vector table + mov #0,r2 | number of bytes copied + mov.w vects_size,r3 ! size of entries in vectab +1: + mov.l @r1+,r4 + mov.l r4,@r0 + add #4,r0 + add #1,r2 + cmp/hi r3,r2 + bf 1b + + mov.l vects_k,r0 ! update vbr to point to vectab + ldc r0,vbr + + ! call the mainline + mov #0,r4 ! argc + mov.l main_k,r0 + jsr @r0 + mov #0,r5 ! argv + + ! call exit + mov r0,r4 + mov.l exit_k,r0 + jsr @r0 + or r0,r0 + + END_CODE + + .align 2 +stack_k: + .long SYM(stack) +edata_k: + .long SYM(edata) +end_k: + .long SYM(end) +main_k: + .long SYM(boot_card) +exit_k: + .long SYM(exit) + +vects_k: + .long SYM(vectab) +vects_size: + .word 255 + +#ifdef __ELF__ + .section .stack,"aw" +#else + .section .stack +#endif +SYM(stack): + .long 0xdeaddead diff --git a/c/src/lib/libbsp/sh/gensh1/startup/Makefile.in b/c/src/lib/libbsp/sh/gensh1/startup/Makefile.in index 08adccc862..a7460aa5e8 100644 --- a/c/src/lib/libbsp/sh/gensh1/startup/Makefile.in +++ b/c/src/lib/libbsp/sh/gensh1/startup/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES= -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=linkcmds $(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/sparc/erc32/clock/Makefile.in b/c/src/lib/libbsp/sparc/erc32/clock/Makefile.in index e40e10fb1a..fa1ee1bb31 100644 --- a/c/src/lib/libbsp/sparc/erc32/clock/Makefile.in +++ b/c/src/lib/libbsp/sparc/erc32/clock/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES= -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/sparc/erc32/console/Makefile.in b/c/src/lib/libbsp/sparc/erc32/console/Makefile.in index b73d23df40..1b9944620b 100644 --- a/c/src/lib/libbsp/sparc/erc32/console/Makefile.in +++ b/c/src/lib/libbsp/sparc/erc32/console/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES= -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/sparc/erc32/start/Makefile.in b/c/src/lib/libbsp/sparc/erc32/start/Makefile.in index dbc9cea9e3..0ba183fb83 100644 --- a/c/src/lib/libbsp/sparc/erc32/start/Makefile.in +++ b/c/src/lib/libbsp/sparc/erc32/start/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=startsis -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/sparc/erc32/start/start.S b/c/src/lib/libbsp/sparc/erc32/start/start.S new file mode 100644 index 0000000000..6097c4ab36 --- /dev/null +++ b/c/src/lib/libbsp/sparc/erc32/start/start.S @@ -0,0 +1,309 @@ +/* + * startsis.s + * + * Start code for the ERC32. + * + * This is based on the file srt0.s provided with the binary + * distribution of the SPARC Instruction Simulator (SIS) found + * at ftp://ftp.estec.esa.nl/pub/ws/wsd/erc32. + * + * $Id$ + */ + +#include +#include + +/* + * Unexpected trap will halt the processor by forcing it to error state + */ + +#define BAD_TRAP \ + ta 0; \ + nop; \ + nop; \ + nop; + +/* + * Software trap. Treat as BAD_TRAP for the time being... + */ + +#define SOFT_TRAP BAD_TRAP + + + .seg "text" + PUBLIC(start) + .global start + +SYM(start): +start: + +/* + * The trap table has to be the first code in a boot PROM. But because + * the Memory Configuration comes up thinking we only have 4K of PROM, we + * cannot have a full trap table and still have room left over to + * reprogram the Memory Configuration register correctly. This file + * uses an abbreviated trap which has every entry which might be used + * before RTEMS installs its own trap table. + */ + + + PUBLIC(trap_table) +SYM(trap_table): + + RTRAP( 0, SYM(hard_reset) ); ! 00 reset trap + BAD_TRAP; ! 01 instruction access + ! exception + BAD_TRAP; ! 02 illegal instruction + BAD_TRAP; ! 03 privileged instruction + BAD_TRAP; ! 04 fp disabled + TRAP( 5, SYM(window_overflow_trap_handler) ); ! 05 window overflow + TRAP( 6, SYM(window_underflow_trap_handler) );! 06 window underflow + BAD_TRAP; ! 07 memory address not aligned + BAD_TRAP; ! 08 fp exception + BAD_TRAP; ! 09 data access exception + BAD_TRAP; ! 0A tag overflow + BAD_TRAP; ! 0B undefined + BAD_TRAP; ! 0C undefined + BAD_TRAP; ! 0D undefined + BAD_TRAP; ! 0E undefined + BAD_TRAP; ! 0F undefined + BAD_TRAP; ! 10 undefined + + /* + * ERC32 defined traps + */ + + BAD_TRAP; ! 11 masked errors + BAD_TRAP; ! 12 external 1 + BAD_TRAP; ! 13 external 2 + BAD_TRAP; ! 14 UART A RX/TX + BAD_TRAP; ! 15 UART B RX/TX + BAD_TRAP; ! 16 correctable memory error + BAD_TRAP; ! 17 UART error + BAD_TRAP; ! 18 DMA access error + BAD_TRAP; ! 19 DMA timeout + BAD_TRAP; ! 1A external 3 + BAD_TRAP; ! 1B external 4 + BAD_TRAP; ! 1C general purpose timer + BAD_TRAP; ! 1D real time clock + BAD_TRAP; ! 1E external 5 + BAD_TRAP; ! 1F watchdog timeout + + + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 20 - 23 undefined + BAD_TRAP; ! 24 cp_disabled + BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 25 - 27 undefined + BAD_TRAP; ! 28 cp_exception + BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 29 - 2B undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 2C - 2F undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 30 - 33 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 34 - 37 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 38 - 3B undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 3C - 3F undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 40 - 43 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 44 - 47 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 48 - 4B undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 4C - 4F undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 50 - 53 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 54 - 57 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 58 - 5B undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 5C - 5F undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 60 - 63 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 64 - 67 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 68 - 6B undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 6C - 6F undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 70 - 73 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 74 - 77 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 78 - 7B undefined + +/* + This is a sad patch to make sure that we know where the + MEC timer control register mirror is so we can stop the timers + from an external debugger. It is needed because the control + register is write-only. Trap 0x7C cannot occure in ERC32... + + We also use this location to store the last location of the + usable RAM in order not to overwrite the remote debugger with + the RTEMS work-space area. + +*/ + + .global __ERC32_MEC_Timer_Control_Mirror, _rdb_start, _CLOCK_SPEED + +_rdb_start: +__ERC32_MEC_Timer_Control_Mirror: + + BAD_TRAP; BAD_TRAP; ! 7C - 7D undefined + +_CLOCK_SPEED: + BAD_TRAP; BAD_TRAP; ! BAD_TRAP; BAD_TRAP; ! 7E - 7F undefined + + /* + * Software traps + * + * NOTE: At the risk of being redundant... this is not a full + * table. The setjmp on the SPARC requires a window flush trap + * handler and RTEMS will preserve the entries that were + * installed before. + */ + + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 80 - 82 + TRAP( 0x83, SYM(window_flush_trap_handler) ); ! 83 flush windows SW trap + + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 84 - 87 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 88 - 8B + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 8C - 8F + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 90 - 93 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 94 - 97 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 98 - 9B + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 9C - 9F + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! A0 - A3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! A4 - A7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! A8 - AB + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! AC - AF + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! B0 - B3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! B4 - B7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! B8 - BB + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! BC - BF + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! C0 - C3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! C4 - C7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! C8 - CB + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! CC - CF + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! D0 - D3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! D4 - D7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! D8 - DB + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! DC - DF + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! E0 - E3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! E4 - E7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! E8 - EB + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! EC - EF + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! F0 - F3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! F4 - F7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! F8 - FB + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! FC - FF + +/* + * This is the hard reset code. + */ + +#define PSR_INIT 0x10c0 /* Disable traps, set s and ps */ +#define WIM_INIT 2 +#define STACK_SIZE 16 * 1024 + + PUBLIC(hard_reset) +SYM(hard_reset): + + set _trap_table, %g1 ! Initialize TBR + mov %g1, %tbr + + set (SYM(rdb_start)), %g6 ! End of work-space area + st %sp, [%g6] + + +/* Check if MEC is initialised. If not, this means that we are + running on the simulator. Initiate some of the parameters + that are done by the boot-prom otherwise. +*/ + + set SYM(ERC32_MEC), %g3 ! g3 = base address of peripherals + ld [%g3], %g2 + set 0xfe080000, %g1 + andcc %g1, %g2, %g0 + bne 1f + set 0x00101000, %g1 ! 2M ROM, 4M RAM + ! set the Memory Configuration + st %g1, [ %g3 + ERC32_MEC_MEMORY_CONFIGURATION_OFFSET ] + + set SYM(RAM_END), %sp ! End of work-space area + st %sp, [%g6] + + set _CLOCK_SPEED, %g6 ! Use 14 MHz in simulator + set 14, %g1 + st %g1, [%g6] + +/* Common initialisation */ +1: + set WIM_INIT, %g1 ! Initialize WIM + mov %g1, %wim + + set PSR_INIT, %g1 + wr %g1, 0x20, %psr ! enable traps + + nop + nop + nop + + sethi %hi(stack_space + STACK_SIZE), %g1 + or %g1,%lo(stack_space + STACK_SIZE),%g1 + ! g1 = top of stack + mov %g1, %sp ! Set stack pointer + mov %sp, %fp ! Set frame pointer + nop + + /* + * Copy the initialized data to RAM + * + * FROM: _endtext + * TO: _data_start + * LENGTH: (__bss_start - _data_start) bytes + */ + + + sethi %hi(_endtext),%g2 + or %g2,%lo(_endtext),%g2 ! g2 = start of initialized data in ROM + + sethi %hi(_data_start),%g3 + or %g3,%lo(_data_start),%g3 ! g3 = start of initialized data in RAM + + sethi %hi(__bss_start),%g4 + or %g4,%lo(__bss_start),%g4 ! g4 = end of initialized data in RAM + + cmp %g2, %g3 + be 1f + nop + +copy_data: + ldd [ %g2 ], %g6 + std %g6 , [ %g3 ] ! copy this double word + add %g3, 8, %g3 ! bump the destination pointer + add %g2, 8, %g2 ! bump the source pointer + cmp %g3, %g4 ! Is the pointer past the end of dest? + bl copy_data + nop + + /* clear the bss */ +1: + + sethi %hi(_edata),%g2 + or %g2,%lo(_edata),%g2 ! g2 = start of bss + sethi %hi(_end),%g3 + or %g3,%lo(_end),%g3 ! g3 = end of bss + mov %g0,%g1 ! so std has two zeros +zerobss: + std %g0,[%g2] + add %g2,8,%g2 + cmp %g2,%g3 + bleu,a zerobss + nop + + mov %0, %o2 ! environ + mov %0, %o1 ! argv + mov %0, %o0 ! argc + call SYM(boot_card) + sub %sp, 0x60, %sp ! room for boot_card to save args + nop + + PUBLIC(BSP_fatal_return) +SYM(BSP_fatal_return): + ta 0 ! Halt if _main returns ... + nop + + /* + * There does not seem to be a way to get this aligned AND + * in the BSS. + */ + + .align 32 + .comm stack_space, STACK_SIZE + +/* end of file */ diff --git a/c/src/lib/libbsp/sparc/erc32/start/startsis.s b/c/src/lib/libbsp/sparc/erc32/start/startsis.s deleted file mode 100644 index 6097c4ab36..0000000000 --- a/c/src/lib/libbsp/sparc/erc32/start/startsis.s +++ /dev/null @@ -1,309 +0,0 @@ -/* - * startsis.s - * - * Start code for the ERC32. - * - * This is based on the file srt0.s provided with the binary - * distribution of the SPARC Instruction Simulator (SIS) found - * at ftp://ftp.estec.esa.nl/pub/ws/wsd/erc32. - * - * $Id$ - */ - -#include -#include - -/* - * Unexpected trap will halt the processor by forcing it to error state - */ - -#define BAD_TRAP \ - ta 0; \ - nop; \ - nop; \ - nop; - -/* - * Software trap. Treat as BAD_TRAP for the time being... - */ - -#define SOFT_TRAP BAD_TRAP - - - .seg "text" - PUBLIC(start) - .global start - -SYM(start): -start: - -/* - * The trap table has to be the first code in a boot PROM. But because - * the Memory Configuration comes up thinking we only have 4K of PROM, we - * cannot have a full trap table and still have room left over to - * reprogram the Memory Configuration register correctly. This file - * uses an abbreviated trap which has every entry which might be used - * before RTEMS installs its own trap table. - */ - - - PUBLIC(trap_table) -SYM(trap_table): - - RTRAP( 0, SYM(hard_reset) ); ! 00 reset trap - BAD_TRAP; ! 01 instruction access - ! exception - BAD_TRAP; ! 02 illegal instruction - BAD_TRAP; ! 03 privileged instruction - BAD_TRAP; ! 04 fp disabled - TRAP( 5, SYM(window_overflow_trap_handler) ); ! 05 window overflow - TRAP( 6, SYM(window_underflow_trap_handler) );! 06 window underflow - BAD_TRAP; ! 07 memory address not aligned - BAD_TRAP; ! 08 fp exception - BAD_TRAP; ! 09 data access exception - BAD_TRAP; ! 0A tag overflow - BAD_TRAP; ! 0B undefined - BAD_TRAP; ! 0C undefined - BAD_TRAP; ! 0D undefined - BAD_TRAP; ! 0E undefined - BAD_TRAP; ! 0F undefined - BAD_TRAP; ! 10 undefined - - /* - * ERC32 defined traps - */ - - BAD_TRAP; ! 11 masked errors - BAD_TRAP; ! 12 external 1 - BAD_TRAP; ! 13 external 2 - BAD_TRAP; ! 14 UART A RX/TX - BAD_TRAP; ! 15 UART B RX/TX - BAD_TRAP; ! 16 correctable memory error - BAD_TRAP; ! 17 UART error - BAD_TRAP; ! 18 DMA access error - BAD_TRAP; ! 19 DMA timeout - BAD_TRAP; ! 1A external 3 - BAD_TRAP; ! 1B external 4 - BAD_TRAP; ! 1C general purpose timer - BAD_TRAP; ! 1D real time clock - BAD_TRAP; ! 1E external 5 - BAD_TRAP; ! 1F watchdog timeout - - - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 20 - 23 undefined - BAD_TRAP; ! 24 cp_disabled - BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 25 - 27 undefined - BAD_TRAP; ! 28 cp_exception - BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 29 - 2B undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 2C - 2F undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 30 - 33 undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 34 - 37 undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 38 - 3B undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 3C - 3F undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 40 - 43 undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 44 - 47 undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 48 - 4B undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 4C - 4F undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 50 - 53 undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 54 - 57 undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 58 - 5B undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 5C - 5F undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 60 - 63 undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 64 - 67 undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 68 - 6B undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 6C - 6F undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 70 - 73 undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 74 - 77 undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 78 - 7B undefined - -/* - This is a sad patch to make sure that we know where the - MEC timer control register mirror is so we can stop the timers - from an external debugger. It is needed because the control - register is write-only. Trap 0x7C cannot occure in ERC32... - - We also use this location to store the last location of the - usable RAM in order not to overwrite the remote debugger with - the RTEMS work-space area. - -*/ - - .global __ERC32_MEC_Timer_Control_Mirror, _rdb_start, _CLOCK_SPEED - -_rdb_start: -__ERC32_MEC_Timer_Control_Mirror: - - BAD_TRAP; BAD_TRAP; ! 7C - 7D undefined - -_CLOCK_SPEED: - BAD_TRAP; BAD_TRAP; ! BAD_TRAP; BAD_TRAP; ! 7E - 7F undefined - - /* - * Software traps - * - * NOTE: At the risk of being redundant... this is not a full - * table. The setjmp on the SPARC requires a window flush trap - * handler and RTEMS will preserve the entries that were - * installed before. - */ - - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 80 - 82 - TRAP( 0x83, SYM(window_flush_trap_handler) ); ! 83 flush windows SW trap - - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 84 - 87 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 88 - 8B - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 8C - 8F - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 90 - 93 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 94 - 97 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 98 - 9B - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 9C - 9F - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! A0 - A3 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! A4 - A7 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! A8 - AB - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! AC - AF - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! B0 - B3 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! B4 - B7 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! B8 - BB - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! BC - BF - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! C0 - C3 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! C4 - C7 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! C8 - CB - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! CC - CF - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! D0 - D3 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! D4 - D7 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! D8 - DB - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! DC - DF - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! E0 - E3 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! E4 - E7 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! E8 - EB - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! EC - EF - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! F0 - F3 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! F4 - F7 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! F8 - FB - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! FC - FF - -/* - * This is the hard reset code. - */ - -#define PSR_INIT 0x10c0 /* Disable traps, set s and ps */ -#define WIM_INIT 2 -#define STACK_SIZE 16 * 1024 - - PUBLIC(hard_reset) -SYM(hard_reset): - - set _trap_table, %g1 ! Initialize TBR - mov %g1, %tbr - - set (SYM(rdb_start)), %g6 ! End of work-space area - st %sp, [%g6] - - -/* Check if MEC is initialised. If not, this means that we are - running on the simulator. Initiate some of the parameters - that are done by the boot-prom otherwise. -*/ - - set SYM(ERC32_MEC), %g3 ! g3 = base address of peripherals - ld [%g3], %g2 - set 0xfe080000, %g1 - andcc %g1, %g2, %g0 - bne 1f - set 0x00101000, %g1 ! 2M ROM, 4M RAM - ! set the Memory Configuration - st %g1, [ %g3 + ERC32_MEC_MEMORY_CONFIGURATION_OFFSET ] - - set SYM(RAM_END), %sp ! End of work-space area - st %sp, [%g6] - - set _CLOCK_SPEED, %g6 ! Use 14 MHz in simulator - set 14, %g1 - st %g1, [%g6] - -/* Common initialisation */ -1: - set WIM_INIT, %g1 ! Initialize WIM - mov %g1, %wim - - set PSR_INIT, %g1 - wr %g1, 0x20, %psr ! enable traps - - nop - nop - nop - - sethi %hi(stack_space + STACK_SIZE), %g1 - or %g1,%lo(stack_space + STACK_SIZE),%g1 - ! g1 = top of stack - mov %g1, %sp ! Set stack pointer - mov %sp, %fp ! Set frame pointer - nop - - /* - * Copy the initialized data to RAM - * - * FROM: _endtext - * TO: _data_start - * LENGTH: (__bss_start - _data_start) bytes - */ - - - sethi %hi(_endtext),%g2 - or %g2,%lo(_endtext),%g2 ! g2 = start of initialized data in ROM - - sethi %hi(_data_start),%g3 - or %g3,%lo(_data_start),%g3 ! g3 = start of initialized data in RAM - - sethi %hi(__bss_start),%g4 - or %g4,%lo(__bss_start),%g4 ! g4 = end of initialized data in RAM - - cmp %g2, %g3 - be 1f - nop - -copy_data: - ldd [ %g2 ], %g6 - std %g6 , [ %g3 ] ! copy this double word - add %g3, 8, %g3 ! bump the destination pointer - add %g2, 8, %g2 ! bump the source pointer - cmp %g3, %g4 ! Is the pointer past the end of dest? - bl copy_data - nop - - /* clear the bss */ -1: - - sethi %hi(_edata),%g2 - or %g2,%lo(_edata),%g2 ! g2 = start of bss - sethi %hi(_end),%g3 - or %g3,%lo(_end),%g3 ! g3 = end of bss - mov %g0,%g1 ! so std has two zeros -zerobss: - std %g0,[%g2] - add %g2,8,%g2 - cmp %g2,%g3 - bleu,a zerobss - nop - - mov %0, %o2 ! environ - mov %0, %o1 ! argv - mov %0, %o0 ! argc - call SYM(boot_card) - sub %sp, 0x60, %sp ! room for boot_card to save args - nop - - PUBLIC(BSP_fatal_return) -SYM(BSP_fatal_return): - ta 0 ! Halt if _main returns ... - nop - - /* - * There does not seem to be a way to get this aligned AND - * in the BSS. - */ - - .align 32 - .comm stack_space, STACK_SIZE - -/* end of file */ diff --git a/c/src/lib/libbsp/sparc/erc32/startsis/Makefile.in b/c/src/lib/libbsp/sparc/erc32/startsis/Makefile.in index dbc9cea9e3..0ba183fb83 100644 --- a/c/src/lib/libbsp/sparc/erc32/startsis/Makefile.in +++ b/c/src/lib/libbsp/sparc/erc32/startsis/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=startsis -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/sparc/erc32/startsis/startsis.S b/c/src/lib/libbsp/sparc/erc32/startsis/startsis.S new file mode 100644 index 0000000000..6097c4ab36 --- /dev/null +++ b/c/src/lib/libbsp/sparc/erc32/startsis/startsis.S @@ -0,0 +1,309 @@ +/* + * startsis.s + * + * Start code for the ERC32. + * + * This is based on the file srt0.s provided with the binary + * distribution of the SPARC Instruction Simulator (SIS) found + * at ftp://ftp.estec.esa.nl/pub/ws/wsd/erc32. + * + * $Id$ + */ + +#include +#include + +/* + * Unexpected trap will halt the processor by forcing it to error state + */ + +#define BAD_TRAP \ + ta 0; \ + nop; \ + nop; \ + nop; + +/* + * Software trap. Treat as BAD_TRAP for the time being... + */ + +#define SOFT_TRAP BAD_TRAP + + + .seg "text" + PUBLIC(start) + .global start + +SYM(start): +start: + +/* + * The trap table has to be the first code in a boot PROM. But because + * the Memory Configuration comes up thinking we only have 4K of PROM, we + * cannot have a full trap table and still have room left over to + * reprogram the Memory Configuration register correctly. This file + * uses an abbreviated trap which has every entry which might be used + * before RTEMS installs its own trap table. + */ + + + PUBLIC(trap_table) +SYM(trap_table): + + RTRAP( 0, SYM(hard_reset) ); ! 00 reset trap + BAD_TRAP; ! 01 instruction access + ! exception + BAD_TRAP; ! 02 illegal instruction + BAD_TRAP; ! 03 privileged instruction + BAD_TRAP; ! 04 fp disabled + TRAP( 5, SYM(window_overflow_trap_handler) ); ! 05 window overflow + TRAP( 6, SYM(window_underflow_trap_handler) );! 06 window underflow + BAD_TRAP; ! 07 memory address not aligned + BAD_TRAP; ! 08 fp exception + BAD_TRAP; ! 09 data access exception + BAD_TRAP; ! 0A tag overflow + BAD_TRAP; ! 0B undefined + BAD_TRAP; ! 0C undefined + BAD_TRAP; ! 0D undefined + BAD_TRAP; ! 0E undefined + BAD_TRAP; ! 0F undefined + BAD_TRAP; ! 10 undefined + + /* + * ERC32 defined traps + */ + + BAD_TRAP; ! 11 masked errors + BAD_TRAP; ! 12 external 1 + BAD_TRAP; ! 13 external 2 + BAD_TRAP; ! 14 UART A RX/TX + BAD_TRAP; ! 15 UART B RX/TX + BAD_TRAP; ! 16 correctable memory error + BAD_TRAP; ! 17 UART error + BAD_TRAP; ! 18 DMA access error + BAD_TRAP; ! 19 DMA timeout + BAD_TRAP; ! 1A external 3 + BAD_TRAP; ! 1B external 4 + BAD_TRAP; ! 1C general purpose timer + BAD_TRAP; ! 1D real time clock + BAD_TRAP; ! 1E external 5 + BAD_TRAP; ! 1F watchdog timeout + + + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 20 - 23 undefined + BAD_TRAP; ! 24 cp_disabled + BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 25 - 27 undefined + BAD_TRAP; ! 28 cp_exception + BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 29 - 2B undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 2C - 2F undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 30 - 33 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 34 - 37 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 38 - 3B undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 3C - 3F undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 40 - 43 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 44 - 47 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 48 - 4B undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 4C - 4F undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 50 - 53 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 54 - 57 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 58 - 5B undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 5C - 5F undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 60 - 63 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 64 - 67 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 68 - 6B undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 6C - 6F undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 70 - 73 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 74 - 77 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 78 - 7B undefined + +/* + This is a sad patch to make sure that we know where the + MEC timer control register mirror is so we can stop the timers + from an external debugger. It is needed because the control + register is write-only. Trap 0x7C cannot occure in ERC32... + + We also use this location to store the last location of the + usable RAM in order not to overwrite the remote debugger with + the RTEMS work-space area. + +*/ + + .global __ERC32_MEC_Timer_Control_Mirror, _rdb_start, _CLOCK_SPEED + +_rdb_start: +__ERC32_MEC_Timer_Control_Mirror: + + BAD_TRAP; BAD_TRAP; ! 7C - 7D undefined + +_CLOCK_SPEED: + BAD_TRAP; BAD_TRAP; ! BAD_TRAP; BAD_TRAP; ! 7E - 7F undefined + + /* + * Software traps + * + * NOTE: At the risk of being redundant... this is not a full + * table. The setjmp on the SPARC requires a window flush trap + * handler and RTEMS will preserve the entries that were + * installed before. + */ + + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 80 - 82 + TRAP( 0x83, SYM(window_flush_trap_handler) ); ! 83 flush windows SW trap + + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 84 - 87 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 88 - 8B + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 8C - 8F + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 90 - 93 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 94 - 97 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 98 - 9B + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 9C - 9F + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! A0 - A3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! A4 - A7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! A8 - AB + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! AC - AF + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! B0 - B3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! B4 - B7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! B8 - BB + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! BC - BF + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! C0 - C3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! C4 - C7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! C8 - CB + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! CC - CF + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! D0 - D3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! D4 - D7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! D8 - DB + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! DC - DF + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! E0 - E3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! E4 - E7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! E8 - EB + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! EC - EF + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! F0 - F3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! F4 - F7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! F8 - FB + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! FC - FF + +/* + * This is the hard reset code. + */ + +#define PSR_INIT 0x10c0 /* Disable traps, set s and ps */ +#define WIM_INIT 2 +#define STACK_SIZE 16 * 1024 + + PUBLIC(hard_reset) +SYM(hard_reset): + + set _trap_table, %g1 ! Initialize TBR + mov %g1, %tbr + + set (SYM(rdb_start)), %g6 ! End of work-space area + st %sp, [%g6] + + +/* Check if MEC is initialised. If not, this means that we are + running on the simulator. Initiate some of the parameters + that are done by the boot-prom otherwise. +*/ + + set SYM(ERC32_MEC), %g3 ! g3 = base address of peripherals + ld [%g3], %g2 + set 0xfe080000, %g1 + andcc %g1, %g2, %g0 + bne 1f + set 0x00101000, %g1 ! 2M ROM, 4M RAM + ! set the Memory Configuration + st %g1, [ %g3 + ERC32_MEC_MEMORY_CONFIGURATION_OFFSET ] + + set SYM(RAM_END), %sp ! End of work-space area + st %sp, [%g6] + + set _CLOCK_SPEED, %g6 ! Use 14 MHz in simulator + set 14, %g1 + st %g1, [%g6] + +/* Common initialisation */ +1: + set WIM_INIT, %g1 ! Initialize WIM + mov %g1, %wim + + set PSR_INIT, %g1 + wr %g1, 0x20, %psr ! enable traps + + nop + nop + nop + + sethi %hi(stack_space + STACK_SIZE), %g1 + or %g1,%lo(stack_space + STACK_SIZE),%g1 + ! g1 = top of stack + mov %g1, %sp ! Set stack pointer + mov %sp, %fp ! Set frame pointer + nop + + /* + * Copy the initialized data to RAM + * + * FROM: _endtext + * TO: _data_start + * LENGTH: (__bss_start - _data_start) bytes + */ + + + sethi %hi(_endtext),%g2 + or %g2,%lo(_endtext),%g2 ! g2 = start of initialized data in ROM + + sethi %hi(_data_start),%g3 + or %g3,%lo(_data_start),%g3 ! g3 = start of initialized data in RAM + + sethi %hi(__bss_start),%g4 + or %g4,%lo(__bss_start),%g4 ! g4 = end of initialized data in RAM + + cmp %g2, %g3 + be 1f + nop + +copy_data: + ldd [ %g2 ], %g6 + std %g6 , [ %g3 ] ! copy this double word + add %g3, 8, %g3 ! bump the destination pointer + add %g2, 8, %g2 ! bump the source pointer + cmp %g3, %g4 ! Is the pointer past the end of dest? + bl copy_data + nop + + /* clear the bss */ +1: + + sethi %hi(_edata),%g2 + or %g2,%lo(_edata),%g2 ! g2 = start of bss + sethi %hi(_end),%g3 + or %g3,%lo(_end),%g3 ! g3 = end of bss + mov %g0,%g1 ! so std has two zeros +zerobss: + std %g0,[%g2] + add %g2,8,%g2 + cmp %g2,%g3 + bleu,a zerobss + nop + + mov %0, %o2 ! environ + mov %0, %o1 ! argv + mov %0, %o0 ! argc + call SYM(boot_card) + sub %sp, 0x60, %sp ! room for boot_card to save args + nop + + PUBLIC(BSP_fatal_return) +SYM(BSP_fatal_return): + ta 0 ! Halt if _main returns ... + nop + + /* + * There does not seem to be a way to get this aligned AND + * in the BSS. + */ + + .align 32 + .comm stack_space, STACK_SIZE + +/* end of file */ diff --git a/c/src/lib/libbsp/sparc/erc32/startsis/startsis.s b/c/src/lib/libbsp/sparc/erc32/startsis/startsis.s deleted file mode 100644 index 6097c4ab36..0000000000 --- a/c/src/lib/libbsp/sparc/erc32/startsis/startsis.s +++ /dev/null @@ -1,309 +0,0 @@ -/* - * startsis.s - * - * Start code for the ERC32. - * - * This is based on the file srt0.s provided with the binary - * distribution of the SPARC Instruction Simulator (SIS) found - * at ftp://ftp.estec.esa.nl/pub/ws/wsd/erc32. - * - * $Id$ - */ - -#include -#include - -/* - * Unexpected trap will halt the processor by forcing it to error state - */ - -#define BAD_TRAP \ - ta 0; \ - nop; \ - nop; \ - nop; - -/* - * Software trap. Treat as BAD_TRAP for the time being... - */ - -#define SOFT_TRAP BAD_TRAP - - - .seg "text" - PUBLIC(start) - .global start - -SYM(start): -start: - -/* - * The trap table has to be the first code in a boot PROM. But because - * the Memory Configuration comes up thinking we only have 4K of PROM, we - * cannot have a full trap table and still have room left over to - * reprogram the Memory Configuration register correctly. This file - * uses an abbreviated trap which has every entry which might be used - * before RTEMS installs its own trap table. - */ - - - PUBLIC(trap_table) -SYM(trap_table): - - RTRAP( 0, SYM(hard_reset) ); ! 00 reset trap - BAD_TRAP; ! 01 instruction access - ! exception - BAD_TRAP; ! 02 illegal instruction - BAD_TRAP; ! 03 privileged instruction - BAD_TRAP; ! 04 fp disabled - TRAP( 5, SYM(window_overflow_trap_handler) ); ! 05 window overflow - TRAP( 6, SYM(window_underflow_trap_handler) );! 06 window underflow - BAD_TRAP; ! 07 memory address not aligned - BAD_TRAP; ! 08 fp exception - BAD_TRAP; ! 09 data access exception - BAD_TRAP; ! 0A tag overflow - BAD_TRAP; ! 0B undefined - BAD_TRAP; ! 0C undefined - BAD_TRAP; ! 0D undefined - BAD_TRAP; ! 0E undefined - BAD_TRAP; ! 0F undefined - BAD_TRAP; ! 10 undefined - - /* - * ERC32 defined traps - */ - - BAD_TRAP; ! 11 masked errors - BAD_TRAP; ! 12 external 1 - BAD_TRAP; ! 13 external 2 - BAD_TRAP; ! 14 UART A RX/TX - BAD_TRAP; ! 15 UART B RX/TX - BAD_TRAP; ! 16 correctable memory error - BAD_TRAP; ! 17 UART error - BAD_TRAP; ! 18 DMA access error - BAD_TRAP; ! 19 DMA timeout - BAD_TRAP; ! 1A external 3 - BAD_TRAP; ! 1B external 4 - BAD_TRAP; ! 1C general purpose timer - BAD_TRAP; ! 1D real time clock - BAD_TRAP; ! 1E external 5 - BAD_TRAP; ! 1F watchdog timeout - - - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 20 - 23 undefined - BAD_TRAP; ! 24 cp_disabled - BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 25 - 27 undefined - BAD_TRAP; ! 28 cp_exception - BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 29 - 2B undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 2C - 2F undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 30 - 33 undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 34 - 37 undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 38 - 3B undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 3C - 3F undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 40 - 43 undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 44 - 47 undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 48 - 4B undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 4C - 4F undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 50 - 53 undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 54 - 57 undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 58 - 5B undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 5C - 5F undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 60 - 63 undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 64 - 67 undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 68 - 6B undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 6C - 6F undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 70 - 73 undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 74 - 77 undefined - BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 78 - 7B undefined - -/* - This is a sad patch to make sure that we know where the - MEC timer control register mirror is so we can stop the timers - from an external debugger. It is needed because the control - register is write-only. Trap 0x7C cannot occure in ERC32... - - We also use this location to store the last location of the - usable RAM in order not to overwrite the remote debugger with - the RTEMS work-space area. - -*/ - - .global __ERC32_MEC_Timer_Control_Mirror, _rdb_start, _CLOCK_SPEED - -_rdb_start: -__ERC32_MEC_Timer_Control_Mirror: - - BAD_TRAP; BAD_TRAP; ! 7C - 7D undefined - -_CLOCK_SPEED: - BAD_TRAP; BAD_TRAP; ! BAD_TRAP; BAD_TRAP; ! 7E - 7F undefined - - /* - * Software traps - * - * NOTE: At the risk of being redundant... this is not a full - * table. The setjmp on the SPARC requires a window flush trap - * handler and RTEMS will preserve the entries that were - * installed before. - */ - - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 80 - 82 - TRAP( 0x83, SYM(window_flush_trap_handler) ); ! 83 flush windows SW trap - - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 84 - 87 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 88 - 8B - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 8C - 8F - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 90 - 93 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 94 - 97 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 98 - 9B - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 9C - 9F - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! A0 - A3 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! A4 - A7 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! A8 - AB - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! AC - AF - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! B0 - B3 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! B4 - B7 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! B8 - BB - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! BC - BF - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! C0 - C3 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! C4 - C7 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! C8 - CB - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! CC - CF - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! D0 - D3 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! D4 - D7 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! D8 - DB - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! DC - DF - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! E0 - E3 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! E4 - E7 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! E8 - EB - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! EC - EF - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! F0 - F3 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! F4 - F7 - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! F8 - FB - SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! FC - FF - -/* - * This is the hard reset code. - */ - -#define PSR_INIT 0x10c0 /* Disable traps, set s and ps */ -#define WIM_INIT 2 -#define STACK_SIZE 16 * 1024 - - PUBLIC(hard_reset) -SYM(hard_reset): - - set _trap_table, %g1 ! Initialize TBR - mov %g1, %tbr - - set (SYM(rdb_start)), %g6 ! End of work-space area - st %sp, [%g6] - - -/* Check if MEC is initialised. If not, this means that we are - running on the simulator. Initiate some of the parameters - that are done by the boot-prom otherwise. -*/ - - set SYM(ERC32_MEC), %g3 ! g3 = base address of peripherals - ld [%g3], %g2 - set 0xfe080000, %g1 - andcc %g1, %g2, %g0 - bne 1f - set 0x00101000, %g1 ! 2M ROM, 4M RAM - ! set the Memory Configuration - st %g1, [ %g3 + ERC32_MEC_MEMORY_CONFIGURATION_OFFSET ] - - set SYM(RAM_END), %sp ! End of work-space area - st %sp, [%g6] - - set _CLOCK_SPEED, %g6 ! Use 14 MHz in simulator - set 14, %g1 - st %g1, [%g6] - -/* Common initialisation */ -1: - set WIM_INIT, %g1 ! Initialize WIM - mov %g1, %wim - - set PSR_INIT, %g1 - wr %g1, 0x20, %psr ! enable traps - - nop - nop - nop - - sethi %hi(stack_space + STACK_SIZE), %g1 - or %g1,%lo(stack_space + STACK_SIZE),%g1 - ! g1 = top of stack - mov %g1, %sp ! Set stack pointer - mov %sp, %fp ! Set frame pointer - nop - - /* - * Copy the initialized data to RAM - * - * FROM: _endtext - * TO: _data_start - * LENGTH: (__bss_start - _data_start) bytes - */ - - - sethi %hi(_endtext),%g2 - or %g2,%lo(_endtext),%g2 ! g2 = start of initialized data in ROM - - sethi %hi(_data_start),%g3 - or %g3,%lo(_data_start),%g3 ! g3 = start of initialized data in RAM - - sethi %hi(__bss_start),%g4 - or %g4,%lo(__bss_start),%g4 ! g4 = end of initialized data in RAM - - cmp %g2, %g3 - be 1f - nop - -copy_data: - ldd [ %g2 ], %g6 - std %g6 , [ %g3 ] ! copy this double word - add %g3, 8, %g3 ! bump the destination pointer - add %g2, 8, %g2 ! bump the source pointer - cmp %g3, %g4 ! Is the pointer past the end of dest? - bl copy_data - nop - - /* clear the bss */ -1: - - sethi %hi(_edata),%g2 - or %g2,%lo(_edata),%g2 ! g2 = start of bss - sethi %hi(_end),%g3 - or %g3,%lo(_end),%g3 ! g3 = end of bss - mov %g0,%g1 ! so std has two zeros -zerobss: - std %g0,[%g2] - add %g2,8,%g2 - cmp %g2,%g3 - bleu,a zerobss - nop - - mov %0, %o2 ! environ - mov %0, %o1 ! argv - mov %0, %o0 ! argc - call SYM(boot_card) - sub %sp, 0x60, %sp ! room for boot_card to save args - nop - - PUBLIC(BSP_fatal_return) -SYM(BSP_fatal_return): - ta 0 ! Halt if _main returns ... - nop - - /* - * There does not seem to be a way to get this aligned AND - * in the BSS. - */ - - .align 32 - .comm stack_space, STACK_SIZE - -/* end of file */ diff --git a/c/src/lib/libbsp/sparc/erc32/timer/Makefile.in b/c/src/lib/libbsp/sparc/erc32/timer/Makefile.in index 16665e4de9..0ac1995395 100644 --- a/c/src/lib/libbsp/sparc/erc32/timer/Makefile.in +++ b/c/src/lib/libbsp/sparc/erc32/timer/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES= -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/unix/posix/wrapup/Makefile.in b/c/src/lib/libbsp/unix/posix/wrapup/Makefile.in index f2e05eeff6..0dd5e4090d 100644 --- a/c/src/lib/libbsp/unix/posix/wrapup/Makefile.in +++ b/c/src/lib/libbsp/unix/posix/wrapup/Makefile.in @@ -8,21 +8,18 @@ VPATH = @srcdir@ RTEMS_ROOT = @top_srcdir@ PROJECT_ROOT = @PROJECT_ROOT@ -# MP_XXX_PARTS are the pieces of the BSP required in a MP environment -# We only build them if HAS_MP was defined - -MP_BSP_PARTS_yes_V = shmsupp -MP_BSP_PARTS = $(MP_BSP_PARTS_$(HAS_MP)_V) - -MP_GENERIC_PARTS_yes_V = shmdr -MP_GENERIC_PARTS = $(MP_GENERIC_PARTS_$(HAS_MP)_V) - - - -BSP_PIECES=startup clock console $(MP_BSP_PARTS) timer +BSP_PIECES=startup clock console timer # pieces to pick up out of libcpu/unix CPU_PIECES= -GENERIC_PIECES=$(MP_GENERIC_PARTS) +GENERIC_PIECES= + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/lib.cfg + +ifeq ($(HAS_MP),yes) +GENERIC_PIECES += shmdr +BSP_PIECES += shmsupp +endif # bummer; have to use $foreach since % pattern subst rules only replace 1x OBJS=$(foreach piece, $(BSP_PIECES), ../$(piece)/$(ARCH)/$(piece).rel) \ @@ -32,9 +29,6 @@ OBJS=$(foreach piece, $(BSP_PIECES), ../$(piece)/$(ARCH)/$(piece).rel) \ ../../../$(piece)/$(ARCH)/$(piece).rel) LIB=$(ARCH)/libbsp.a -include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg -include $(RTEMS_ROOT)/make/lib.cfg - # # (OPTIONAL) Add local stuff here using += # -- cgit v1.2.3