From 4cf93658eff5cf6b0c02e98a0d1ec33dea5ed85c Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Sat, 27 Jan 2018 14:37:51 +0100 Subject: bsps: Rework cache manager implementation The previous cache manager support used a single souce file (cache_manager.c) which included an implementation header (cache_.h). This required the use of specialized include paths to find the right header file. Change this to include a generic implementation header (cacheimpl.h) in specialized source files. Use the following directories and files: * bsps/shared/cache * bsps/@RTEMS_CPU@/shared/cache * bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILY/start/cache.c Update #3285. --- c/src/lib/libbsp/sparc/erc32/Makefile.am | 3 +- c/src/lib/libbsp/sparc/leon2/Makefile.am | 2 +- c/src/lib/libbsp/sparc/leon3/Makefile.am | 5 +- c/src/lib/libbsp/sparc/leon3/include/cache_.h | 202 -------------------------- 4 files changed, 4 insertions(+), 208 deletions(-) delete mode 100644 c/src/lib/libbsp/sparc/leon3/include/cache_.h (limited to 'c/src/lib/libbsp/sparc') diff --git a/c/src/lib/libbsp/sparc/erc32/Makefile.am b/c/src/lib/libbsp/sparc/erc32/Makefile.am index cb7ee0a34e..52017ba0d6 100644 --- a/c/src/lib/libbsp/sparc/erc32/Makefile.am +++ b/c/src/lib/libbsp/sparc/erc32/Makefile.am @@ -76,9 +76,10 @@ if HAS_NETWORKING libbsp_a_SOURCES += erc32sonic/erc32sonic.c endif +libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c + libbsp_a_LIBADD = \ ../../../libcpu/@RTEMS_CPU@/access.rel \ - ../../../libcpu/@RTEMS_CPU@/cache.rel \ ../../../libcpu/@RTEMS_CPU@/reg_win.rel \ ../../../libcpu/@RTEMS_CPU@/syscall.rel diff --git a/c/src/lib/libbsp/sparc/leon2/Makefile.am b/c/src/lib/libbsp/sparc/leon2/Makefile.am index f7f2fd6937..f2d7e56a4f 100644 --- a/c/src/lib/libbsp/sparc/leon2/Makefile.am +++ b/c/src/lib/libbsp/sparc/leon2/Makefile.am @@ -143,6 +143,7 @@ libbsp_a_SOURCES += ../../sparc/shared/analog/gradcdac.c libbsp_a_SOURCES += ../../sparc/shared/mem/mctrl.c # l2cache libbsp_a_SOURCES += ../../sparc/shared/l2c/l2c.c +libbsp_a_SOURCES += ../../../../../../bsps/sparc/leon2/start/cache.c # griommu libbsp_a_SOURCES += ../../sparc/shared/iommu/griommu.c # timer @@ -177,7 +178,6 @@ endif libbsp_a_LIBADD = \ ../../../libcpu/@RTEMS_CPU@/access.rel \ - ../../../libcpu/@RTEMS_CPU@/cache.rel \ ../../../libcpu/@RTEMS_CPU@/reg_win.rel \ ../../../libcpu/@RTEMS_CPU@/syscall.rel diff --git a/c/src/lib/libbsp/sparc/leon3/Makefile.am b/c/src/lib/libbsp/sparc/leon3/Makefile.am index 2f8480ae97..614a5d5d26 100644 --- a/c/src/lib/libbsp/sparc/leon3/Makefile.am +++ b/c/src/lib/libbsp/sparc/leon3/Makefile.am @@ -155,15 +155,12 @@ libbsp_a_SOURCES += ../../sparc/shared/analog/gradcdac.c libbsp_a_SOURCES += ../../sparc/shared/mem/mctrl.c # l2cache libbsp_a_SOURCES += ../../sparc/shared/l2c/l2c.c +libbsp_a_SOURCES += ../../../../../../bsps/sparc/leon3/start/cache.c # griommu libbsp_a_SOURCES += ../../sparc/shared/iommu/griommu.c # timer libbsp_a_SOURCES += timer/timer.c libbsp_a_SOURCES += timer/watchdog.c -# Cache -libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c -libbsp_a_SOURCES += include/cache_.h -libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/include # GR712 libbsp_a_SOURCES += ../../sparc/shared/ascs/grascs.c diff --git a/c/src/lib/libbsp/sparc/leon3/include/cache_.h b/c/src/lib/libbsp/sparc/leon3/include/cache_.h deleted file mode 100644 index ced5b6dd0a..0000000000 --- a/c/src/lib/libbsp/sparc/leon3/include/cache_.h +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Copyright (c) 2014 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LEON3_CACHE_H -#define LEON3_CACHE_H - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS - -#define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS - -#define CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING - -#define CPU_INSTRUCTION_CACHE_ALIGNMENT 64 - -#define CPU_DATA_CACHE_ALIGNMENT 64 - -static inline volatile struct l2c_regs *get_l2c_regs(void) -{ - volatile struct l2c_regs *l2c = NULL; - struct ambapp_dev *adev; - - adev = (void *) ambapp_for_each( - &ambapp_plb, - OPTIONS_ALL | OPTIONS_AHB_SLVS, - VENDOR_GAISLER, - GAISLER_L2CACHE, - ambapp_find_by_idx, - NULL - ); - if (adev != NULL) { - l2c = (volatile struct l2c_regs *) DEV_TO_AHB(adev)->start[1]; - } - - return l2c; -} - -static inline size_t get_l2_size(void) -{ - size_t size = 0; - volatile struct l2c_regs *l2c = get_l2c_regs(); - - if (l2c != NULL) { - unsigned status = l2c->status; - unsigned ways = (status & 0x3) + 1; - unsigned set_size = ((status & 0x7ff) >> 2) * 1024; - - size = ways * set_size; - } - - return size; -} - -static inline size_t get_l1_size(uint32_t l1_cfg) -{ - uint32_t ways = ((l1_cfg >> 24) & 0x7) + 1; - uint32_t wsize = UINT32_C(1) << (((l1_cfg >> 20) & 0xf) + 10); - - return ways * wsize; -} - -static inline size_t get_max_size(size_t a, size_t b) -{ - return a < b ? b : a; -} - -static inline size_t get_cache_size(uint32_t level, uint32_t l1_cfg) -{ - size_t size; - - switch (level) { - case 0: - size = get_max_size(get_l1_size(l1_cfg), get_l2_size()); - break; - case 1: - size = get_l1_size(l1_cfg); - break; - case 2: - size = get_l2_size(); - break; - default: - size = 0; - break; - } - - return size; -} - -static inline size_t _CPU_cache_get_data_cache_size(uint32_t level) -{ - return get_cache_size(level, leon3_get_data_cache_config_register()); -} - -static inline void _CPU_cache_flush_data_range( - const void *d_addr, - size_t n_bytes -) -{ - /* TODO */ -} - -static inline void _CPU_cache_invalidate_data_range( - const void *d_addr, - size_t n_bytes -) -{ - /* TODO */ -} - -static inline void _CPU_cache_freeze_data(void) -{ - /* TODO */ -} - -static inline void _CPU_cache_unfreeze_data(void) -{ - /* TODO */ -} - -static inline void _CPU_cache_invalidate_entire_instruction(void) -{ - uint32_t cache_reg = leon3_get_cache_control_register(); - - cache_reg |= LEON3_REG_CACHE_CTRL_FI; - leon3_set_cache_control_register(cache_reg); -} - -static inline void _CPU_cache_invalidate_instruction_range( - const void *i_addr, - size_t n_bytes -) -{ - _CPU_cache_invalidate_entire_instruction(); -} - -static inline void _CPU_cache_freeze_instruction(void) -{ - /* TODO */ -} - -static inline void _CPU_cache_unfreeze_instruction(void) -{ - /* TODO */ -} - -static inline void _CPU_cache_flush_entire_data(void) -{ - /* TODO */ -} - -static inline void _CPU_cache_invalidate_entire_data(void) -{ - /* TODO */ -} - -static inline void _CPU_cache_enable_data(void) -{ - /* TODO */ -} - -static inline void _CPU_cache_disable_data(void) -{ - /* TODO */ -} - -static inline size_t _CPU_cache_get_instruction_cache_size( uint32_t level ) -{ - return get_cache_size(level, leon3_get_inst_cache_config_register()); -} - -static inline void _CPU_cache_enable_instruction(void) -{ - /* TODO */ -} - -static inline void _CPU_cache_disable_instruction(void) -{ - /* TODO */ -} - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LEON3_CACHE_H */ -- cgit v1.2.3