From 3bb41226e0941b86d58ecb97f7d292677de573c8 Mon Sep 17 00:00:00 2001 From: Daniel Hellstrom Date: Mon, 23 Feb 2015 13:02:39 +0100 Subject: LEON: added new drivers to the LEON2/LEON3 BSPs Most drivers use the Driver Manager for device probing, they work on AMBA-over-PCI systems if PCI is big-endian. New APIs: * GPIO Library, interfaced to GRGPIO * GENIRQ, Generic interrupt service implementation helper New GRLIB Drivers: * ACTEL 1553 RT, user interface is similar to 1553 BRM driver * GR1553 (1553 BC, RT and BM core) * AHBSTAT (AHB error status core) * GRADCDAC (Core interfacing to ADC/DAC hardware) * GRGPIO (GPIO port accessed from GPIO Library) * MCTRL (Memory controller settings configuration) * GRETH (10/100/1000 Ethernet driver using Driver manager) * GRPWM (Pulse Width Modulation core) * SPICTRL (SPI master interface) * GRSPW_ROUTER (SpaceWire Router AMBA configuration interface) * GRCTM (SpaceCraft on-board Time Management core) * SPWCUC (Time distribution over SpaceWire) * GRTC (SpaceCraft up-link Tele core) * GRTM (SpaceCraft down-link Tele Metry core) GR712RC ASIC specific interfaces: * GRASCS * CANMUX (select between OCCAN and SATCAN) * SATCAN * SLINK --- c/src/lib/libbsp/sparc/shared/include/gr1553b.h | 365 ++++++++++++++++++++++++ 1 file changed, 365 insertions(+) create mode 100644 c/src/lib/libbsp/sparc/shared/include/gr1553b.h (limited to 'c/src/lib/libbsp/sparc/shared/include/gr1553b.h') diff --git a/c/src/lib/libbsp/sparc/shared/include/gr1553b.h b/c/src/lib/libbsp/sparc/shared/include/gr1553b.h new file mode 100644 index 0000000000..33a79bfdb6 --- /dev/null +++ b/c/src/lib/libbsp/sparc/shared/include/gr1553b.h @@ -0,0 +1,365 @@ +/* GR1553B driver, used by BC, RT and/or BM driver + * + * COPYRIGHT (c) 2010. + * Cobham Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * OVERVIEW + * ======== + * This driver controls the GR1553B device regardless of interfaces supported + * (BC, RT and/or BM). The device can be located at an on-chip AMBA or an + * AMBA-over-PCI bus. This driver provides an interface for the BC, RT and BM + * drivers to use. Since the different interfaces are accessed over the same + * register interface on the same core, the other drivers must share a GR1553B + * device. Any combination of interface functionality is supported, but the RT + * and BC functionality can nnot be used simultaneously due to hardware + * limitation. + * + */ + +#ifndef __GR1553B_H__ +#define __GR1553B_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* The GR1553B registers */ +struct gr1553b_regs { + /* Common Registers */ + volatile unsigned int irq; /* 0x00 IRQ register */ + volatile unsigned int imask; /* 0x04 IRQ enable mask */ + int unused0[(0x10-0x08)/4]; + volatile unsigned int hwcfg; /* 0x10 HW config register */ + + int unused1[(0x40-0x14)/4]; /* Padding */ + + /* BC Registers */ + volatile unsigned int bc_stat; /* 0x40 BC status */ + volatile unsigned int bc_ctrl; /* 0x44 BC Action register */ + volatile unsigned int bc_bd; /* 0x48 BC transfer list pointer */ + volatile unsigned int bc_abd; /* 0x4c BC async list pointer */ + volatile unsigned int bc_timer; /* 0x50 BC timer register */ + volatile unsigned int bc_wake; /* 0x54 BC wakeup control register */ + volatile unsigned int bc_irqptr;/* 0x58 BC transfer IRQ pointer */ + volatile unsigned int bc_busmsk;/* 0x5C BC per-RT bus mask register */ + + int unused2[(0x68-0x60)/4]; /* Padding */ + + volatile unsigned int bc_slot; /* 0x48 BC Current BD pointer */ + volatile unsigned int bc_aslot; /* 0x4c BC Current async BD pointer */ + + int unused3[(0x80-0x70)/4]; /* Padding */ + + /* RT Registers */ + volatile unsigned int rt_stat; /* 0x80 RT status */ + volatile unsigned int rt_cfg; /* 0x84 RT config register */ + volatile unsigned int rt_stat2; /* 0x88 RT bus status bits */ + volatile unsigned int rt_statw; /* 0x8c RT status words */ + volatile unsigned int rt_sync; /* 0x90 RT bus synchronize */ + volatile unsigned int rt_tab; /* 0x94 RT subaddress table base */ + volatile unsigned int rt_mcctrl;/* 0x98 RT valid mode code mask */ + int unused4[(0xa4-0x9c)/4]; + volatile unsigned int rt_ttag; /* 0xa4 RT time tag register */ + int unused5; /* 0xa8 RESERVED */ + volatile unsigned int rt_evsz; /* 0xac RT event log end pointer */ + volatile unsigned int rt_evlog; /* 0xb0 RT event log position */ + volatile unsigned int rt_evirq; /* 0xb4 RT event log IRQ position */ + + int unused6[(0xc0-0xb8)/4]; /* Padding */ + + /* BM Registers */ + volatile unsigned int bm_stat; /* 0xc0 BM status */ + volatile unsigned int bm_ctrl; /* 0xc4 BM control register */ + volatile unsigned int bm_adr; /* 0xc8 BM address filter */ + volatile unsigned int bm_subadr;/* 0xcc BM subaddress filter */ + volatile unsigned int bm_mc; /* 0xd0 BM mode code filter */ + volatile unsigned int bm_start; /* 0xd4 BM log start address */ + volatile unsigned int bm_end; /* 0xd8 BM log size/alignment mask */ + volatile unsigned int bm_pos; /* 0xdc BM log position */ + volatile unsigned int bm_ttag; /* 0xe0 BM time tag register */ +}; + +#define GR1553BC_KEY 0x15520000 +#define GR1553RT_KEY 0x15530000 + +/* IRQ Definitions */ +#define GR1553BC_IRQLOG_SIZE 64 +#define GR1553BC_IRQLOG_CNT (GR1553BC_IRQLOG_SIZE/sizeof(uint32_t)) + +/*** IRQ Flag Register ***/ +#define GR1553B_IRQ_BCEV_BIT 0 +#define GR1553B_IRQ_BCD_BIT 1 +#define GR1553B_IRQ_BCWK_BIT 2 +#define GR1553B_IRQ_RTEV_BIT 8 +#define GR1553B_IRQ_RTD_BIT 9 +#define GR1553B_IRQ_RTTE_BIT 10 +#define GR1553B_IRQ_BMD_BIT 16 +#define GR1553B_IRQ_BMTOF_BIT 17 + +#define GR1553B_IRQ_BCEV (1<