From 01629105c2817a59a4f1f05039593f211cf5ddaa Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Mon, 14 Dec 1998 23:15:38 +0000 Subject: Patch from Ralf Corsepius to rename all .s files to .S in conformance with GNU conventions. This is a minor step along the way to supporting automake. --- c/src/lib/libbsp/powerpc/dmv177/clock/Makefile.in | 6 +- c/src/lib/libbsp/powerpc/dmv177/sonic/Makefile.in | 6 +- c/src/lib/libbsp/powerpc/dmv177/start/Makefile.in | 6 +- c/src/lib/libbsp/powerpc/dmv177/start/start.S | 117 +++++ c/src/lib/libbsp/powerpc/dmv177/start/start.s | 117 ----- .../lib/libbsp/powerpc/dmv177/startup/Makefile.in | 6 +- c/src/lib/libbsp/powerpc/dmv177/timer/Makefile.in | 6 +- .../libbsp/powerpc/helas403/dlentry/Makefile.in | 6 +- .../lib/libbsp/powerpc/helas403/dlentry/dlentry.S | 144 +++++++ .../lib/libbsp/powerpc/helas403/dlentry/dlentry.s | 144 ------- .../libbsp/powerpc/helas403/flashentry/Makefile.in | 6 +- .../powerpc/helas403/flashentry/flashentry.S | 469 +++++++++++++++++++++ .../powerpc/helas403/flashentry/flashentry.s | 469 --------------------- .../lib/libbsp/powerpc/papyrus/dlentry/Makefile.in | 6 +- c/src/lib/libbsp/powerpc/papyrus/dlentry/dlentry.S | 251 +++++++++++ c/src/lib/libbsp/powerpc/papyrus/dlentry/dlentry.s | 251 ----------- .../libbsp/powerpc/papyrus/flashentry/Makefile.in | 6 +- .../libbsp/powerpc/papyrus/flashentry/flashentry.S | 289 +++++++++++++ .../libbsp/powerpc/papyrus/flashentry/flashentry.s | 289 ------------- c/src/lib/libbsp/powerpc/psim/clock/Makefile.in | 6 +- c/src/lib/libbsp/powerpc/psim/console/Makefile.in | 6 +- c/src/lib/libbsp/powerpc/psim/console/consupp.S | 33 ++ c/src/lib/libbsp/powerpc/psim/console/consupp.s | 33 -- c/src/lib/libbsp/powerpc/psim/start/Makefile.in | 6 +- c/src/lib/libbsp/powerpc/psim/start/start.S | 106 +++++ c/src/lib/libbsp/powerpc/psim/start/startsim.s | 106 ----- c/src/lib/libbsp/powerpc/psim/startsim/Makefile.in | 6 +- c/src/lib/libbsp/powerpc/psim/startsim/startsim.S | 106 +++++ c/src/lib/libbsp/powerpc/psim/startsim/startsim.s | 106 ----- c/src/lib/libbsp/powerpc/psim/startup/Makefile.in | 6 +- c/src/lib/libbsp/powerpc/psim/timer/Makefile.in | 6 +- c/src/lib/libbsp/powerpc/psim/vectors/Makefile.in | 6 +- c/src/lib/libbsp/powerpc/psim/vectors/align_h.S | 434 +++++++++++++++++++ c/src/lib/libbsp/powerpc/psim/vectors/align_h.s | 434 ------------------- c/src/lib/libbsp/powerpc/psim/vectors/vectors.S | 123 ++++++ c/src/lib/libbsp/powerpc/psim/vectors/vectors.s | 123 ------ c/src/lib/libbsp/powerpc/psim/wrapup/Makefile.in | 6 +- 37 files changed, 2123 insertions(+), 2123 deletions(-) create mode 100644 c/src/lib/libbsp/powerpc/dmv177/start/start.S delete mode 100644 c/src/lib/libbsp/powerpc/dmv177/start/start.s create mode 100644 c/src/lib/libbsp/powerpc/helas403/dlentry/dlentry.S delete mode 100644 c/src/lib/libbsp/powerpc/helas403/dlentry/dlentry.s create mode 100644 c/src/lib/libbsp/powerpc/helas403/flashentry/flashentry.S delete mode 100644 c/src/lib/libbsp/powerpc/helas403/flashentry/flashentry.s create mode 100644 c/src/lib/libbsp/powerpc/papyrus/dlentry/dlentry.S delete mode 100644 c/src/lib/libbsp/powerpc/papyrus/dlentry/dlentry.s create mode 100644 c/src/lib/libbsp/powerpc/papyrus/flashentry/flashentry.S delete mode 100644 c/src/lib/libbsp/powerpc/papyrus/flashentry/flashentry.s create mode 100644 c/src/lib/libbsp/powerpc/psim/console/consupp.S delete mode 100644 c/src/lib/libbsp/powerpc/psim/console/consupp.s create mode 100644 c/src/lib/libbsp/powerpc/psim/start/start.S delete mode 100644 c/src/lib/libbsp/powerpc/psim/start/startsim.s create mode 100644 c/src/lib/libbsp/powerpc/psim/startsim/startsim.S delete mode 100644 c/src/lib/libbsp/powerpc/psim/startsim/startsim.s create mode 100644 c/src/lib/libbsp/powerpc/psim/vectors/align_h.S delete mode 100644 c/src/lib/libbsp/powerpc/psim/vectors/align_h.s create mode 100644 c/src/lib/libbsp/powerpc/psim/vectors/vectors.S delete mode 100644 c/src/lib/libbsp/powerpc/psim/vectors/vectors.s (limited to 'c/src/lib/libbsp/powerpc') diff --git a/c/src/lib/libbsp/powerpc/dmv177/clock/Makefile.in b/c/src/lib/libbsp/powerpc/dmv177/clock/Makefile.in index 7c2cfc0772..8a758fce71 100644 --- a/c/src/lib/libbsp/powerpc/dmv177/clock/Makefile.in +++ b/c/src/lib/libbsp/powerpc/dmv177/clock/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES= -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/powerpc/dmv177/sonic/Makefile.in b/c/src/lib/libbsp/powerpc/dmv177/sonic/Makefile.in index 35cd5ff209..b6c1bed0c4 100644 --- a/c/src/lib/libbsp/powerpc/dmv177/sonic/Makefile.in +++ b/c/src/lib/libbsp/powerpc/dmv177/sonic/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES= -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/powerpc/dmv177/start/Makefile.in b/c/src/lib/libbsp/powerpc/dmv177/start/Makefile.in index cb7d9c07ec..20c3bb77bf 100644 --- a/c/src/lib/libbsp/powerpc/dmv177/start/Makefile.in +++ b/c/src/lib/libbsp/powerpc/dmv177/start/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=start -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/powerpc/dmv177/start/start.S b/c/src/lib/libbsp/powerpc/dmv177/start/start.S new file mode 100644 index 0000000000..f8e4e4e614 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/dmv177/start/start.S @@ -0,0 +1,117 @@ +/* + * This is based on the mvme-crt0.S file from libgloss/rs6000. + * crt0.S -- startup file for PowerPC systems. + * + * Copyright (c) 1995 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + * + * $Id$ + */ + +#include +#include "ppc-asm.h" + + .file "start.s" + .section ".got2","aw" + .align 2 + +.LCTOC1 = .+32768 + + .extern FUNC_NAME(atexit) + .globl FUNC_NAME(__atexit) + .section ".sdata","aw" + .align 2 +FUNC_NAME(__atexit): /* tell C's eabi-ctor's we have an atexit function */ + .long FUNC_NAME(atexit)@fixup /* and that it is to register __do_global_dtors */ + + .section ".fixup","aw" + .align 2 + .long FUNC_NAME(__atexit) + + .section ".got2","aw" +.Ltable = .-.LCTOC1 + .long .LCTOC1 /* address we think .LCTOC1 is loaded at */ + +.Lbss_start = .-.LCTOC1 + .long __bss_start + +.Lend = .-.LCTOC1 + .long _end + +.Lstack = .-.LCTOC1 /* stack address if set by user */ + .long __stack + + .text +.Lptr: + .long .LCTOC1-.Laddr + + .globl _start + .type _start,@function +_start: + lis r5,0 + mr r4,r5 + ori r4,r4,0x0000 /* 0x2030 */ + mtmsr r4 + +/* Add special purpose register initialization based upon the console driver + * initialization of these registers XXXXX + */ + + bl .Laddr /* get current address */ + +.Laddr: + mflr r4 /* real address of .Laddr */ + lwz r5,(.Lptr-.Laddr)(r4) /* linker generated address of .LCTOC1 */ + add r5,r5,r4 /* correct to real pointer */ + lwz r4,.Ltable(r5) /* get linker's idea of where .Laddr is */ + subf r4,r4,r5 /* calculate difference between where linked and current */ + + /* clear bss */ + lwz r6,.Lbss_start(r5) /* calculate beginning of the BSS */ + lwz r7,.Lend(r5) /* calculate end of the BSS */ + add r6,r6,r4 /* adjust pointers */ + add r7,r7,r4 + + cmplw 1,r6,r7 + bc 4,4,.Ldone + + subf r8,r6,r7 /* number of bytes to zero */ + srwi r9,r8,2 /* number of words to zero */ + mtctr r9 + li r0,0 /* zero to clear memory */ + addi r6,r6,-4 /* adjust so we can use stwu */ +.Lloop: + stwu r0,4(r6) /* zero bss */ + bdnz .Lloop + +.Ldone: + + lwz r0,.Lstack(r5) /* stack address or 0 */ + cmplwi 1,r0,0 /* equal to 0? */ + bc 12,6,.Lnostack /* use default stack if == 0 */ + mr sp,r0 /* use user defined stack */ + +.Lnostack: + /* set up initial stack frame */ + addi sp,sp,-4 /* make sure we don't overwrite debug mem */ + lis r0,0 + stw r0,0(sp) /* clear back chain */ + stwu sp,-56(sp) /* push another stack frame */ + + /* Let her rip */ + bl FUNC_NAME(boot_card) + + /* return value from boot_card is argument to exit */ + /* bl FUNC_NAME(exit) */ + trap +.Lstart: + .size _start,.Lstart-_start diff --git a/c/src/lib/libbsp/powerpc/dmv177/start/start.s b/c/src/lib/libbsp/powerpc/dmv177/start/start.s deleted file mode 100644 index f8e4e4e614..0000000000 --- a/c/src/lib/libbsp/powerpc/dmv177/start/start.s +++ /dev/null @@ -1,117 +0,0 @@ -/* - * This is based on the mvme-crt0.S file from libgloss/rs6000. - * crt0.S -- startup file for PowerPC systems. - * - * Copyright (c) 1995 Cygnus Support - * - * The authors hereby grant permission to use, copy, modify, distribute, - * and license this software and its documentation for any purpose, provided - * that existing copyright notices are retained in all copies and that this - * notice is included verbatim in any distributions. No written agreement, - * license, or royalty fee is required for any of the authorized uses. - * Modifications to this software may be copyrighted by their authors - * and need not follow the licensing terms described here, provided that - * the new terms are clearly indicated on the first page of each file where - * they apply. - * - * $Id$ - */ - -#include -#include "ppc-asm.h" - - .file "start.s" - .section ".got2","aw" - .align 2 - -.LCTOC1 = .+32768 - - .extern FUNC_NAME(atexit) - .globl FUNC_NAME(__atexit) - .section ".sdata","aw" - .align 2 -FUNC_NAME(__atexit): /* tell C's eabi-ctor's we have an atexit function */ - .long FUNC_NAME(atexit)@fixup /* and that it is to register __do_global_dtors */ - - .section ".fixup","aw" - .align 2 - .long FUNC_NAME(__atexit) - - .section ".got2","aw" -.Ltable = .-.LCTOC1 - .long .LCTOC1 /* address we think .LCTOC1 is loaded at */ - -.Lbss_start = .-.LCTOC1 - .long __bss_start - -.Lend = .-.LCTOC1 - .long _end - -.Lstack = .-.LCTOC1 /* stack address if set by user */ - .long __stack - - .text -.Lptr: - .long .LCTOC1-.Laddr - - .globl _start - .type _start,@function -_start: - lis r5,0 - mr r4,r5 - ori r4,r4,0x0000 /* 0x2030 */ - mtmsr r4 - -/* Add special purpose register initialization based upon the console driver - * initialization of these registers XXXXX - */ - - bl .Laddr /* get current address */ - -.Laddr: - mflr r4 /* real address of .Laddr */ - lwz r5,(.Lptr-.Laddr)(r4) /* linker generated address of .LCTOC1 */ - add r5,r5,r4 /* correct to real pointer */ - lwz r4,.Ltable(r5) /* get linker's idea of where .Laddr is */ - subf r4,r4,r5 /* calculate difference between where linked and current */ - - /* clear bss */ - lwz r6,.Lbss_start(r5) /* calculate beginning of the BSS */ - lwz r7,.Lend(r5) /* calculate end of the BSS */ - add r6,r6,r4 /* adjust pointers */ - add r7,r7,r4 - - cmplw 1,r6,r7 - bc 4,4,.Ldone - - subf r8,r6,r7 /* number of bytes to zero */ - srwi r9,r8,2 /* number of words to zero */ - mtctr r9 - li r0,0 /* zero to clear memory */ - addi r6,r6,-4 /* adjust so we can use stwu */ -.Lloop: - stwu r0,4(r6) /* zero bss */ - bdnz .Lloop - -.Ldone: - - lwz r0,.Lstack(r5) /* stack address or 0 */ - cmplwi 1,r0,0 /* equal to 0? */ - bc 12,6,.Lnostack /* use default stack if == 0 */ - mr sp,r0 /* use user defined stack */ - -.Lnostack: - /* set up initial stack frame */ - addi sp,sp,-4 /* make sure we don't overwrite debug mem */ - lis r0,0 - stw r0,0(sp) /* clear back chain */ - stwu sp,-56(sp) /* push another stack frame */ - - /* Let her rip */ - bl FUNC_NAME(boot_card) - - /* return value from boot_card is argument to exit */ - /* bl FUNC_NAME(exit) */ - trap -.Lstart: - .size _start,.Lstart-_start diff --git a/c/src/lib/libbsp/powerpc/dmv177/startup/Makefile.in b/c/src/lib/libbsp/powerpc/dmv177/startup/Makefile.in index 0877918685..277f30b51c 100644 --- a/c/src/lib/libbsp/powerpc/dmv177/startup/Makefile.in +++ b/c/src/lib/libbsp/powerpc/dmv177/startup/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES= -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=linkcmds $(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/powerpc/dmv177/timer/Makefile.in b/c/src/lib/libbsp/powerpc/dmv177/timer/Makefile.in index 16665e4de9..0ac1995395 100644 --- a/c/src/lib/libbsp/powerpc/dmv177/timer/Makefile.in +++ b/c/src/lib/libbsp/powerpc/dmv177/timer/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES= -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/powerpc/helas403/dlentry/Makefile.in b/c/src/lib/libbsp/powerpc/helas403/dlentry/Makefile.in index dc40c405f6..5ecb9eaef8 100644 --- a/c/src/lib/libbsp/powerpc/helas403/dlentry/Makefile.in +++ b/c/src/lib/libbsp/powerpc/helas403/dlentry/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=dlentry -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/powerpc/helas403/dlentry/dlentry.S b/c/src/lib/libbsp/powerpc/helas403/dlentry/dlentry.S new file mode 100644 index 0000000000..3944d2bc47 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/helas403/dlentry/dlentry.S @@ -0,0 +1,144 @@ +/* dlentry.s + * + * This file contains the entry code for RTEMS programs starting + * after download to RAM + * + * Author: Thomas Doerfler + * IMD Ingenieurbuero fuer Microcomputertechnik + * + * COPYRIGHT (c) 1998 by IMD + * + * Changes from IMD are covered by the original distributions terms. + * This file has been derived from the papyrus BSP: + * + * This file contains the entry veneer for RTEMS programs + * downloaded to Papyrus. + * + * Author: Andrew Bray + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * $Id$ + */ + +#include "asm.h" + +/* + * The helas403 ELF link scripts support three special sections: + * .entry The actual entry point + * .vectors The section containing the interrupt entry veneers. + */ + +/* + * Downloaded code loads the vectors separately to 0x00000100, + * so .entry can be over 256 bytes. + * + * The other sections are linked in the following order: + * .entry + * .text + * .data + * .bss + * see linker command file for section placement + * + * The initial stack is set to stack.end + * + * All the entry veneer has to do is to clear the BSS. + */ + +/* + * GDB likes to have debugging information for the entry veneer. + * Here was some DWARF information. IMD removed it, because we + * could not check, whether it was still correct. Sorry. + + */ + +#if PPC_ASM == PPC_ASM_ELF + .section .entry +#else + .csect .text[PR] +#endif + + PUBLIC_VAR (download_entry) +SYM(download_entry): + bl .startup +base_addr: + +/*--------------------------------------------------------------------------- + * Parameters from linker + *--------------------------------------------------------------------------*/ +toc_pointer: +#if PPC_ASM == PPC_ASM_ELF + .long s.got +#else + .long TOC[tc0] +#endif +bss_length: + .long bss.size +bss_addr: + .long bss.start +stack_top: + .long stack.end +/*--------------------------------------------------------------------------- + * Reset_entry. + *--------------------------------------------------------------------------*/ +.startup: + /* Get start address, stack grows down from here... */ + mflr r1 + + /* Assume Bank regs set up..., cache etc. */ + bl bssclr + + .extern SYM(__vectors) + + lis r2,__vectors@h /* set EVPR exc. vector prefix */ + mtspr evpr,r2 + + /*------------------------------------------------------------------- + * C_setup. + *------------------------------------------------------------------*/ + lwz r2,toc_pointer-base_addr(r1) /* set r2 to toc */ + lwz r1,stack_top-base_addr(r1) /* set r1 to stack_top */ + + addi r1,r1,-56-4 /* start stack at text_addr - 56 */ + addi r3,r0,0x0 /* clear r3 */ + stw r3, 0(r1) /* Clear stack chain */ + stw r3, 4(r1) + stw r3, 8(r1) + stw r3, 12(r1) + .extern SYM (boot_card) + b SYM (boot_card) /* call the first C routine */ + +/*--------------------------------------------------------------------------- + * bssclr. + *--------------------------------------------------------------------------*/ +bssclr: + /*------------------------------------------------------------------- + * Data move finished, zero out bss. + *------------------------------------------------------------------*/ + lwz r2,bss_addr-base_addr(r1) /* start of bss set by loader */ + lwz r3,bss_length-base_addr(r1) /* bss length */ + rlwinm. r3,r3,30,0x3FFFFFFF /* form length/4 */ + beqlr /* no bss */ + mtctr r3 /* set ctr reg */ + xor r6,r6,r6 /* r6 = 0 */ +clear_bss: + stswi r6,r2,0x4 /* store r6 */ + addi r2,r2,0x4 /* update r2 */ + bdnz clear_bss /* decrement counter and loop */ + blr /* return */ +.L_text_e: + +#if PPC_ABI == PPC_ABI_POWEROPEN + DESCRIPTOR (startup) +#endif diff --git a/c/src/lib/libbsp/powerpc/helas403/dlentry/dlentry.s b/c/src/lib/libbsp/powerpc/helas403/dlentry/dlentry.s deleted file mode 100644 index 3944d2bc47..0000000000 --- a/c/src/lib/libbsp/powerpc/helas403/dlentry/dlentry.s +++ /dev/null @@ -1,144 +0,0 @@ -/* dlentry.s - * - * This file contains the entry code for RTEMS programs starting - * after download to RAM - * - * Author: Thomas Doerfler - * IMD Ingenieurbuero fuer Microcomputertechnik - * - * COPYRIGHT (c) 1998 by IMD - * - * Changes from IMD are covered by the original distributions terms. - * This file has been derived from the papyrus BSP: - * - * This file contains the entry veneer for RTEMS programs - * downloaded to Papyrus. - * - * Author: Andrew Bray - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * $Id$ - */ - -#include "asm.h" - -/* - * The helas403 ELF link scripts support three special sections: - * .entry The actual entry point - * .vectors The section containing the interrupt entry veneers. - */ - -/* - * Downloaded code loads the vectors separately to 0x00000100, - * so .entry can be over 256 bytes. - * - * The other sections are linked in the following order: - * .entry - * .text - * .data - * .bss - * see linker command file for section placement - * - * The initial stack is set to stack.end - * - * All the entry veneer has to do is to clear the BSS. - */ - -/* - * GDB likes to have debugging information for the entry veneer. - * Here was some DWARF information. IMD removed it, because we - * could not check, whether it was still correct. Sorry. - - */ - -#if PPC_ASM == PPC_ASM_ELF - .section .entry -#else - .csect .text[PR] -#endif - - PUBLIC_VAR (download_entry) -SYM(download_entry): - bl .startup -base_addr: - -/*--------------------------------------------------------------------------- - * Parameters from linker - *--------------------------------------------------------------------------*/ -toc_pointer: -#if PPC_ASM == PPC_ASM_ELF - .long s.got -#else - .long TOC[tc0] -#endif -bss_length: - .long bss.size -bss_addr: - .long bss.start -stack_top: - .long stack.end -/*--------------------------------------------------------------------------- - * Reset_entry. - *--------------------------------------------------------------------------*/ -.startup: - /* Get start address, stack grows down from here... */ - mflr r1 - - /* Assume Bank regs set up..., cache etc. */ - bl bssclr - - .extern SYM(__vectors) - - lis r2,__vectors@h /* set EVPR exc. vector prefix */ - mtspr evpr,r2 - - /*------------------------------------------------------------------- - * C_setup. - *------------------------------------------------------------------*/ - lwz r2,toc_pointer-base_addr(r1) /* set r2 to toc */ - lwz r1,stack_top-base_addr(r1) /* set r1 to stack_top */ - - addi r1,r1,-56-4 /* start stack at text_addr - 56 */ - addi r3,r0,0x0 /* clear r3 */ - stw r3, 0(r1) /* Clear stack chain */ - stw r3, 4(r1) - stw r3, 8(r1) - stw r3, 12(r1) - .extern SYM (boot_card) - b SYM (boot_card) /* call the first C routine */ - -/*--------------------------------------------------------------------------- - * bssclr. - *--------------------------------------------------------------------------*/ -bssclr: - /*------------------------------------------------------------------- - * Data move finished, zero out bss. - *------------------------------------------------------------------*/ - lwz r2,bss_addr-base_addr(r1) /* start of bss set by loader */ - lwz r3,bss_length-base_addr(r1) /* bss length */ - rlwinm. r3,r3,30,0x3FFFFFFF /* form length/4 */ - beqlr /* no bss */ - mtctr r3 /* set ctr reg */ - xor r6,r6,r6 /* r6 = 0 */ -clear_bss: - stswi r6,r2,0x4 /* store r6 */ - addi r2,r2,0x4 /* update r2 */ - bdnz clear_bss /* decrement counter and loop */ - blr /* return */ -.L_text_e: - -#if PPC_ABI == PPC_ABI_POWEROPEN - DESCRIPTOR (startup) -#endif diff --git a/c/src/lib/libbsp/powerpc/helas403/flashentry/Makefile.in b/c/src/lib/libbsp/powerpc/helas403/flashentry/Makefile.in index 683f996472..b56cce2ea8 100644 --- a/c/src/lib/libbsp/powerpc/helas403/flashentry/Makefile.in +++ b/c/src/lib/libbsp/powerpc/helas403/flashentry/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=flashentry -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/powerpc/helas403/flashentry/flashentry.S b/c/src/lib/libbsp/powerpc/helas403/flashentry/flashentry.S new file mode 100644 index 0000000000..133e64e650 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/helas403/flashentry/flashentry.S @@ -0,0 +1,469 @@ +/* flashentry.s + * + * This file contains the entry code for RTEMS programs starting + * directly from Flash. + * + * Author: Thomas Doerfler + * IMD Ingenieurbuero fuer Microcomputertechnik + * + * COPYRIGHT (c) 1998 by IMD + * + * Changes from IMD are covered by the original distributions terms. + * This file has been derived from the papyrus BSP: + * + * This file contains the entry veneer for RTEMS programs + * stored in Papyrus' flash ROM. + * + * Author: Andrew Bray + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * $Id$ + */ + +#include "asm.h" +#include + +/*---------------------------------------------------------------------------- + * Reset_entry. + *---------------------------------------------------------------------------*/ +#if PPC_ASM == PPC_ASM_ELF + .section .reset,"ax",@progbits + /* this section MUST be located at absolute address 0xFFFFFFFC + or last word of EPROM */ +#else + .csect .text[PR] +#endif + + ba flash_entry /* this is the first instruction after reset */ + + .previous + +/*---------------------------------------------------------------------------- + * ROM Vector area. + *---------------------------------------------------------------------------*/ +#if PPC_ASM == PPC_ASM_ELF + .section .entry,"ax",@progbits +#else + .csect .text[PR] +#endif + PUBLIC_VAR (flash_entry) +SYM (flash_entry): + bl .startup /* call startup, link reg points to base_addr */ +base_addr: +/*---------------------------------------------------------------------------- + * Parameters from linker + *---------------------------------------------------------------------------*/ +toc_pointer: +#if PPC_ASM == PPC_ASM_ELF + .long s.got +#else + .long TOC[tc0] +#endif +text_length: + .long text.size +text_addr: + .long text.start +copy_src: + .long copy.src +copy_length: + .long copy.size +copy_dest: + .long copy.dest +bss_length: + .long bss.size +bss_addr: + .long bss.start +stack_top: + .long stack.end + +/*---------------------------------------------------------------------------- + * from Reset_entry. + *---------------------------------------------------------------------------*/ +.startup: + /* Get start address, r1 points to label base_addr */ + mflr r1 + + /* Set up Bank regs, cache etc. */ + /* set up bank register BR0 for Flash-EPROM: + * NOTE: bank size should stay 1MByte, this is standard size + * after RESET + * base addr = Fffxxxxx -> 0b11111111........................ + * bank size = 1 MByte -> 0b........000..................... (std) + * bank use = readonly -> 0b...........01................... + * seq. fill = targ frst-> 0b.............0.................. + * burst mode= enable -> 0b..............1................. + * bus width = 8 bit -> 0b...............00............... + * ready pin = disable -> 0b.................0.............. + * first wait= 2 clocks -> 0b..................0010.......... + * burst wait= 2 clocks -> 0b......................10........ + * CSon time = 0 clocks -> 0b........................0....... + * OEon time = 0 clocks -> 0b.........................0...... + * WBon time = 1 clocks -> 0b..........................1..... + * WBoff time= 0 clocks -> 0b...........................0.... + * Hold time = 1 clocks -> 0b............................001. + * ram type = SRAM(ign)-> 0b...............................1 + * value 0b11111111000010100000101000100011 + * 0x F F 0 A 0 A 2 3 + */ + lis r2,0xFF0A + ori r2,r2,0x0A23 + + mtdcr br0,r2 /* write to DCR BR0 */ + + + /*-------------------------------------------------------------------- + * test various RAM configurations (from big to small per bank) + *------------------------------------------------------------------*/ + /*-------------------------------------------------------------------- + * test RAM config 16 MByte (1x4Mx32Bit) + *------------------------------------------------------------------*/ + /* set up bank register BR7 for DRAM: + * base addr = 000xxxxx -> 0b00000000........................ + * bank size = 16MByte -> 0b........100..................... + * bank use = readwrite-> 0b...........11................... + * seq. fill = targ.frst-> 0b.............0.................. + * early RAS = disabled -> 0b..............0................. + * bus width = 32bit -> 0b...............10............... + * adr mux = internal -> 0b.................0.............. + * RAS to CAS= 2 clocks -> 0b..................1............. + * Alt. Rfrsh= normal -> 0b...................0............ + * page mode = enabled -> 0b....................1........... + * first wait= 1 clocks -> 0b.....................01......... + * burst wait= 1 clocks -> 0b.......................01....... + * precharge = 1 clocks -> 0b.........................0...... + * RAS Rfrsh = 2 clocks -> 0b..........................1..... + * Rfrsh Itvl= 512 clks -> 0b...........................1000. + * ram type = DRAM -> 0b...............................0 + * value 0b00000000100110010010101010110000 + * 0x 0 0 9 9 2 A B 0 + */ + lis r2,0x0099 + ori r2,r2,0x2AB0 + mtdcr br7,r2 /* write to DCR BR7*/ + + lis r2,0x0000 /* start address = 0x00000000 */ + lis r3,0x0100 /* size 16 MB = 0x01000000 */ + bl ramacc /* test memory accessibility */ + cmpi 0,0,r4,0 /* memory ok? else test smaller size */ + bne ramcfgt18 + + /*-------------------------------------------------------------------- + * test RAM config 32 MByte (2x4Mx32Bit) + *------------------------------------------------------------------*/ + /* set up bank register BR7 like above + * set up bank register BR6 for DRAM: + * base addr = 010xxxxx -> 0b00010000........................ + * bank size = 16MByte -> 0b........100..................... (for now) + * bank use = readwrite-> 0b...........11................... + * seq. fill = targ.frst-> 0b.............0.................. + * early RAS = disabled -> 0b..............0................. + * bus width = 32bit -> 0b...............10............... + * adr mux = internal -> 0b.................0.............. + * RAS to CAS= 2 clocks -> 0b..................1............. + * Alt. Rfrsh= normal -> 0b...................0............ + * page mode = enabled -> 0b....................1........... + * first wait= 1 clocks -> 0b.....................01......... + * burst wait= 1 clocks -> 0b.......................01....... + * precharge = 1 clocks -> 0b.........................0...... + * RAS Rfrsh = 2 clocks -> 0b..........................1..... + * Rfrsh Itvl= 512 clks -> 0b...........................1000. + * ram type = DRAM -> 0b...............................0 + * value 0b00010000100110010010101010110000 + * 0x 1 0 9 9 2 A B 0 + */ + lis r2,0x1099 + ori r2,r2,0x2AB0 + mtdcr br6,r2 /* write to DCR BR6*/ + + lis r2,0x0100 /* start address = 0x01000000 */ + lis r3,0x0100 /* size 16 MB = 0x01000000 */ + bl ramacc /* test memory accessibility */ + cmpi 0,0,r4,0 /* memory ok? else test smaller size */ + beq ramcfgok /* ok, we found configuration... +/ + + lis r2,0x0000 /* disable BR6, config not ok */ + mtdcr br6,r2 /* write to DCR BR6*/ + b ramcfgok /* and finish configuration */ + +ramcfgt18: + /*-------------------------------------------------------------------- + * test RAM config 8 MByte (1x2Mx32Bit) + *------------------------------------------------------------------*/ + /* set up bank register BR7 for DRAM: + * base addr = 000xxxxx -> 0b00000000........................ + * bank size = 8MByte -> 0b........011..................... + * bank use = readwrite-> 0b...........11................... + * seq. fill = targ.frst-> 0b.............0.................. + * early RAS = disabled -> 0b..............0................. + * bus width = 32bit -> 0b...............10............... + * adr mux = internal -> 0b.................0.............. + * RAS to CAS= 2 clocks -> 0b..................1............. + * Alt. Rfrsh= normal -> 0b...................0............ + * page mode = enabled -> 0b....................1........... + * first wait= 1 clocks -> 0b.....................01......... + * burst wait= 1 clocks -> 0b.......................01....... + * precharge = 1 clocks -> 0b.........................0...... + * RAS Rfrsh = 2 clocks -> 0b..........................1..... + * Rfrsh Itvl= 512 clks -> 0b...........................1000. + * ram type = DRAM -> 0b...............................0 + * value 0b00000000011110010010101010110000 + * 0x 0 0 7 9 2 A B 0 + */ + lis r2,0x0079 + ori r2,r2,0x2AB0 + mtdcr br7,r2 /* write to DCR BR7 */ + + lis r2,0x0000 /* start address = 0x00000000 */ + lis r3,0x0080 /* size 8 MB = 0x00800000 */ + bl ramacc /* test memory accessibility */ + cmpi 0,0,r4,0 /* memory ok? else test smaller size */ + bne ramcfgt14 + + /*-------------------------------------------------------------------- + * test RAM config 16 MByte (2x2Mx32Bit) + *------------------------------------------------------------------*/ + /* set up bank register BR7 like above + * set up bank register BR6 for DRAM: + * base addr = 008xxxxx -> 0b00001000........................ + * bank size = 08MByte -> 0b........011..................... (for now) + * bank use = readwrite-> 0b...........11................... + * seq. fill = targ.frst-> 0b.............0.................. + * early RAS = disabled -> 0b..............0................. + * bus width = 32bit -> 0b...............10............... + * adr mux = internal -> 0b.................0.............. + * RAS to CAS= 2 clocks -> 0b..................1............. + * Alt. Rfrsh= normal -> 0b...................0............ + * page mode = enabled -> 0b....................1........... + * first wait= 1 clocks -> 0b.....................01......... + * burst wait= 1 clocks -> 0b.......................01....... + * precharge = 1 clocks -> 0b.........................0...... + * RAS Rfrsh = 2 clocks -> 0b..........................1..... + * Rfrsh Itvl= 512 clks -> 0b...........................1000. + * ram type = DRAM -> 0b...............................0 + * value 0b00001000011110010010101010110000 + * 0x 0 8 7 9 2 A B 0 + */ + lis r2,0x0879 + ori r2,r2,0x2AB0 + mtdcr br6,r2 /* write to DCR BR6*/ + + lis r2,0x0080 /* start address = 0x00800000 */ + lis r3,0x0080 /* size 8 MB = 0x00800000 */ + bl ramacc /* test memory accessibility */ + cmpi 0,0,r4,0 /* memory ok? else test smaller size */ + beq ramcfgok /* ok, we found configuration... +/ + + lis r2,0x0000 /* disable BR6, config not ok */ + mtdcr br6,r2 /* write to DCR BR6*/ + b ramcfgok /* and finish configuration */ + +ramcfgt14: + /*-------------------------------------------------------------------- + * test RAM config 4 MByte (1x1Mx32Bit) + *------------------------------------------------------------------*/ + /* set up bank register BR7 for DRAM: + * base addr = 000xxxxx -> 0b00000000........................ + * bank size = 4MByte -> 0b........010..................... + * bank use = readwrite-> 0b...........11................... + * seq. fill = targ.frst-> 0b.............0.................. + * early RAS = disabled -> 0b..............0................. + * bus width = 32bit -> 0b...............10............... + * adr mux = internal -> 0b.................0.............. + * RAS to CAS= 2 clocks -> 0b..................1............. + * Alt. Rfrsh= normal -> 0b...................0............ + * page mode = enabled -> 0b....................1........... + * first wait= 1 clocks -> 0b.....................01......... + * burst wait= 1 clocks -> 0b.......................01....... + * precharge = 1 clocks -> 0b.........................0...... + * RAS Rfrsh = 2 clocks -> 0b..........................1..... + * Rfrsh Itvl= 512 clks -> 0b...........................1000. + * ram type = DRAM -> 0b...............................0 + * value 0b00000000010110010010101010110000 + * 0x 0 0 5 9 2 A B 0 + */ + /* + * FIXME: this is the minimum size supported, should test and + * report error, when failed + */ + lis r2,0x0059 + ori r2,r2,0x2AB0 + mtdcr br7,r2 /* write to DCR BR7*/ + + /*-------------------------------------------------------------------- + * test RAM config 8 MByte (2x1Mx32Bit) + *------------------------------------------------------------------*/ + /* set up bank register BR7 like above + * set up bank register BR6 for DRAM: + * base addr = 004xxxxx -> 0b00000100........................ + * bank size = 4MByte -> 0b........010..................... (for now) + * bank use = readwrite-> 0b...........11................... + * seq. fill = targ.frst-> 0b.............0.................. + * early RAS = disabled -> 0b..............0................. + * bus width = 32bit -> 0b...............10............... + * adr mux = internal -> 0b.................0.............. + * RAS to CAS= 2 clocks -> 0b..................1............. + * Alt. Rfrsh= normal -> 0b...................0............ + * page mode = enabled -> 0b....................1........... + * first wait= 1 clocks -> 0b.....................01......... + * burst wait= 1 clocks -> 0b.......................01....... + * precharge = 1 clocks -> 0b.........................0...... + * RAS Rfrsh = 2 clocks -> 0b..........................1..... + * Rfrsh Itvl= 512 clks -> 0b...........................1000. + * ram type = DRAM -> 0b...............................0 + * value 0b00000100010110010010101010110000 + * 0x 0 4 5 9 2 A B 0 + */ + lis r2,0x0459 + ori r2,r2,0x2AB0 + mtdcr br6,r2 /* write to DCR BR6*/ + + lis r2,0x0040 /* start address = 0x00400000 */ + lis r3,0x0040 /* size 4 MB = 0x00400000 */ + bl ramacc /* test memory accessibility */ + cmpi 0,0,r4,0 /* memory ok? else test smaller size */ + beq ramcfgok /* ok, we found configuration... +/ + + lis r2,0x0000 /* disable BR6, config not ok */ + mtdcr br6,r2 /* write to DCR BR6*/ + b ramcfgok /* and finish configuration */ + +ramcfgok: + /*-------------------------------------------------------------------- + * init the DRAM where STACK+ DATA+ BBS will be placed. If this is OK + * we will return here. + *-------------------------------------------------------------------*/ + bl rom2ram + + /* clear caches */ + addi r2,0,PPC_I_CACHE/PPC_CACHE_ALIGNMENT + mtctr r2 /* count the loops needed... */ + xor r2,r2,r2 /* start at adr zero */ +icinvlp: + iccci 0,r2 + addi r2,r2,PPC_CACHE_ALIGNMENT + bdnz icinvlp + + addi r2,r0,PPC_D_CACHE/PPC_CACHE_ALIGNMENT + mtctr r2 /* count the loops needed... */ + xor r2,r2,r2 /* start at adr 0 */ +dcinvlp: + dccci 0,r2 + addi r2,r2,PPC_CACHE_ALIGNMENT + bdnz dcinvlp + /*-------------------------------------------------------------------- + * Enable two 128MB cachable regions. + * FEPROM is cachable at 0xFFF00000..0xFFFFFFFF + * DRAM is cachable at 0x00000000..0x00FFFFFF + * FEPROM is noncachable at 0x7FF00000..0x7FFFFFFF + * DRAM is noncachable at 0x80000000..0x80FFFFFF + *-------------------------------------------------------------------*/ + addis r2,r0,0x8000 + addi r2,r2,0x0001 + + mtspr iccr, r2 /* ICCR */ + mtspr dccr, r2 /* DCCR */ + + .extern SYM(__vectors) + + lis r2,__vectors@h /* set EVPR exc. vector prefix */ + mtspr evpr,r2 + + lis r2,0x0000 + ori r2,r2,0x0000 + mtmsr r2 /* set default msr */ + lis r2,0x0000 /* do not allow critical IRQ */ + ori r2,r2,0x0000 + mtdcr exier, r2 /* disable all external IRQs */ + + addi r2,r0,-1 /* r2 = 0xffffffff */ + mtdcr exisr, r2 /* clear all pendingdisable IRQs */ + + /*-------------------------------------------------------------------- + * C_setup. + *-------------------------------------------------------------------*/ + + lwz r2,toc_pointer-base_addr(r1) /* set r2 to toc */ + lwz r1,stack_top-base_addr(r1) /* set r1 to stack_top */ + + addi r1,r1,-56 /* start stack at data_addr - 56 */ + addi r3,r0,0x0 /* clear r3 */ + stw r3, 0(r1) /* Clear stack chain */ + stw r3, 4(r1) + stw r3, 8(r1) + stw r3, 12(r1) + .extern SYM (boot_card) + b SYM (boot_card) /* call the first C routine */ + +/*---------------------------------------------------------------------------- + * Rom2ram. + *---------------------------------------------------------------------------*/ +rom2ram: + lwz r2,copy_dest-base_addr(r1) /* start of data set by loader */ + lwz r3,copy_length-base_addr(r1) /* data length */ + rlwinm r3,r3,30,0x3FFFFFFF /* form length/4 */ + mtctr r3 /* set ctr reg */ + /*-------------------------------------------------------------------- + * Calculate offset of data in image. + *-------------------------------------------------------------------*/ + lwz r4,copy_src-base_addr(r1) /* get start of copy area */ +move_data: + lswi r6,r4,0x4 /* load r6 */ + stswi r6,r2,0x4 /* store r6 */ + addi r4,r4,0x4 /* update r4 */ + addi r2,r2,0x4 /* update r2 */ + bdnz move_data /* decrement counter and loop */ + /*-------------------------------------------------------------------- + * Data move finished, zero out bss. + *-------------------------------------------------------------------*/ + lwz r2,bss_addr-base_addr(r1) /* start of bss set by loader */ + lwz r3,bss_length-base_addr(r1) /* bss length */ + rlwinm. r3,r3,30,0x3FFFFFFF /* form length/4 */ + beqlr /* no bss */ + mtctr r3 /* set ctr reg */ + xor r6,r6,r6 /* r6 = 0 */ +clear_bss: + stswi r6,r2,0x4 /* store r6 */ + addi r2,r2,0x4 /* update r2 */ + bdnz clear_bss /* decrement counter and loop */ + blr /* return */ + +/*---------------------------------------------------------------------------- + * ramacc test accessibility of RAM + * input: r2 = start address, r3 = length (in byte) + * output: r4 = 0 -> ok, !=0 -> fail + *---------------------------------------------------------------------------*/ +ramacc: + xor r4,r4,r4 /* r4 = 0 */ + stw r4,0(r2) /* init ram at start address */ + addi r4,r0,0x04 /* set start shift */ +ramaccf1: + cmp 0,0,r4,r3 /* compare with length */ + bge ramaccfx /* r4 >= r3? then finished */ + add r5,r4,r2 /* get next address to fill */ + stw r4,0(r5) /* store new pattern */ + add r4,r4,r4 /* r4 = r4*2 */ + b ramaccf1 /* and then next loop */ + +ramaccfx: + lwz r4,0(r2) /* get memory at start adr */ + blr + + +#if PPC_ABI == PPC_ABI_POWEROPEN + DESCRIPTOR (startup) +#endif + + + diff --git a/c/src/lib/libbsp/powerpc/helas403/flashentry/flashentry.s b/c/src/lib/libbsp/powerpc/helas403/flashentry/flashentry.s deleted file mode 100644 index 133e64e650..0000000000 --- a/c/src/lib/libbsp/powerpc/helas403/flashentry/flashentry.s +++ /dev/null @@ -1,469 +0,0 @@ -/* flashentry.s - * - * This file contains the entry code for RTEMS programs starting - * directly from Flash. - * - * Author: Thomas Doerfler - * IMD Ingenieurbuero fuer Microcomputertechnik - * - * COPYRIGHT (c) 1998 by IMD - * - * Changes from IMD are covered by the original distributions terms. - * This file has been derived from the papyrus BSP: - * - * This file contains the entry veneer for RTEMS programs - * stored in Papyrus' flash ROM. - * - * Author: Andrew Bray - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * $Id$ - */ - -#include "asm.h" -#include - -/*---------------------------------------------------------------------------- - * Reset_entry. - *---------------------------------------------------------------------------*/ -#if PPC_ASM == PPC_ASM_ELF - .section .reset,"ax",@progbits - /* this section MUST be located at absolute address 0xFFFFFFFC - or last word of EPROM */ -#else - .csect .text[PR] -#endif - - ba flash_entry /* this is the first instruction after reset */ - - .previous - -/*---------------------------------------------------------------------------- - * ROM Vector area. - *---------------------------------------------------------------------------*/ -#if PPC_ASM == PPC_ASM_ELF - .section .entry,"ax",@progbits -#else - .csect .text[PR] -#endif - PUBLIC_VAR (flash_entry) -SYM (flash_entry): - bl .startup /* call startup, link reg points to base_addr */ -base_addr: -/*---------------------------------------------------------------------------- - * Parameters from linker - *---------------------------------------------------------------------------*/ -toc_pointer: -#if PPC_ASM == PPC_ASM_ELF - .long s.got -#else - .long TOC[tc0] -#endif -text_length: - .long text.size -text_addr: - .long text.start -copy_src: - .long copy.src -copy_length: - .long copy.size -copy_dest: - .long copy.dest -bss_length: - .long bss.size -bss_addr: - .long bss.start -stack_top: - .long stack.end - -/*---------------------------------------------------------------------------- - * from Reset_entry. - *---------------------------------------------------------------------------*/ -.startup: - /* Get start address, r1 points to label base_addr */ - mflr r1 - - /* Set up Bank regs, cache etc. */ - /* set up bank register BR0 for Flash-EPROM: - * NOTE: bank size should stay 1MByte, this is standard size - * after RESET - * base addr = Fffxxxxx -> 0b11111111........................ - * bank size = 1 MByte -> 0b........000..................... (std) - * bank use = readonly -> 0b...........01................... - * seq. fill = targ frst-> 0b.............0.................. - * burst mode= enable -> 0b..............1................. - * bus width = 8 bit -> 0b...............00............... - * ready pin = disable -> 0b.................0.............. - * first wait= 2 clocks -> 0b..................0010.......... - * burst wait= 2 clocks -> 0b......................10........ - * CSon time = 0 clocks -> 0b........................0....... - * OEon time = 0 clocks -> 0b.........................0...... - * WBon time = 1 clocks -> 0b..........................1..... - * WBoff time= 0 clocks -> 0b...........................0.... - * Hold time = 1 clocks -> 0b............................001. - * ram type = SRAM(ign)-> 0b...............................1 - * value 0b11111111000010100000101000100011 - * 0x F F 0 A 0 A 2 3 - */ - lis r2,0xFF0A - ori r2,r2,0x0A23 - - mtdcr br0,r2 /* write to DCR BR0 */ - - - /*-------------------------------------------------------------------- - * test various RAM configurations (from big to small per bank) - *------------------------------------------------------------------*/ - /*-------------------------------------------------------------------- - * test RAM config 16 MByte (1x4Mx32Bit) - *------------------------------------------------------------------*/ - /* set up bank register BR7 for DRAM: - * base addr = 000xxxxx -> 0b00000000........................ - * bank size = 16MByte -> 0b........100..................... - * bank use = readwrite-> 0b...........11................... - * seq. fill = targ.frst-> 0b.............0.................. - * early RAS = disabled -> 0b..............0................. - * bus width = 32bit -> 0b...............10............... - * adr mux = internal -> 0b.................0.............. - * RAS to CAS= 2 clocks -> 0b..................1............. - * Alt. Rfrsh= normal -> 0b...................0............ - * page mode = enabled -> 0b....................1........... - * first wait= 1 clocks -> 0b.....................01......... - * burst wait= 1 clocks -> 0b.......................01....... - * precharge = 1 clocks -> 0b.........................0...... - * RAS Rfrsh = 2 clocks -> 0b..........................1..... - * Rfrsh Itvl= 512 clks -> 0b...........................1000. - * ram type = DRAM -> 0b...............................0 - * value 0b00000000100110010010101010110000 - * 0x 0 0 9 9 2 A B 0 - */ - lis r2,0x0099 - ori r2,r2,0x2AB0 - mtdcr br7,r2 /* write to DCR BR7*/ - - lis r2,0x0000 /* start address = 0x00000000 */ - lis r3,0x0100 /* size 16 MB = 0x01000000 */ - bl ramacc /* test memory accessibility */ - cmpi 0,0,r4,0 /* memory ok? else test smaller size */ - bne ramcfgt18 - - /*-------------------------------------------------------------------- - * test RAM config 32 MByte (2x4Mx32Bit) - *------------------------------------------------------------------*/ - /* set up bank register BR7 like above - * set up bank register BR6 for DRAM: - * base addr = 010xxxxx -> 0b00010000........................ - * bank size = 16MByte -> 0b........100..................... (for now) - * bank use = readwrite-> 0b...........11................... - * seq. fill = targ.frst-> 0b.............0.................. - * early RAS = disabled -> 0b..............0................. - * bus width = 32bit -> 0b...............10............... - * adr mux = internal -> 0b.................0.............. - * RAS to CAS= 2 clocks -> 0b..................1............. - * Alt. Rfrsh= normal -> 0b...................0............ - * page mode = enabled -> 0b....................1........... - * first wait= 1 clocks -> 0b.....................01......... - * burst wait= 1 clocks -> 0b.......................01....... - * precharge = 1 clocks -> 0b.........................0...... - * RAS Rfrsh = 2 clocks -> 0b..........................1..... - * Rfrsh Itvl= 512 clks -> 0b...........................1000. - * ram type = DRAM -> 0b...............................0 - * value 0b00010000100110010010101010110000 - * 0x 1 0 9 9 2 A B 0 - */ - lis r2,0x1099 - ori r2,r2,0x2AB0 - mtdcr br6,r2 /* write to DCR BR6*/ - - lis r2,0x0100 /* start address = 0x01000000 */ - lis r3,0x0100 /* size 16 MB = 0x01000000 */ - bl ramacc /* test memory accessibility */ - cmpi 0,0,r4,0 /* memory ok? else test smaller size */ - beq ramcfgok /* ok, we found configuration... +/ - - lis r2,0x0000 /* disable BR6, config not ok */ - mtdcr br6,r2 /* write to DCR BR6*/ - b ramcfgok /* and finish configuration */ - -ramcfgt18: - /*-------------------------------------------------------------------- - * test RAM config 8 MByte (1x2Mx32Bit) - *------------------------------------------------------------------*/ - /* set up bank register BR7 for DRAM: - * base addr = 000xxxxx -> 0b00000000........................ - * bank size = 8MByte -> 0b........011..................... - * bank use = readwrite-> 0b...........11................... - * seq. fill = targ.frst-> 0b.............0.................. - * early RAS = disabled -> 0b..............0................. - * bus width = 32bit -> 0b...............10............... - * adr mux = internal -> 0b.................0.............. - * RAS to CAS= 2 clocks -> 0b..................1............. - * Alt. Rfrsh= normal -> 0b...................0............ - * page mode = enabled -> 0b....................1........... - * first wait= 1 clocks -> 0b.....................01......... - * burst wait= 1 clocks -> 0b.......................01....... - * precharge = 1 clocks -> 0b.........................0...... - * RAS Rfrsh = 2 clocks -> 0b..........................1..... - * Rfrsh Itvl= 512 clks -> 0b...........................1000. - * ram type = DRAM -> 0b...............................0 - * value 0b00000000011110010010101010110000 - * 0x 0 0 7 9 2 A B 0 - */ - lis r2,0x0079 - ori r2,r2,0x2AB0 - mtdcr br7,r2 /* write to DCR BR7 */ - - lis r2,0x0000 /* start address = 0x00000000 */ - lis r3,0x0080 /* size 8 MB = 0x00800000 */ - bl ramacc /* test memory accessibility */ - cmpi 0,0,r4,0 /* memory ok? else test smaller size */ - bne ramcfgt14 - - /*-------------------------------------------------------------------- - * test RAM config 16 MByte (2x2Mx32Bit) - *------------------------------------------------------------------*/ - /* set up bank register BR7 like above - * set up bank register BR6 for DRAM: - * base addr = 008xxxxx -> 0b00001000........................ - * bank size = 08MByte -> 0b........011..................... (for now) - * bank use = readwrite-> 0b...........11................... - * seq. fill = targ.frst-> 0b.............0.................. - * early RAS = disabled -> 0b..............0................. - * bus width = 32bit -> 0b...............10............... - * adr mux = internal -> 0b.................0.............. - * RAS to CAS= 2 clocks -> 0b..................1............. - * Alt. Rfrsh= normal -> 0b...................0............ - * page mode = enabled -> 0b....................1........... - * first wait= 1 clocks -> 0b.....................01......... - * burst wait= 1 clocks -> 0b.......................01....... - * precharge = 1 clocks -> 0b.........................0...... - * RAS Rfrsh = 2 clocks -> 0b..........................1..... - * Rfrsh Itvl= 512 clks -> 0b...........................1000. - * ram type = DRAM -> 0b...............................0 - * value 0b00001000011110010010101010110000 - * 0x 0 8 7 9 2 A B 0 - */ - lis r2,0x0879 - ori r2,r2,0x2AB0 - mtdcr br6,r2 /* write to DCR BR6*/ - - lis r2,0x0080 /* start address = 0x00800000 */ - lis r3,0x0080 /* size 8 MB = 0x00800000 */ - bl ramacc /* test memory accessibility */ - cmpi 0,0,r4,0 /* memory ok? else test smaller size */ - beq ramcfgok /* ok, we found configuration... +/ - - lis r2,0x0000 /* disable BR6, config not ok */ - mtdcr br6,r2 /* write to DCR BR6*/ - b ramcfgok /* and finish configuration */ - -ramcfgt14: - /*-------------------------------------------------------------------- - * test RAM config 4 MByte (1x1Mx32Bit) - *------------------------------------------------------------------*/ - /* set up bank register BR7 for DRAM: - * base addr = 000xxxxx -> 0b00000000........................ - * bank size = 4MByte -> 0b........010..................... - * bank use = readwrite-> 0b...........11................... - * seq. fill = targ.frst-> 0b.............0.................. - * early RAS = disabled -> 0b..............0................. - * bus width = 32bit -> 0b...............10............... - * adr mux = internal -> 0b.................0.............. - * RAS to CAS= 2 clocks -> 0b..................1............. - * Alt. Rfrsh= normal -> 0b...................0............ - * page mode = enabled -> 0b....................1........... - * first wait= 1 clocks -> 0b.....................01......... - * burst wait= 1 clocks -> 0b.......................01....... - * precharge = 1 clocks -> 0b.........................0...... - * RAS Rfrsh = 2 clocks -> 0b..........................1..... - * Rfrsh Itvl= 512 clks -> 0b...........................1000. - * ram type = DRAM -> 0b...............................0 - * value 0b00000000010110010010101010110000 - * 0x 0 0 5 9 2 A B 0 - */ - /* - * FIXME: this is the minimum size supported, should test and - * report error, when failed - */ - lis r2,0x0059 - ori r2,r2,0x2AB0 - mtdcr br7,r2 /* write to DCR BR7*/ - - /*-------------------------------------------------------------------- - * test RAM config 8 MByte (2x1Mx32Bit) - *------------------------------------------------------------------*/ - /* set up bank register BR7 like above - * set up bank register BR6 for DRAM: - * base addr = 004xxxxx -> 0b00000100........................ - * bank size = 4MByte -> 0b........010..................... (for now) - * bank use = readwrite-> 0b...........11................... - * seq. fill = targ.frst-> 0b.............0.................. - * early RAS = disabled -> 0b..............0................. - * bus width = 32bit -> 0b...............10............... - * adr mux = internal -> 0b.................0.............. - * RAS to CAS= 2 clocks -> 0b..................1............. - * Alt. Rfrsh= normal -> 0b...................0............ - * page mode = enabled -> 0b....................1........... - * first wait= 1 clocks -> 0b.....................01......... - * burst wait= 1 clocks -> 0b.......................01....... - * precharge = 1 clocks -> 0b.........................0...... - * RAS Rfrsh = 2 clocks -> 0b..........................1..... - * Rfrsh Itvl= 512 clks -> 0b...........................1000. - * ram type = DRAM -> 0b...............................0 - * value 0b00000100010110010010101010110000 - * 0x 0 4 5 9 2 A B 0 - */ - lis r2,0x0459 - ori r2,r2,0x2AB0 - mtdcr br6,r2 /* write to DCR BR6*/ - - lis r2,0x0040 /* start address = 0x00400000 */ - lis r3,0x0040 /* size 4 MB = 0x00400000 */ - bl ramacc /* test memory accessibility */ - cmpi 0,0,r4,0 /* memory ok? else test smaller size */ - beq ramcfgok /* ok, we found configuration... +/ - - lis r2,0x0000 /* disable BR6, config not ok */ - mtdcr br6,r2 /* write to DCR BR6*/ - b ramcfgok /* and finish configuration */ - -ramcfgok: - /*-------------------------------------------------------------------- - * init the DRAM where STACK+ DATA+ BBS will be placed. If this is OK - * we will return here. - *-------------------------------------------------------------------*/ - bl rom2ram - - /* clear caches */ - addi r2,0,PPC_I_CACHE/PPC_CACHE_ALIGNMENT - mtctr r2 /* count the loops needed... */ - xor r2,r2,r2 /* start at adr zero */ -icinvlp: - iccci 0,r2 - addi r2,r2,PPC_CACHE_ALIGNMENT - bdnz icinvlp - - addi r2,r0,PPC_D_CACHE/PPC_CACHE_ALIGNMENT - mtctr r2 /* count the loops needed... */ - xor r2,r2,r2 /* start at adr 0 */ -dcinvlp: - dccci 0,r2 - addi r2,r2,PPC_CACHE_ALIGNMENT - bdnz dcinvlp - /*-------------------------------------------------------------------- - * Enable two 128MB cachable regions. - * FEPROM is cachable at 0xFFF00000..0xFFFFFFFF - * DRAM is cachable at 0x00000000..0x00FFFFFF - * FEPROM is noncachable at 0x7FF00000..0x7FFFFFFF - * DRAM is noncachable at 0x80000000..0x80FFFFFF - *-------------------------------------------------------------------*/ - addis r2,r0,0x8000 - addi r2,r2,0x0001 - - mtspr iccr, r2 /* ICCR */ - mtspr dccr, r2 /* DCCR */ - - .extern SYM(__vectors) - - lis r2,__vectors@h /* set EVPR exc. vector prefix */ - mtspr evpr,r2 - - lis r2,0x0000 - ori r2,r2,0x0000 - mtmsr r2 /* set default msr */ - lis r2,0x0000 /* do not allow critical IRQ */ - ori r2,r2,0x0000 - mtdcr exier, r2 /* disable all external IRQs */ - - addi r2,r0,-1 /* r2 = 0xffffffff */ - mtdcr exisr, r2 /* clear all pendingdisable IRQs */ - - /*-------------------------------------------------------------------- - * C_setup. - *-------------------------------------------------------------------*/ - - lwz r2,toc_pointer-base_addr(r1) /* set r2 to toc */ - lwz r1,stack_top-base_addr(r1) /* set r1 to stack_top */ - - addi r1,r1,-56 /* start stack at data_addr - 56 */ - addi r3,r0,0x0 /* clear r3 */ - stw r3, 0(r1) /* Clear stack chain */ - stw r3, 4(r1) - stw r3, 8(r1) - stw r3, 12(r1) - .extern SYM (boot_card) - b SYM (boot_card) /* call the first C routine */ - -/*---------------------------------------------------------------------------- - * Rom2ram. - *---------------------------------------------------------------------------*/ -rom2ram: - lwz r2,copy_dest-base_addr(r1) /* start of data set by loader */ - lwz r3,copy_length-base_addr(r1) /* data length */ - rlwinm r3,r3,30,0x3FFFFFFF /* form length/4 */ - mtctr r3 /* set ctr reg */ - /*-------------------------------------------------------------------- - * Calculate offset of data in image. - *-------------------------------------------------------------------*/ - lwz r4,copy_src-base_addr(r1) /* get start of copy area */ -move_data: - lswi r6,r4,0x4 /* load r6 */ - stswi r6,r2,0x4 /* store r6 */ - addi r4,r4,0x4 /* update r4 */ - addi r2,r2,0x4 /* update r2 */ - bdnz move_data /* decrement counter and loop */ - /*-------------------------------------------------------------------- - * Data move finished, zero out bss. - *-------------------------------------------------------------------*/ - lwz r2,bss_addr-base_addr(r1) /* start of bss set by loader */ - lwz r3,bss_length-base_addr(r1) /* bss length */ - rlwinm. r3,r3,30,0x3FFFFFFF /* form length/4 */ - beqlr /* no bss */ - mtctr r3 /* set ctr reg */ - xor r6,r6,r6 /* r6 = 0 */ -clear_bss: - stswi r6,r2,0x4 /* store r6 */ - addi r2,r2,0x4 /* update r2 */ - bdnz clear_bss /* decrement counter and loop */ - blr /* return */ - -/*---------------------------------------------------------------------------- - * ramacc test accessibility of RAM - * input: r2 = start address, r3 = length (in byte) - * output: r4 = 0 -> ok, !=0 -> fail - *---------------------------------------------------------------------------*/ -ramacc: - xor r4,r4,r4 /* r4 = 0 */ - stw r4,0(r2) /* init ram at start address */ - addi r4,r0,0x04 /* set start shift */ -ramaccf1: - cmp 0,0,r4,r3 /* compare with length */ - bge ramaccfx /* r4 >= r3? then finished */ - add r5,r4,r2 /* get next address to fill */ - stw r4,0(r5) /* store new pattern */ - add r4,r4,r4 /* r4 = r4*2 */ - b ramaccf1 /* and then next loop */ - -ramaccfx: - lwz r4,0(r2) /* get memory at start adr */ - blr - - -#if PPC_ABI == PPC_ABI_POWEROPEN - DESCRIPTOR (startup) -#endif - - - diff --git a/c/src/lib/libbsp/powerpc/papyrus/dlentry/Makefile.in b/c/src/lib/libbsp/powerpc/papyrus/dlentry/Makefile.in index dc40c405f6..5ecb9eaef8 100644 --- a/c/src/lib/libbsp/powerpc/papyrus/dlentry/Makefile.in +++ b/c/src/lib/libbsp/powerpc/papyrus/dlentry/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=dlentry -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/powerpc/papyrus/dlentry/dlentry.S b/c/src/lib/libbsp/powerpc/papyrus/dlentry/dlentry.S new file mode 100644 index 0000000000..b1e1f3a11b --- /dev/null +++ b/c/src/lib/libbsp/powerpc/papyrus/dlentry/dlentry.S @@ -0,0 +1,251 @@ +/* dlentry.s 1.0 - 95/08/08 + * + * This file contains the entry veneer for RTEMS programs + * downloaded to Papyrus. + * + * Author: Andrew Bray + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * $Id$ + */ + +#include "asm.h" + +/* + * The Papyrus ELF link scripts support three special sections: + * .entry The actual entry point, this must contain less + * than 256 bytes of code/data to fit below the + * .vectors section. This always preceeds any other + * code or data. + * .vectors The section containing the interrupt entry veneers. + * .entry2 Any code overflowing from .entry + * .descriptors The PowerOpen function indirection blocks. + */ + +/* + * Downloaded code loads the vectors separately to 0x00000100, + * so .entry can be over 256 bytes. + * + * The other sections are linked in the following order: + * .entry + * .entry2 + * .text + * .descriptors + * .data + * .bss + * usually starting from 0x00020000. + * + * The initial stack is set to run BELOW the code base address. + * + * All the entry veneer has to do is to clear the BSS. + */ + +/* + * GDB likes to have debugging information for the entry veneer. + * Here is some DWARF information. + */ + +#if PPC_ASM == PPC_ASM_ELF + .section .entry,"ax",@progbits +.L_text_b: +.L_LC1: + .previous + +.section .debug_sfnames +.L_sfnames_b: + .byte "/home/andy/powerpc/rtems-3.2.0/c/src/lib/libcpu/ppc/ppc403/dlentry/" + .byte 0 +.L_F0: + .byte "dlentry.s" + .byte 0 + .previous + +.section .line +.L_line_b: + .4byte .L_line_e-.L_line_b + .4byte .L_text_b +.L_LE1: +.L_line_last: + .4byte 0x0 + .2byte 0xffff + .4byte .L_text_e-.L_text_b +.L_line_e: + .previous + +.section .debug_srcinfo +.L_srcinfo_b: + .4byte .L_line_b + .4byte .L_sfnames_b + .4byte .L_text_b + .4byte .L_text_e + .4byte 0xffffffff + .4byte .L_LE1-.L_line_b + .4byte .L_F0-.L_sfnames_b + .4byte .L_line_last-.L_line_b + .4byte 0xffffffff + .previous + +.section .debug_pubnames + .4byte .L_debug_b + .4byte .L_P0 + .byte "download_entry" + .byte 0 + .4byte 0x0 + .byte 0 + .previous + +.section .debug_aranges + .4byte .L_debug_b + .4byte .L_text_b + .4byte .L_text_e-.L_text_b + .4byte 0 + .4byte 0 + .4byte 0 + .4byte 0 + .4byte 0 + .4byte 0 + .4byte 0x0 + .4byte 0x0 + .previous + +.section .debug +.L_debug_b: +.L_D1: + .4byte .L_D1_e-.L_D1 + .2byte 0x11 /* TAG_compile_unit */ + .2byte 0x12 /* AT_sibling */ + .4byte .L_D2 + .2byte 0x38 /* AT_name */ + .byte "dlentry.s" + .byte 0 + .2byte 0x258 /* AT_producer */ + .byte "GAS 2.5.2" + .byte 0 + .2byte 0x111 /* AT_low_pc */ + .4byte .L_text_b + .2byte 0x121 /* AT_high_pc */ + .4byte .L_text_e + .2byte 0x106 /* AT_stmt_list */ + .4byte .L_line_b + .2byte 0x1b8 /* AT_comp_dir */ + .byte "/home/andy/powerpc/rtems-3.2.0/c/src/lib/libcpu/ppc/ppc403/dlentry/" + .byte 0 + .2byte 0x8006 /* AT_sf_names */ + .4byte .L_sfnames_b + .2byte 0x8016 /* AT_src_info */ + .4byte .L_srcinfo_b +.L_D1_e: +.L_P0: +.L_D3: + .4byte .L_D3_e-.L_D3 + .2byte 0x6 /* TAG_global_subroutine */ + .2byte 0x12 /* AT_sibling */ + .4byte .L_D4 + .2byte 0x38 /* AT_name */ + .byte "download_entry" + .byte 0 + .2byte 0x278 /* AT_prototyped */ + .byte 0 + .2byte 0x111 /* AT_low_pc */ + .4byte .L_text_b + .2byte 0x121 /* AT_high_pc */ + .4byte .L_text_e + .2byte 0x8041 /* AT_body_begin */ + .4byte .L_text_b + .2byte 0x8051 /* AT_body_end */ + .4byte .L_text_e +.L_D3_e: + +.L_D4: + .4byte .L_D4_e-.L_D4 + .align 2 +.L_D4_e: +.L_D2: + .previous +#endif + +/*------------------------------------------------------------------------------- + * ROM Vector area. + *------------------------------------------------------------------------------*/ +#if PPC_ASM == PPC_ASM_ELF + .section .entry +#else + .csect .text[PR] +#endif + + PUBLIC_VAR (download_entry) +SYM(download_entry): + bl .startup +base_addr: + +/*------------------------------------------------------------------------------- + * Parameters from linker + *------------------------------------------------------------------------------*/ +toc_pointer: +#if PPC_ASM == PPC_ASM_ELF + .long s.got +#else + .long TOC[tc0] +#endif +bss_length: + .long bss.size +bss_addr: + .long bss.start +/*------------------------------------------------------------------------------- + * Reset_entry. + *------------------------------------------------------------------------------*/ +.startup: + /* Get start address, stack grows down from here... */ + mflr r1 + + /* Assume Bank regs set up..., cache etc. */ + bl bssclr + + /*----------------------------------------------------------------------- + * C_setup. + *----------------------------------------------------------------------*/ + lwz r2,toc_pointer-base_addr(r1) /* set r2 to toc */ + addi r1,r1,-56-4 /* start stack at text_addr - 56 */ + addi r3,r0,0x0 /* clear r3 */ + stw r3, 0(r1) /* Clear stack chain */ + stw r3, 4(r1) + stw r3, 8(r1) + stw r3, 12(r1) + .extern SYM (boot_card) + b SYM (boot_card) /* call the first C routine */ + +/*------------------------------------------------------------------------------- + * bssclr. + *------------------------------------------------------------------------------*/ +bssclr: + /*----------------------------------------------------------------------- + * Data move finished, zero out bss. + *----------------------------------------------------------------------*/ + lwz r2,bss_addr-base_addr(r1) /* start of bss set by loader */ + lwz r3,bss_length-base_addr(r1) /* bss length */ + rlwinm. r3,r3,30,0x3FFFFFFF /* form length/4 */ + beqlr /* no bss */ + mtctr r3 /* set ctr reg */ + xor r6,r6,r6 /* r6 = 0 */ +clear_bss: + stswi r6,r2,0x4 /* store r6 */ + addi r3,r2,0x4 /* update r2 */ + bdnz clear_bss /* decrement counter and loop */ + blr /* return */ +.L_text_e: + +#if PPC_ABI == PPC_ABI_POWEROPEN + DESCRIPTOR (startup) +#endif diff --git a/c/src/lib/libbsp/powerpc/papyrus/dlentry/dlentry.s b/c/src/lib/libbsp/powerpc/papyrus/dlentry/dlentry.s deleted file mode 100644 index b1e1f3a11b..0000000000 --- a/c/src/lib/libbsp/powerpc/papyrus/dlentry/dlentry.s +++ /dev/null @@ -1,251 +0,0 @@ -/* dlentry.s 1.0 - 95/08/08 - * - * This file contains the entry veneer for RTEMS programs - * downloaded to Papyrus. - * - * Author: Andrew Bray - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * $Id$ - */ - -#include "asm.h" - -/* - * The Papyrus ELF link scripts support three special sections: - * .entry The actual entry point, this must contain less - * than 256 bytes of code/data to fit below the - * .vectors section. This always preceeds any other - * code or data. - * .vectors The section containing the interrupt entry veneers. - * .entry2 Any code overflowing from .entry - * .descriptors The PowerOpen function indirection blocks. - */ - -/* - * Downloaded code loads the vectors separately to 0x00000100, - * so .entry can be over 256 bytes. - * - * The other sections are linked in the following order: - * .entry - * .entry2 - * .text - * .descriptors - * .data - * .bss - * usually starting from 0x00020000. - * - * The initial stack is set to run BELOW the code base address. - * - * All the entry veneer has to do is to clear the BSS. - */ - -/* - * GDB likes to have debugging information for the entry veneer. - * Here is some DWARF information. - */ - -#if PPC_ASM == PPC_ASM_ELF - .section .entry,"ax",@progbits -.L_text_b: -.L_LC1: - .previous - -.section .debug_sfnames -.L_sfnames_b: - .byte "/home/andy/powerpc/rtems-3.2.0/c/src/lib/libcpu/ppc/ppc403/dlentry/" - .byte 0 -.L_F0: - .byte "dlentry.s" - .byte 0 - .previous - -.section .line -.L_line_b: - .4byte .L_line_e-.L_line_b - .4byte .L_text_b -.L_LE1: -.L_line_last: - .4byte 0x0 - .2byte 0xffff - .4byte .L_text_e-.L_text_b -.L_line_e: - .previous - -.section .debug_srcinfo -.L_srcinfo_b: - .4byte .L_line_b - .4byte .L_sfnames_b - .4byte .L_text_b - .4byte .L_text_e - .4byte 0xffffffff - .4byte .L_LE1-.L_line_b - .4byte .L_F0-.L_sfnames_b - .4byte .L_line_last-.L_line_b - .4byte 0xffffffff - .previous - -.section .debug_pubnames - .4byte .L_debug_b - .4byte .L_P0 - .byte "download_entry" - .byte 0 - .4byte 0x0 - .byte 0 - .previous - -.section .debug_aranges - .4byte .L_debug_b - .4byte .L_text_b - .4byte .L_text_e-.L_text_b - .4byte 0 - .4byte 0 - .4byte 0 - .4byte 0 - .4byte 0 - .4byte 0 - .4byte 0x0 - .4byte 0x0 - .previous - -.section .debug -.L_debug_b: -.L_D1: - .4byte .L_D1_e-.L_D1 - .2byte 0x11 /* TAG_compile_unit */ - .2byte 0x12 /* AT_sibling */ - .4byte .L_D2 - .2byte 0x38 /* AT_name */ - .byte "dlentry.s" - .byte 0 - .2byte 0x258 /* AT_producer */ - .byte "GAS 2.5.2" - .byte 0 - .2byte 0x111 /* AT_low_pc */ - .4byte .L_text_b - .2byte 0x121 /* AT_high_pc */ - .4byte .L_text_e - .2byte 0x106 /* AT_stmt_list */ - .4byte .L_line_b - .2byte 0x1b8 /* AT_comp_dir */ - .byte "/home/andy/powerpc/rtems-3.2.0/c/src/lib/libcpu/ppc/ppc403/dlentry/" - .byte 0 - .2byte 0x8006 /* AT_sf_names */ - .4byte .L_sfnames_b - .2byte 0x8016 /* AT_src_info */ - .4byte .L_srcinfo_b -.L_D1_e: -.L_P0: -.L_D3: - .4byte .L_D3_e-.L_D3 - .2byte 0x6 /* TAG_global_subroutine */ - .2byte 0x12 /* AT_sibling */ - .4byte .L_D4 - .2byte 0x38 /* AT_name */ - .byte "download_entry" - .byte 0 - .2byte 0x278 /* AT_prototyped */ - .byte 0 - .2byte 0x111 /* AT_low_pc */ - .4byte .L_text_b - .2byte 0x121 /* AT_high_pc */ - .4byte .L_text_e - .2byte 0x8041 /* AT_body_begin */ - .4byte .L_text_b - .2byte 0x8051 /* AT_body_end */ - .4byte .L_text_e -.L_D3_e: - -.L_D4: - .4byte .L_D4_e-.L_D4 - .align 2 -.L_D4_e: -.L_D2: - .previous -#endif - -/*------------------------------------------------------------------------------- - * ROM Vector area. - *------------------------------------------------------------------------------*/ -#if PPC_ASM == PPC_ASM_ELF - .section .entry -#else - .csect .text[PR] -#endif - - PUBLIC_VAR (download_entry) -SYM(download_entry): - bl .startup -base_addr: - -/*------------------------------------------------------------------------------- - * Parameters from linker - *------------------------------------------------------------------------------*/ -toc_pointer: -#if PPC_ASM == PPC_ASM_ELF - .long s.got -#else - .long TOC[tc0] -#endif -bss_length: - .long bss.size -bss_addr: - .long bss.start -/*------------------------------------------------------------------------------- - * Reset_entry. - *------------------------------------------------------------------------------*/ -.startup: - /* Get start address, stack grows down from here... */ - mflr r1 - - /* Assume Bank regs set up..., cache etc. */ - bl bssclr - - /*----------------------------------------------------------------------- - * C_setup. - *----------------------------------------------------------------------*/ - lwz r2,toc_pointer-base_addr(r1) /* set r2 to toc */ - addi r1,r1,-56-4 /* start stack at text_addr - 56 */ - addi r3,r0,0x0 /* clear r3 */ - stw r3, 0(r1) /* Clear stack chain */ - stw r3, 4(r1) - stw r3, 8(r1) - stw r3, 12(r1) - .extern SYM (boot_card) - b SYM (boot_card) /* call the first C routine */ - -/*------------------------------------------------------------------------------- - * bssclr. - *------------------------------------------------------------------------------*/ -bssclr: - /*----------------------------------------------------------------------- - * Data move finished, zero out bss. - *----------------------------------------------------------------------*/ - lwz r2,bss_addr-base_addr(r1) /* start of bss set by loader */ - lwz r3,bss_length-base_addr(r1) /* bss length */ - rlwinm. r3,r3,30,0x3FFFFFFF /* form length/4 */ - beqlr /* no bss */ - mtctr r3 /* set ctr reg */ - xor r6,r6,r6 /* r6 = 0 */ -clear_bss: - stswi r6,r2,0x4 /* store r6 */ - addi r3,r2,0x4 /* update r2 */ - bdnz clear_bss /* decrement counter and loop */ - blr /* return */ -.L_text_e: - -#if PPC_ABI == PPC_ABI_POWEROPEN - DESCRIPTOR (startup) -#endif diff --git a/c/src/lib/libbsp/powerpc/papyrus/flashentry/Makefile.in b/c/src/lib/libbsp/powerpc/papyrus/flashentry/Makefile.in index 683f996472..b56cce2ea8 100644 --- a/c/src/lib/libbsp/powerpc/papyrus/flashentry/Makefile.in +++ b/c/src/lib/libbsp/powerpc/papyrus/flashentry/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=flashentry -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/powerpc/papyrus/flashentry/flashentry.S b/c/src/lib/libbsp/powerpc/papyrus/flashentry/flashentry.S new file mode 100644 index 0000000000..857caa729d --- /dev/null +++ b/c/src/lib/libbsp/powerpc/papyrus/flashentry/flashentry.S @@ -0,0 +1,289 @@ +/* dlentry.s 1.0 - 95/08/08 + * + * This file contains the entry veneer for RTEMS programs + * stored in Papyrus' flash ROM. + * + * Author: Andrew Bray + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * $Id$ + */ + +#include "asm.h" + +/* + * The Papyrus ELF link scripts support three special sections: + * .entry The actual entry point, this must contain less + * than 256 bytes of code/data to fit below the + * .vectors section. This always preceeds any other + * code or data. + * .vectors The section containing the interrupt entry veneers. + * .entry2 Any code overflowing from .entry + * .descriptors The PowerOpen function indirection blocks. + */ + +/* + * Flash sections are linked in the following order: + * .entry + * .vectors + * .entry2 + * .text + * .descriptors + * .data + * .bss + * usually starting from 0xFFF00000. + * + * The initial stack is set to run BELOW the final location of + * the initialised data. + * + * All the entry veneer has to do is to copy the initialised data + * to its final location and clear the BSS. + */ + +/* + * GDB likes to have debugging information for the entry veneer. + * Here is some DWARF information. + */ + +#if PPC_ASM == PPC_ASM_ELF + .section .entry,"ax",@progbits +.L_text_b: +.L_LC1: + .previous + +.section .debug_sfnames +.L_sfnames_b: + .byte "/home/andy/powerpc/rtems-3.2.0/c/src/lib/libcpu/ppc/ppc403/flashentry/" + .byte 0 +.L_F0: + .byte "flashentry.s" + .byte 0 + .previous + +.section .line +.L_line_b: + .4byte .L_line_e-.L_line_b + .4byte .L_text_b +.L_LE1: +.L_line_last: + .4byte 0x0 + .2byte 0xffff + .4byte .L_text_e-.L_text_b +.L_line_e: + .previous + +.section .debug_srcinfo +.L_srcinfo_b: + .4byte .L_line_b + .4byte .L_sfnames_b + .4byte .L_text_b + .4byte .L_text_e + .4byte 0xffffffff + .4byte .L_LE1-.L_line_b + .4byte .L_F0-.L_sfnames_b + .4byte .L_line_last-.L_line_b + .4byte 0xffffffff + .previous + +.section .debug_pubnames + .4byte .L_debug_b + .4byte .L_P0 + .byte "flash_entry" + .byte 0 + .4byte 0x0 + .byte 0 + .previous + +.section .debug_aranges + .4byte .L_debug_b + .4byte .L_text_b + .4byte .L_text_e-.L_text_b + .4byte 0 + .4byte 0 + .4byte 0 + .4byte 0 + .4byte 0 + .4byte 0 + .4byte 0x0 + .4byte 0x0 + .previous + +.section .debug +.L_debug_b: +.L_D1: + .4byte .L_D1_e-.L_D1 + .2byte 0x11 /* TAG_compile_unit */ + .2byte 0x12 /* AT_sibling */ + .4byte .L_D2 + .2byte 0x38 /* AT_name */ + .byte "flashentry.s" + .byte 0 + .2byte 0x258 /* AT_producer */ + .byte "GAS 2.5.2" + .byte 0 + .2byte 0x111 /* AT_low_pc */ + .4byte .L_text_b + .2byte 0x121 /* AT_high_pc */ + .4byte .L_text_e + .2byte 0x106 /* AT_stmt_list */ + .4byte .L_line_b + .2byte 0x1b8 /* AT_comp_dir */ + .byte "/home/andy/powerpc/rtems-3.2.0/c/src/lib/libcpu/ppc/ppc403/dlentry/" + .byte 0 + .2byte 0x8006 /* AT_sf_names */ + .4byte .L_sfnames_b + .2byte 0x8016 /* AT_src_info */ + .4byte .L_srcinfo_b +.L_D1_e: +.L_P0: +.L_D3: + .4byte .L_D3_e-.L_D3 + .2byte 0x6 /* TAG_global_subroutine */ + .2byte 0x12 /* AT_sibling */ + .4byte .L_D4 + .2byte 0x38 /* AT_name */ + .byte "flash_entry" + .byte 0 + .2byte 0x278 /* AT_prototyped */ + .byte 0 + .2byte 0x111 /* AT_low_pc */ + .4byte .L_text_b + .2byte 0x121 /* AT_high_pc */ + .4byte .L_text_e + .2byte 0x8041 /* AT_body_begin */ + .4byte .L_text_b + .2byte 0x8051 /* AT_body_end */ + .4byte .L_text_e +.L_D3_e: + +.L_D4: + .4byte .L_D4_e-.L_D4 + .align 2 +.L_D4_e: +.L_D2: + .previous +#endif + +/*------------------------------------------------------------------------------- + * ROM Vector area. + *------------------------------------------------------------------------------*/ +#if PPC_ASM == PPC_ASM_ELF + .section .entry +#else + .csect .text[PR] +#endif + PUBLIC_VAR (flash_entry) +SYM (flash_entry): + bl .startup +base_addr: + +/*------------------------------------------------------------------------------- + * Parameters from linker + *------------------------------------------------------------------------------*/ +toc_pointer: +#if PPC_ASM == PPC_ASM_ELF + .long s.got +#else + .long TOC[tc0] +#endif +text_length: + .long t.size +text_addr: + .long t.start +data_length: + .long copy.size +data_addr: + .long copy.dest +bss_length: + .long bss.size +bss_addr: + .long bss.start + +/*------------------------------------------------------------------------------- + * Reset_entry. + *------------------------------------------------------------------------------*/ +.startup: + /* Get start address */ + mflr r1 + + /* Assume Bank regs set up..., cache etc. */ + + /*----------------------------------------------------------------------- + * Check the DRAM where STACK+ DATA+ BBS will be placed. If this is OK + * we will return here. + *----------------------------------------------------------------------*/ + bl rom2ram + /*----------------------------------------------------------------------- + * Enable two 128MB cachable regions. + *----------------------------------------------------------------------*/ + addis r2,r0,0x8000 + addi r2,r2,0x0001 + + mtspr 0x3fb, r2 /* ICCR */ + mtspr 0x3fa, r2 /* DCCR */ + + /*----------------------------------------------------------------------- + * C_setup. + *----------------------------------------------------------------------*/ + lwz r2,toc_pointer-base_addr(r1) /* set r2 to toc */ + lwz r1,data_addr-base_addr(r1) /* set r1 to data_addr */ + addi r1,r1,-56 /* start stack at data_addr - 56 */ + addi r3,r0,0x0 /* clear r3 */ + stw r3, 0(r1) /* Clear stack chain */ + stw r3, 4(r1) + stw r3, 8(r1) + stw r3, 12(r1) + .extern SYM (boot_card) + b SYM (boot_card) /* call the first C routine */ + +/*------------------------------------------------------------------------------- + * Rom2ram. + *------------------------------------------------------------------------------*/ +rom2ram: + lwz r2,data_addr-base_addr(r1) /* start of data set by loader */ + lwz r3,data_length-base_addr(r1) /* data length */ + rlwinm r3,r3,30,0x3FFFFFFF /* form length/4 */ + mtctr r3 /* set ctr reg */ + /*----------------------------------------------------------------------- + * Calculate offset of data in image. + *----------------------------------------------------------------------*/ + lwz r5,text_length-base_addr(r1) /* get text length */ + lwz r4,text_addr-base_addr(r1) /* get text length */ + add r4,r4,r5 /* r4 = data pointer */ +move_data: + lswi r6,r4,0x4 /* load r6 */ + stswi r6,r2,0x4 /* store r6 */ + addi r4,r4,0x4 /* update r4 */ + addi r2,r2,0x4 /* update r2 */ + bdnz move_data /* decrement counter and loop */ + /*----------------------------------------------------------------------- + * Data move finished, zero out bss. + *----------------------------------------------------------------------*/ + lwz r2,bss_addr-base_addr(r1) /* start of bss set by loader */ + lwz r3,bss_length-base_addr(r1) /* bss length */ + rlwinm. r3,r3,30,0x3FFFFFFF /* form length/4 */ + beqlr /* no bss */ + mtctr r3 /* set ctr reg */ + xor r6,r6,r6 /* r6 = 0 */ +clear_bss: + stswi r6,r2,0x4 /* store r6 */ + addi r3,r2,0x4 /* update r2 */ + bdnz clear_bss /* decrement counter and loop */ + blr /* return */ +.L_text_e: + +#if PPC_ABI == PPC_ABI_POWEROPEN + DESCRIPTOR (startup) +#endif diff --git a/c/src/lib/libbsp/powerpc/papyrus/flashentry/flashentry.s b/c/src/lib/libbsp/powerpc/papyrus/flashentry/flashentry.s deleted file mode 100644 index 857caa729d..0000000000 --- a/c/src/lib/libbsp/powerpc/papyrus/flashentry/flashentry.s +++ /dev/null @@ -1,289 +0,0 @@ -/* dlentry.s 1.0 - 95/08/08 - * - * This file contains the entry veneer for RTEMS programs - * stored in Papyrus' flash ROM. - * - * Author: Andrew Bray - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * $Id$ - */ - -#include "asm.h" - -/* - * The Papyrus ELF link scripts support three special sections: - * .entry The actual entry point, this must contain less - * than 256 bytes of code/data to fit below the - * .vectors section. This always preceeds any other - * code or data. - * .vectors The section containing the interrupt entry veneers. - * .entry2 Any code overflowing from .entry - * .descriptors The PowerOpen function indirection blocks. - */ - -/* - * Flash sections are linked in the following order: - * .entry - * .vectors - * .entry2 - * .text - * .descriptors - * .data - * .bss - * usually starting from 0xFFF00000. - * - * The initial stack is set to run BELOW the final location of - * the initialised data. - * - * All the entry veneer has to do is to copy the initialised data - * to its final location and clear the BSS. - */ - -/* - * GDB likes to have debugging information for the entry veneer. - * Here is some DWARF information. - */ - -#if PPC_ASM == PPC_ASM_ELF - .section .entry,"ax",@progbits -.L_text_b: -.L_LC1: - .previous - -.section .debug_sfnames -.L_sfnames_b: - .byte "/home/andy/powerpc/rtems-3.2.0/c/src/lib/libcpu/ppc/ppc403/flashentry/" - .byte 0 -.L_F0: - .byte "flashentry.s" - .byte 0 - .previous - -.section .line -.L_line_b: - .4byte .L_line_e-.L_line_b - .4byte .L_text_b -.L_LE1: -.L_line_last: - .4byte 0x0 - .2byte 0xffff - .4byte .L_text_e-.L_text_b -.L_line_e: - .previous - -.section .debug_srcinfo -.L_srcinfo_b: - .4byte .L_line_b - .4byte .L_sfnames_b - .4byte .L_text_b - .4byte .L_text_e - .4byte 0xffffffff - .4byte .L_LE1-.L_line_b - .4byte .L_F0-.L_sfnames_b - .4byte .L_line_last-.L_line_b - .4byte 0xffffffff - .previous - -.section .debug_pubnames - .4byte .L_debug_b - .4byte .L_P0 - .byte "flash_entry" - .byte 0 - .4byte 0x0 - .byte 0 - .previous - -.section .debug_aranges - .4byte .L_debug_b - .4byte .L_text_b - .4byte .L_text_e-.L_text_b - .4byte 0 - .4byte 0 - .4byte 0 - .4byte 0 - .4byte 0 - .4byte 0 - .4byte 0x0 - .4byte 0x0 - .previous - -.section .debug -.L_debug_b: -.L_D1: - .4byte .L_D1_e-.L_D1 - .2byte 0x11 /* TAG_compile_unit */ - .2byte 0x12 /* AT_sibling */ - .4byte .L_D2 - .2byte 0x38 /* AT_name */ - .byte "flashentry.s" - .byte 0 - .2byte 0x258 /* AT_producer */ - .byte "GAS 2.5.2" - .byte 0 - .2byte 0x111 /* AT_low_pc */ - .4byte .L_text_b - .2byte 0x121 /* AT_high_pc */ - .4byte .L_text_e - .2byte 0x106 /* AT_stmt_list */ - .4byte .L_line_b - .2byte 0x1b8 /* AT_comp_dir */ - .byte "/home/andy/powerpc/rtems-3.2.0/c/src/lib/libcpu/ppc/ppc403/dlentry/" - .byte 0 - .2byte 0x8006 /* AT_sf_names */ - .4byte .L_sfnames_b - .2byte 0x8016 /* AT_src_info */ - .4byte .L_srcinfo_b -.L_D1_e: -.L_P0: -.L_D3: - .4byte .L_D3_e-.L_D3 - .2byte 0x6 /* TAG_global_subroutine */ - .2byte 0x12 /* AT_sibling */ - .4byte .L_D4 - .2byte 0x38 /* AT_name */ - .byte "flash_entry" - .byte 0 - .2byte 0x278 /* AT_prototyped */ - .byte 0 - .2byte 0x111 /* AT_low_pc */ - .4byte .L_text_b - .2byte 0x121 /* AT_high_pc */ - .4byte .L_text_e - .2byte 0x8041 /* AT_body_begin */ - .4byte .L_text_b - .2byte 0x8051 /* AT_body_end */ - .4byte .L_text_e -.L_D3_e: - -.L_D4: - .4byte .L_D4_e-.L_D4 - .align 2 -.L_D4_e: -.L_D2: - .previous -#endif - -/*------------------------------------------------------------------------------- - * ROM Vector area. - *------------------------------------------------------------------------------*/ -#if PPC_ASM == PPC_ASM_ELF - .section .entry -#else - .csect .text[PR] -#endif - PUBLIC_VAR (flash_entry) -SYM (flash_entry): - bl .startup -base_addr: - -/*------------------------------------------------------------------------------- - * Parameters from linker - *------------------------------------------------------------------------------*/ -toc_pointer: -#if PPC_ASM == PPC_ASM_ELF - .long s.got -#else - .long TOC[tc0] -#endif -text_length: - .long t.size -text_addr: - .long t.start -data_length: - .long copy.size -data_addr: - .long copy.dest -bss_length: - .long bss.size -bss_addr: - .long bss.start - -/*------------------------------------------------------------------------------- - * Reset_entry. - *------------------------------------------------------------------------------*/ -.startup: - /* Get start address */ - mflr r1 - - /* Assume Bank regs set up..., cache etc. */ - - /*----------------------------------------------------------------------- - * Check the DRAM where STACK+ DATA+ BBS will be placed. If this is OK - * we will return here. - *----------------------------------------------------------------------*/ - bl rom2ram - /*----------------------------------------------------------------------- - * Enable two 128MB cachable regions. - *----------------------------------------------------------------------*/ - addis r2,r0,0x8000 - addi r2,r2,0x0001 - - mtspr 0x3fb, r2 /* ICCR */ - mtspr 0x3fa, r2 /* DCCR */ - - /*----------------------------------------------------------------------- - * C_setup. - *----------------------------------------------------------------------*/ - lwz r2,toc_pointer-base_addr(r1) /* set r2 to toc */ - lwz r1,data_addr-base_addr(r1) /* set r1 to data_addr */ - addi r1,r1,-56 /* start stack at data_addr - 56 */ - addi r3,r0,0x0 /* clear r3 */ - stw r3, 0(r1) /* Clear stack chain */ - stw r3, 4(r1) - stw r3, 8(r1) - stw r3, 12(r1) - .extern SYM (boot_card) - b SYM (boot_card) /* call the first C routine */ - -/*------------------------------------------------------------------------------- - * Rom2ram. - *------------------------------------------------------------------------------*/ -rom2ram: - lwz r2,data_addr-base_addr(r1) /* start of data set by loader */ - lwz r3,data_length-base_addr(r1) /* data length */ - rlwinm r3,r3,30,0x3FFFFFFF /* form length/4 */ - mtctr r3 /* set ctr reg */ - /*----------------------------------------------------------------------- - * Calculate offset of data in image. - *----------------------------------------------------------------------*/ - lwz r5,text_length-base_addr(r1) /* get text length */ - lwz r4,text_addr-base_addr(r1) /* get text length */ - add r4,r4,r5 /* r4 = data pointer */ -move_data: - lswi r6,r4,0x4 /* load r6 */ - stswi r6,r2,0x4 /* store r6 */ - addi r4,r4,0x4 /* update r4 */ - addi r2,r2,0x4 /* update r2 */ - bdnz move_data /* decrement counter and loop */ - /*----------------------------------------------------------------------- - * Data move finished, zero out bss. - *----------------------------------------------------------------------*/ - lwz r2,bss_addr-base_addr(r1) /* start of bss set by loader */ - lwz r3,bss_length-base_addr(r1) /* bss length */ - rlwinm. r3,r3,30,0x3FFFFFFF /* form length/4 */ - beqlr /* no bss */ - mtctr r3 /* set ctr reg */ - xor r6,r6,r6 /* r6 = 0 */ -clear_bss: - stswi r6,r2,0x4 /* store r6 */ - addi r3,r2,0x4 /* update r2 */ - bdnz clear_bss /* decrement counter and loop */ - blr /* return */ -.L_text_e: - -#if PPC_ABI == PPC_ABI_POWEROPEN - DESCRIPTOR (startup) -#endif diff --git a/c/src/lib/libbsp/powerpc/psim/clock/Makefile.in b/c/src/lib/libbsp/powerpc/psim/clock/Makefile.in index be0a454963..b2674e2009 100644 --- a/c/src/lib/libbsp/powerpc/psim/clock/Makefile.in +++ b/c/src/lib/libbsp/powerpc/psim/clock/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES= -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/powerpc/psim/console/Makefile.in b/c/src/lib/libbsp/powerpc/psim/console/Makefile.in index 125410e1c6..2ba8603478 100644 --- a/c/src/lib/libbsp/powerpc/psim/console/Makefile.in +++ b/c/src/lib/libbsp/powerpc/psim/console/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=consupp -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/powerpc/psim/console/consupp.S b/c/src/lib/libbsp/powerpc/psim/console/consupp.S new file mode 100644 index 0000000000..bb9e834fc6 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/psim/console/consupp.S @@ -0,0 +1,33 @@ +/* + * Adapted from the mvme-inbyte.S and mvme-outbyte.S files in libgloss. + * These should work on all targets using the ppcbug monitor. + * + * Copyright (c) 1995 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ + +#include "ppc-asm.h" + + .file "support.s" + .text +FUNC_START(outbyte) + li r10,0x20 + sc + blr +FUNC_END(outbyte) + + .text +FUNC_START(inbyte) + li r10,0x0 + sc + blr +FUNC_END(inbyte) diff --git a/c/src/lib/libbsp/powerpc/psim/console/consupp.s b/c/src/lib/libbsp/powerpc/psim/console/consupp.s deleted file mode 100644 index bb9e834fc6..0000000000 --- a/c/src/lib/libbsp/powerpc/psim/console/consupp.s +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Adapted from the mvme-inbyte.S and mvme-outbyte.S files in libgloss. - * These should work on all targets using the ppcbug monitor. - * - * Copyright (c) 1995 Cygnus Support - * - * The authors hereby grant permission to use, copy, modify, distribute, - * and license this software and its documentation for any purpose, provided - * that existing copyright notices are retained in all copies and that this - * notice is included verbatim in any distributions. No written agreement, - * license, or royalty fee is required for any of the authorized uses. - * Modifications to this software may be copyrighted by their authors - * and need not follow the licensing terms described here, provided that - * the new terms are clearly indicated on the first page of each file where - * they apply. - */ - -#include "ppc-asm.h" - - .file "support.s" - .text -FUNC_START(outbyte) - li r10,0x20 - sc - blr -FUNC_END(outbyte) - - .text -FUNC_START(inbyte) - li r10,0x0 - sc - blr -FUNC_END(inbyte) diff --git a/c/src/lib/libbsp/powerpc/psim/start/Makefile.in b/c/src/lib/libbsp/powerpc/psim/start/Makefile.in index 35377e94f1..48d2c854c3 100644 --- a/c/src/lib/libbsp/powerpc/psim/start/Makefile.in +++ b/c/src/lib/libbsp/powerpc/psim/start/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=startsim -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/powerpc/psim/start/start.S b/c/src/lib/libbsp/powerpc/psim/start/start.S new file mode 100644 index 0000000000..f94a3ca330 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/psim/start/start.S @@ -0,0 +1,106 @@ +/* + * This is based on the mvme-crt0.S file from libgloss/rs6000. + * crt0.S -- startup file for PowerPC systems. + * + * Copyright (c) 1995 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + * + * $Id$ + */ + +#include "ppc-asm.h" + + .file "startsim.s" + .section ".got2","aw" + .align 2 + +.LCTOC1 = .+32768 + + .extern FUNC_NAME(atexit) + .globl FUNC_NAME(__atexit) + .section ".sdata","aw" + .align 2 +FUNC_NAME(__atexit): /* tell C's eabi-ctor's we have an atexit function */ + .long FUNC_NAME(atexit)@fixup /* and that it is to register __do_global_dtors */ + + .section ".fixup","aw" + .align 2 + .long FUNC_NAME(__atexit) + + .section ".got2","aw" +.Ltable = .-.LCTOC1 + .long .LCTOC1 /* address we think .LCTOC1 is loaded at */ + +.Lbss_start = .-.LCTOC1 + .long __bss_start + +.Lend = .-.LCTOC1 + .long _end + +.Lstack = .-.LCTOC1 /* stack address if set by user */ + .long __stack + + .text +.Lptr: + .long .LCTOC1-.Laddr + + .globl _start + .type _start,@function +_start: + bl .Laddr /* get current address */ +.Laddr: + mflr r4 /* real address of .Laddr */ + lwz r5,(.Lptr-.Laddr)(r4) /* linker generated address of .LCTOC1 */ + add r5,r5,r4 /* correct to real pointer */ + lwz r4,.Ltable(r5) /* get linker's idea of where .Laddr is */ + subf r4,r4,r5 /* calculate difference between where linked and current */ + + /* clear bss */ + lwz r6,.Lbss_start(r5) /* calculate beginning of the BSS */ + lwz r7,.Lend(r5) /* calculate end of the BSS */ + add r6,r6,r4 /* adjust pointers */ + add r7,r7,r4 + + cmplw 1,r6,r7 + bc 4,4,.Ldone + + subf r8,r6,r7 /* number of bytes to zero */ + srwi r9,r8,2 /* number of words to zero */ + mtctr r9 + li r0,0 /* zero to clear memory */ + addi r6,r6,-4 /* adjust so we can use stwu */ +.Lloop: + stwu r0,4(r6) /* zero bss */ + bdnz .Lloop + +.Ldone: + + lwz r0,.Lstack(r5) /* stack address or 0 */ + cmplwi 1,r0,0 /* equal to 0? */ + bc 12,6,.Lnostack /* use default stack if == 0 */ + mr sp,r0 /* use user defined stack */ + +.Lnostack: + /* set up initial stack frame */ + addi sp,sp,-4 /* make sure we don't overwrite debug mem */ + lis r0,0 + stw r0,0(sp) /* clear back chain */ + stwu sp,-56(sp) /* push another stack frame */ + + /* Let her rip */ + bl FUNC_NAME(boot_card) + + /* return value from boot_card is argument to exit */ + bl FUNC_NAME(exit) + trap +.Lstart: + .size _start,.Lstart-_start diff --git a/c/src/lib/libbsp/powerpc/psim/start/startsim.s b/c/src/lib/libbsp/powerpc/psim/start/startsim.s deleted file mode 100644 index f94a3ca330..0000000000 --- a/c/src/lib/libbsp/powerpc/psim/start/startsim.s +++ /dev/null @@ -1,106 +0,0 @@ -/* - * This is based on the mvme-crt0.S file from libgloss/rs6000. - * crt0.S -- startup file for PowerPC systems. - * - * Copyright (c) 1995 Cygnus Support - * - * The authors hereby grant permission to use, copy, modify, distribute, - * and license this software and its documentation for any purpose, provided - * that existing copyright notices are retained in all copies and that this - * notice is included verbatim in any distributions. No written agreement, - * license, or royalty fee is required for any of the authorized uses. - * Modifications to this software may be copyrighted by their authors - * and need not follow the licensing terms described here, provided that - * the new terms are clearly indicated on the first page of each file where - * they apply. - * - * $Id$ - */ - -#include "ppc-asm.h" - - .file "startsim.s" - .section ".got2","aw" - .align 2 - -.LCTOC1 = .+32768 - - .extern FUNC_NAME(atexit) - .globl FUNC_NAME(__atexit) - .section ".sdata","aw" - .align 2 -FUNC_NAME(__atexit): /* tell C's eabi-ctor's we have an atexit function */ - .long FUNC_NAME(atexit)@fixup /* and that it is to register __do_global_dtors */ - - .section ".fixup","aw" - .align 2 - .long FUNC_NAME(__atexit) - - .section ".got2","aw" -.Ltable = .-.LCTOC1 - .long .LCTOC1 /* address we think .LCTOC1 is loaded at */ - -.Lbss_start = .-.LCTOC1 - .long __bss_start - -.Lend = .-.LCTOC1 - .long _end - -.Lstack = .-.LCTOC1 /* stack address if set by user */ - .long __stack - - .text -.Lptr: - .long .LCTOC1-.Laddr - - .globl _start - .type _start,@function -_start: - bl .Laddr /* get current address */ -.Laddr: - mflr r4 /* real address of .Laddr */ - lwz r5,(.Lptr-.Laddr)(r4) /* linker generated address of .LCTOC1 */ - add r5,r5,r4 /* correct to real pointer */ - lwz r4,.Ltable(r5) /* get linker's idea of where .Laddr is */ - subf r4,r4,r5 /* calculate difference between where linked and current */ - - /* clear bss */ - lwz r6,.Lbss_start(r5) /* calculate beginning of the BSS */ - lwz r7,.Lend(r5) /* calculate end of the BSS */ - add r6,r6,r4 /* adjust pointers */ - add r7,r7,r4 - - cmplw 1,r6,r7 - bc 4,4,.Ldone - - subf r8,r6,r7 /* number of bytes to zero */ - srwi r9,r8,2 /* number of words to zero */ - mtctr r9 - li r0,0 /* zero to clear memory */ - addi r6,r6,-4 /* adjust so we can use stwu */ -.Lloop: - stwu r0,4(r6) /* zero bss */ - bdnz .Lloop - -.Ldone: - - lwz r0,.Lstack(r5) /* stack address or 0 */ - cmplwi 1,r0,0 /* equal to 0? */ - bc 12,6,.Lnostack /* use default stack if == 0 */ - mr sp,r0 /* use user defined stack */ - -.Lnostack: - /* set up initial stack frame */ - addi sp,sp,-4 /* make sure we don't overwrite debug mem */ - lis r0,0 - stw r0,0(sp) /* clear back chain */ - stwu sp,-56(sp) /* push another stack frame */ - - /* Let her rip */ - bl FUNC_NAME(boot_card) - - /* return value from boot_card is argument to exit */ - bl FUNC_NAME(exit) - trap -.Lstart: - .size _start,.Lstart-_start diff --git a/c/src/lib/libbsp/powerpc/psim/startsim/Makefile.in b/c/src/lib/libbsp/powerpc/psim/startsim/Makefile.in index 35377e94f1..48d2c854c3 100644 --- a/c/src/lib/libbsp/powerpc/psim/startsim/Makefile.in +++ b/c/src/lib/libbsp/powerpc/psim/startsim/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=startsim -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/powerpc/psim/startsim/startsim.S b/c/src/lib/libbsp/powerpc/psim/startsim/startsim.S new file mode 100644 index 0000000000..f94a3ca330 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/psim/startsim/startsim.S @@ -0,0 +1,106 @@ +/* + * This is based on the mvme-crt0.S file from libgloss/rs6000. + * crt0.S -- startup file for PowerPC systems. + * + * Copyright (c) 1995 Cygnus Support + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + * + * $Id$ + */ + +#include "ppc-asm.h" + + .file "startsim.s" + .section ".got2","aw" + .align 2 + +.LCTOC1 = .+32768 + + .extern FUNC_NAME(atexit) + .globl FUNC_NAME(__atexit) + .section ".sdata","aw" + .align 2 +FUNC_NAME(__atexit): /* tell C's eabi-ctor's we have an atexit function */ + .long FUNC_NAME(atexit)@fixup /* and that it is to register __do_global_dtors */ + + .section ".fixup","aw" + .align 2 + .long FUNC_NAME(__atexit) + + .section ".got2","aw" +.Ltable = .-.LCTOC1 + .long .LCTOC1 /* address we think .LCTOC1 is loaded at */ + +.Lbss_start = .-.LCTOC1 + .long __bss_start + +.Lend = .-.LCTOC1 + .long _end + +.Lstack = .-.LCTOC1 /* stack address if set by user */ + .long __stack + + .text +.Lptr: + .long .LCTOC1-.Laddr + + .globl _start + .type _start,@function +_start: + bl .Laddr /* get current address */ +.Laddr: + mflr r4 /* real address of .Laddr */ + lwz r5,(.Lptr-.Laddr)(r4) /* linker generated address of .LCTOC1 */ + add r5,r5,r4 /* correct to real pointer */ + lwz r4,.Ltable(r5) /* get linker's idea of where .Laddr is */ + subf r4,r4,r5 /* calculate difference between where linked and current */ + + /* clear bss */ + lwz r6,.Lbss_start(r5) /* calculate beginning of the BSS */ + lwz r7,.Lend(r5) /* calculate end of the BSS */ + add r6,r6,r4 /* adjust pointers */ + add r7,r7,r4 + + cmplw 1,r6,r7 + bc 4,4,.Ldone + + subf r8,r6,r7 /* number of bytes to zero */ + srwi r9,r8,2 /* number of words to zero */ + mtctr r9 + li r0,0 /* zero to clear memory */ + addi r6,r6,-4 /* adjust so we can use stwu */ +.Lloop: + stwu r0,4(r6) /* zero bss */ + bdnz .Lloop + +.Ldone: + + lwz r0,.Lstack(r5) /* stack address or 0 */ + cmplwi 1,r0,0 /* equal to 0? */ + bc 12,6,.Lnostack /* use default stack if == 0 */ + mr sp,r0 /* use user defined stack */ + +.Lnostack: + /* set up initial stack frame */ + addi sp,sp,-4 /* make sure we don't overwrite debug mem */ + lis r0,0 + stw r0,0(sp) /* clear back chain */ + stwu sp,-56(sp) /* push another stack frame */ + + /* Let her rip */ + bl FUNC_NAME(boot_card) + + /* return value from boot_card is argument to exit */ + bl FUNC_NAME(exit) + trap +.Lstart: + .size _start,.Lstart-_start diff --git a/c/src/lib/libbsp/powerpc/psim/startsim/startsim.s b/c/src/lib/libbsp/powerpc/psim/startsim/startsim.s deleted file mode 100644 index f94a3ca330..0000000000 --- a/c/src/lib/libbsp/powerpc/psim/startsim/startsim.s +++ /dev/null @@ -1,106 +0,0 @@ -/* - * This is based on the mvme-crt0.S file from libgloss/rs6000. - * crt0.S -- startup file for PowerPC systems. - * - * Copyright (c) 1995 Cygnus Support - * - * The authors hereby grant permission to use, copy, modify, distribute, - * and license this software and its documentation for any purpose, provided - * that existing copyright notices are retained in all copies and that this - * notice is included verbatim in any distributions. No written agreement, - * license, or royalty fee is required for any of the authorized uses. - * Modifications to this software may be copyrighted by their authors - * and need not follow the licensing terms described here, provided that - * the new terms are clearly indicated on the first page of each file where - * they apply. - * - * $Id$ - */ - -#include "ppc-asm.h" - - .file "startsim.s" - .section ".got2","aw" - .align 2 - -.LCTOC1 = .+32768 - - .extern FUNC_NAME(atexit) - .globl FUNC_NAME(__atexit) - .section ".sdata","aw" - .align 2 -FUNC_NAME(__atexit): /* tell C's eabi-ctor's we have an atexit function */ - .long FUNC_NAME(atexit)@fixup /* and that it is to register __do_global_dtors */ - - .section ".fixup","aw" - .align 2 - .long FUNC_NAME(__atexit) - - .section ".got2","aw" -.Ltable = .-.LCTOC1 - .long .LCTOC1 /* address we think .LCTOC1 is loaded at */ - -.Lbss_start = .-.LCTOC1 - .long __bss_start - -.Lend = .-.LCTOC1 - .long _end - -.Lstack = .-.LCTOC1 /* stack address if set by user */ - .long __stack - - .text -.Lptr: - .long .LCTOC1-.Laddr - - .globl _start - .type _start,@function -_start: - bl .Laddr /* get current address */ -.Laddr: - mflr r4 /* real address of .Laddr */ - lwz r5,(.Lptr-.Laddr)(r4) /* linker generated address of .LCTOC1 */ - add r5,r5,r4 /* correct to real pointer */ - lwz r4,.Ltable(r5) /* get linker's idea of where .Laddr is */ - subf r4,r4,r5 /* calculate difference between where linked and current */ - - /* clear bss */ - lwz r6,.Lbss_start(r5) /* calculate beginning of the BSS */ - lwz r7,.Lend(r5) /* calculate end of the BSS */ - add r6,r6,r4 /* adjust pointers */ - add r7,r7,r4 - - cmplw 1,r6,r7 - bc 4,4,.Ldone - - subf r8,r6,r7 /* number of bytes to zero */ - srwi r9,r8,2 /* number of words to zero */ - mtctr r9 - li r0,0 /* zero to clear memory */ - addi r6,r6,-4 /* adjust so we can use stwu */ -.Lloop: - stwu r0,4(r6) /* zero bss */ - bdnz .Lloop - -.Ldone: - - lwz r0,.Lstack(r5) /* stack address or 0 */ - cmplwi 1,r0,0 /* equal to 0? */ - bc 12,6,.Lnostack /* use default stack if == 0 */ - mr sp,r0 /* use user defined stack */ - -.Lnostack: - /* set up initial stack frame */ - addi sp,sp,-4 /* make sure we don't overwrite debug mem */ - lis r0,0 - stw r0,0(sp) /* clear back chain */ - stwu sp,-56(sp) /* push another stack frame */ - - /* Let her rip */ - bl FUNC_NAME(boot_card) - - /* return value from boot_card is argument to exit */ - bl FUNC_NAME(exit) - trap -.Lstart: - .size _start,.Lstart-_start diff --git a/c/src/lib/libbsp/powerpc/psim/startup/Makefile.in b/c/src/lib/libbsp/powerpc/psim/startup/Makefile.in index 8ae332fa12..15afe54b35 100644 --- a/c/src/lib/libbsp/powerpc/psim/startup/Makefile.in +++ b/c/src/lib/libbsp/powerpc/psim/startup/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES= -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=linkcmds device-tree $(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/powerpc/psim/timer/Makefile.in b/c/src/lib/libbsp/powerpc/psim/timer/Makefile.in index 16665e4de9..0ac1995395 100644 --- a/c/src/lib/libbsp/powerpc/psim/timer/Makefile.in +++ b/c/src/lib/libbsp/powerpc/psim/timer/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES= -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/powerpc/psim/vectors/Makefile.in b/c/src/lib/libbsp/powerpc/psim/vectors/Makefile.in index 031b7ca193..8034ba90e3 100644 --- a/c/src/lib/libbsp/powerpc/psim/vectors/Makefile.in +++ b/c/src/lib/libbsp/powerpc/psim/vectors/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=align_h vectors -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/powerpc/psim/vectors/align_h.S b/c/src/lib/libbsp/powerpc/psim/vectors/align_h.S new file mode 100644 index 0000000000..d16298343d --- /dev/null +++ b/c/src/lib/libbsp/powerpc/psim/vectors/align_h.S @@ -0,0 +1,434 @@ +/* align_h.s 1.1 - 95/12/04 + * + * This file contains the assembly code for the PowerPC 403 + * alignment exception handler for RTEMS. + * + * Based upon IBM provided code with the following release: + * + * This source code has been made available to you by IBM on an AS-IS + * basis. Anyone receiving this source is licensed under IBM + * copyrights to use it in any way he or she deems fit, including + * copying it, modifying it, compiling it, and redistributing it either + * with or without modifications. No license under IBM patents or + * patent applications is to be implied by the copyright license. + * + * Any user of this software should understand that IBM cannot provide + * technical support for this software and will not be responsible for + * any consequences resulting from the use of this software. + * + * Any person who transfers this source code or any derivative work + * must include the IBM copyright notice, this paragraph, and the + * preceding two paragraphs in the transferred software. + * + * COPYRIGHT I B M CORPORATION 1995 + * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M + * + * Modifications: + * + * Author: Andrew Bray + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * $Id$ + */ + +#include "asm.h" +#include "bsp.h" + +.set CACHE_SIZE,16 # cache line size of 32 bytes +.set CACHE_SIZE_L2,4 # cache line size, log 2 + +.set Open_gpr0,0 +.set Open_gpr1,4 +.set Open_gpr2,8 +.set Open_gpr3,12 +.set Open_gpr4,16 +.set Open_gpr5,20 +.set Open_gpr6,24 +.set Open_gpr7,28 +.set Open_gpr8,32 +.set Open_gpr9,36 +.set Open_gpr10,40 +.set Open_gpr11,44 +.set Open_gpr12,48 +.set Open_gpr13,52 +.set Open_gpr14,56 +.set Open_gpr15,60 +.set Open_gpr16,64 +.set Open_gpr17,68 +.set Open_gpr18,72 +.set Open_gpr19,76 +.set Open_gpr20,80 +.set Open_gpr21,84 +.set Open_gpr22,88 +.set Open_gpr23,92 +.set Open_gpr24,96 +.set Open_gpr25,100 +.set Open_gpr26,104 +.set Open_gpr27,108 +.set Open_gpr28,112 +.set Open_gpr29,116 +.set Open_gpr30,120 +.set Open_gpr31,124 +.set Open_xer,128 +.set Open_lr,132 +.set Open_ctr,136 +.set Open_cr,140 +.set Open_srr2,144 +.set Open_srr3,148 +.set Open_srr0,152 +.set Open_srr1,156 + + +/* + * This code makes several assumptions for processing efficiency + * * General purpose registers are continuous in the image, beginning with + * Open_gpr0 + * * Hash table is highly dependent on opcodes - opcode changes *will* + * require rework of the instruction decode mechanism. + */ + + .text + .globl align_h + + .align CACHE_SIZE_L2 +align_h: + /*----------------------------------------------------------------------- + * Store GPRs in Open Reg save area + * Set up r2 as base reg, r1 pointing to Open Reg save area + *----------------------------------------------------------------------*/ + stmw r0,ALIGN_REGS(r0) + li r1,ALIGN_REGS + /*----------------------------------------------------------------------- + * Store special purpose registers in reg save area + *----------------------------------------------------------------------*/ + mfxer r7 + mflr r8 + mfcr r9 + mfctr r10 + stw r7,Open_xer(r1) + stw r8,Open_lr(r1) + stw r9,Open_cr(r1) + stw r10,Open_ctr(r1) + mfspr r7, srr2 /* SRR 2 */ + mfspr r8, srr3 /* SRR 3 */ + mfspr r9, srr0 /* SRR 0 */ + mfspr r10, srr1 /* SRR 1 */ + stw r7,Open_srr2(r1) + stw r8,Open_srr3(r1) + stw r9,Open_srr0(r1) + stw r10,Open_srr1(r1) + +/* Set up common registers */ + mfspr r5, dear /* DEAR: R5 is data exception address */ + lwz r9,Open_srr0(r1) /* get faulting instruction */ + addi r7,r9,4 /* bump instruction */ + stw r7,Open_srr0(r1) /* restore to image */ + lwz r9, 0(r9) /* retrieve actual instruction */ + rlwinm r6,r9,18,25,29 /* r6 is RA * 4 field from instruction */ + rlwinm r7,r9,6,26,31 /* r7 is primary opcode */ + bl ref_point /* establish addressibility */ +ref_point: + mflr r11 /* r11 is the anchor point for ref_point */ + addi r10, r7, -31 /* r10 = r7 - 31 */ + rlwinm r10,r10,2,2,31 /* r10 *= 4 */ + add r10, r10, r11 /* r10 += anchor point */ + lwz r10, primary_jt-ref_point(r10) + mtlr r10 + rlwinm r8,r9,13,25,29 /* r8 is RD * 4 */ + la r7,Open_gpr0(r1) /* r7 is address of GPR 0 in list */ + blr +primary_jt: + .long xform + .long lwz + .long lwzu + .long 0 + .long 0 + .long stw + .long stwu + .long 0 + .long 0 + .long lhz + .long lhzu + .long lha + .long lhau + .long sth + .long sthu + .long lmw + .long stmw +/* + * handlers + */ +/* + * xform instructions require an additional decode. Fortunately, a relatively + * simple hash step breaks the instructions out with no collisions + */ +xform: + rlwinm r7,r9,31,22,31 /* r7 is secondary opcode */ + rlwinm r10,r7,27,5,31 /* r10 = r7 >> 5 */ + add r10,r7,r10 /* r10 = r7 + r10 */ + rlwinm r10,r10,2,25,29 /* r10 = (r10 & 0x1F) * 4 */ + add r10,r10,r11 /* r10 += anchor point */ + lwz r10, secondary_ht-ref_point(r10) + mtlr r10 + la r7,Open_gpr0(r1) /* r7 is address of GPR 0 in list */ + rlwinm r8,r9,13,25,29 /* r8 is RD * 4 */ + blrl + +secondary_ht: + .long lhzux /* b 0 0x137 */ + .long lhax /* b 1 0x157 */ + .long lhaux /* b 2 0x177 */ + .long sthx /* b 3 0x197 */ + .long sthux /* b 4 0x1b7 */ + .long 0 /* b 5 */ + .long lwbrx /* b 6 0x216 */ + .long 0 /* b 7 */ + .long 0 /* b 8 */ + .long 0 /* b 9 */ + .long stwbrx /* b A 0x296 */ + .long 0 /* b B */ + .long 0 /* b C */ + .long 0 /* b D */ + .long lhbrx /* b E 0x316 */ + .long 0 /* b F */ + .long 0 /* b 10 */ + .long 0 /* b 11 */ + .long sthbrx /* b 12 0x396 */ + .long 0 /* b 13 */ + .long lwarx /* b 14 0x014 */ + .long dcbz /* b 15 0x3f6 */ + .long 0 /* b 16 */ + .long lwzx /* b 17 0x017 */ + .long lwzux /* b 18 0x037 */ + .long 0 /* b 19 */ + .long stwcx /* b 1A 0x096 */ + .long stwx /* b 1B 0x097 */ + .long stwux /* b 1C 0x0B7 */ + .long 0 /* b 1D */ + .long 0 /* b 1E */ + .long lhzx /* b 1F 0x117 */ + +/* + * for all handlers + * r4 - Addressability to interrupt context + * r5 - DEAR address (faulting data address) + * r6 - RA field * 4 + * r7 - Address of GPR 0 in image + * r8 - RD field * 4 + * r9 - Failing instruction + */ + +/* Load halfword algebraic with update */ +lhau: +/* Load halfword algebraic with update indexed */ +lhaux: + stwx r5,r7,r6 /* update RA with effective addr */ + +/* Load halfword algebraic */ +lha: +/* Load halfword algebraic indexed */ +lhax: + lswi r10,r5,2 /* load two bytes into r10 */ + srawi r10,r10,16 /* shift right 2 bytes, extending sign */ + stwx r10,r7,r8 /* update reg image */ + b align_complete /* return */ + +/* Load Half Word Byte-Reversed Indexed */ +lhbrx: + lswi r10,r5,2 /* load two bytes from DEAR into r10 */ + rlwinm r10,r10,0,0,15 /* mask off lower 2 bytes */ + stwbrx r10,r7,r8 /* store reversed in reg image */ + b align_complete /* return */ + +/* Load Half Word and Zero with Update */ +lhzu: +/* Load Half Word and Zero with Update Indexed */ +lhzux: + stwx r5,r7,r6 /* update RA with effective addr */ + +/* Load Half Word and Zero */ +lhz: +/* Load Half Word and Zero Indexed */ +lhzx: + lswi r10,r5,2 /* load two bytes from DEAR into r10 */ + rlwinm r10,r10,16,16,31 /* shift right 2 bytes, with zero fill */ + stwx r10,r7,r8 /* update reg image */ + b align_complete /* return */ + +/* + * Load Multiple Word + */ +lmw: + lwzx r9,r6,r7 /* R9 contains saved value of RA */ + addi r10,r7,32*4 /* r10 points to r31 in image + 4 */ + rlwinm r8,r8,30,2,31 /* r8 >>= 2 (recovers RT) */ + subfic r8,r8,32 /* r8 is reg count to load */ + mtctr r8 /* load counter */ + addi r8,r8,-1 /* r8-- */ + rlwinm r8,r8,2,2,31 /* r8 *= 4 */ + add r5,r5,r8 /* update DEAR to point to last reg */ +lwmloop: + lswi r11,r5,4 /* load r11 with 4 bytes from DEAR */ + stwu r11,-4(r10) /* load image and decrement pointer */ + addi r5,r5,-4 /* decrement effective address */ + bdnz lwmloop + stwx r9,r6,r7 /* restore RA (in case it was trashed) */ + b align_complete /* return */ + +/* + * Load Word and Reserve Indexed + */ +lwarx: + lswi r10,r5,4 /* load four bytes from DEAR into r10 */ + stwx r10,r7,r8 /* update reg image */ + rlwinm r5,r5,0,0,29 /* Word align address */ + lwarx r10,0,r5 /* Set reservation */ + b align_complete /* return */ + +/* + * Load Word Byte-Reversed Indexed + */ +lwbrx: + lswi r10,r5,4 /* load four bytes from DEAR into r10 */ + stwbrx r10,r7,r8 /* store reversed in reg image */ + b align_complete /* return */ + +/* Load Word and Zero with Update */ +lwzu: +/* Load Word and Zero with Update Indexed */ +lwzux: + stwx r5,r7,r6 /* update RA with effective addr */ + +/* Load Word and Zero */ +lwz: +/* Load Word and Zero Indexed */ +lwzx: + lswi r10,r5,4 /* load four bytes from DEAR into r10 */ + stwx r10,r7,r8 /* update reg image */ + b align_complete /* return */ + +/* Store instructions */ + +/* */ +/* Store Half Word and Update */ +sthu: +/* Store Half Word and Update Indexed */ +sthux: + stwx r5,r7,r6 /* Update RA with effective address */ + +/* Store Half Word */ +sth: +/* Store Half Word Indexed */ +sthx: + lwzx r10,r8,r7 /* retrieve source register value */ + rlwinm r10,r10,16,0,15 /* move two bytes to high end of reg */ + stswi r10,r5,2 /* store bytes to DEAR address */ + b align_complete /* return */ + +/* */ +/* Store Half Word Byte-Reversed Indexed */ +sthbrx: + lwbrx r10,r8,r7 /* retrieve src reg value byte reversed */ + stswi r10,r5,2 /* move two bytes to DEAR address */ + b align_complete /* return */ + +/* */ +/* Store Multiple Word */ +stmw: + addi r10,r7,32*4 /* r10 points to r31 in image + 4 */ + rlwinm r8,r8,30,2,31 /* r8 >>= 2 (recovers RT) */ + subfic r8,r8,32 /* r8 is reg count to load */ + mtctr r8 /* load counter */ + addi r8,r8,-1 /* r8-- */ + rlwinm r8,r8,2,2,31 /* r8 *= 4 */ + add r5,r5,r8 /* update DEAR to point to last reg */ +stmloop: + lwzu r11,-4(r10) /* get register value */ + stswi r11,r5,4 /* output to DEAR address */ + addi r5,r5,-4 /* decrement effective address */ + bdnz stmloop + b align_complete /* return */ + +/* */ +/* Store Word and Update */ +stwu: +/* Store Word and Update Indexed */ +stwux: + stwx r5,r7,r6 /* Update RA with effective address */ + +/* Store Word */ +stw: +/* Store Word Indexed */ +stwx: + lwzx r10,r8,r7 /* retrieve source register value */ + stswi r10,r5,4 /* store bytes to DEAR address */ + b align_complete /* return */ + +/* */ +/* Store Word Byte-Reversed Indexed */ +stwbrx: + lwbrx r10,r8,r7 /* retrieve src reg value byte reversed */ + stswi r10,r5,4 /* move two bytes to DEAR address */ + b align_complete /* return */ + +/* */ +/* Store Word Conditional Indexed */ +stwcx: + rlwinm r10,r5,0,0,29 /* r10 = word aligned DEAR */ + lwz r11,0(r10) /* save original value of store */ + stwcx. r11,r0,r10 /* attempt store to address */ + bne stwcx_moveon /* store failed, move on */ + stw r11,0(r10) /* repair damage */ + lwzx r9,r7,r8 /* get register value */ + stswi r10,r5,4 /* store bytes to DEAR address */ +stwcx_moveon: + mfcr r11 /* get condition reg */ + lwz r9,Open_cr(r1) /* get condition reg image */ + rlwimi r9,r11,0,0,2 /* insert 3 CR bits into cr image */ + lwz r11,Open_xer(r1) /* get XER reg */ + rlwimi r9,r11,29,2,2 /* insert XER SO bit into cr image */ + stw r9,Open_cr(r1) /* store cr image */ + b align_complete /* return */ + +/* */ +/* Data Cache Block Zero */ +dcbz: + rlwinm r5,r5,0,0,31-CACHE_SIZE_L2 + /* get address to nearest Cache line */ + addi r5,r5,-4 /* adjust by a word */ + addi r10,r0,CACHE_SIZE/4 /* set counter value */ + mtctr r10 + addi r11,r0,0 /* r11 = 0 */ +dcbz_loop: + stwu r11,4(r5) /* store a word and update EA */ + bdnz dcbz_loop + b align_complete /* return */ + +align_complete: + /*----------------------------------------------------------------------- + * Restore regs and return from the interrupt + *----------------------------------------------------------------------*/ + lmw r24,Open_xer+ALIGN_REGS(r0) + mtxer r24 + mtlr r25 + mtctr r26 + mtcrf 0xFF, r27 + mtspr srr2, r28 /* SRR 2 */ + mtspr srr3, r29 /* SRR 3 */ + mtspr srr0, r30 /* SRR 0 */ + mtspr srr1, r31 /* SRR 1 */ + lmw r1,Open_gpr1+ALIGN_REGS(r0) + lwz r0,Open_gpr0+ALIGN_REGS(r0) + rfi diff --git a/c/src/lib/libbsp/powerpc/psim/vectors/align_h.s b/c/src/lib/libbsp/powerpc/psim/vectors/align_h.s deleted file mode 100644 index d16298343d..0000000000 --- a/c/src/lib/libbsp/powerpc/psim/vectors/align_h.s +++ /dev/null @@ -1,434 +0,0 @@ -/* align_h.s 1.1 - 95/12/04 - * - * This file contains the assembly code for the PowerPC 403 - * alignment exception handler for RTEMS. - * - * Based upon IBM provided code with the following release: - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - * - * Modifications: - * - * Author: Andrew Bray - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * $Id$ - */ - -#include "asm.h" -#include "bsp.h" - -.set CACHE_SIZE,16 # cache line size of 32 bytes -.set CACHE_SIZE_L2,4 # cache line size, log 2 - -.set Open_gpr0,0 -.set Open_gpr1,4 -.set Open_gpr2,8 -.set Open_gpr3,12 -.set Open_gpr4,16 -.set Open_gpr5,20 -.set Open_gpr6,24 -.set Open_gpr7,28 -.set Open_gpr8,32 -.set Open_gpr9,36 -.set Open_gpr10,40 -.set Open_gpr11,44 -.set Open_gpr12,48 -.set Open_gpr13,52 -.set Open_gpr14,56 -.set Open_gpr15,60 -.set Open_gpr16,64 -.set Open_gpr17,68 -.set Open_gpr18,72 -.set Open_gpr19,76 -.set Open_gpr20,80 -.set Open_gpr21,84 -.set Open_gpr22,88 -.set Open_gpr23,92 -.set Open_gpr24,96 -.set Open_gpr25,100 -.set Open_gpr26,104 -.set Open_gpr27,108 -.set Open_gpr28,112 -.set Open_gpr29,116 -.set Open_gpr30,120 -.set Open_gpr31,124 -.set Open_xer,128 -.set Open_lr,132 -.set Open_ctr,136 -.set Open_cr,140 -.set Open_srr2,144 -.set Open_srr3,148 -.set Open_srr0,152 -.set Open_srr1,156 - - -/* - * This code makes several assumptions for processing efficiency - * * General purpose registers are continuous in the image, beginning with - * Open_gpr0 - * * Hash table is highly dependent on opcodes - opcode changes *will* - * require rework of the instruction decode mechanism. - */ - - .text - .globl align_h - - .align CACHE_SIZE_L2 -align_h: - /*----------------------------------------------------------------------- - * Store GPRs in Open Reg save area - * Set up r2 as base reg, r1 pointing to Open Reg save area - *----------------------------------------------------------------------*/ - stmw r0,ALIGN_REGS(r0) - li r1,ALIGN_REGS - /*----------------------------------------------------------------------- - * Store special purpose registers in reg save area - *----------------------------------------------------------------------*/ - mfxer r7 - mflr r8 - mfcr r9 - mfctr r10 - stw r7,Open_xer(r1) - stw r8,Open_lr(r1) - stw r9,Open_cr(r1) - stw r10,Open_ctr(r1) - mfspr r7, srr2 /* SRR 2 */ - mfspr r8, srr3 /* SRR 3 */ - mfspr r9, srr0 /* SRR 0 */ - mfspr r10, srr1 /* SRR 1 */ - stw r7,Open_srr2(r1) - stw r8,Open_srr3(r1) - stw r9,Open_srr0(r1) - stw r10,Open_srr1(r1) - -/* Set up common registers */ - mfspr r5, dear /* DEAR: R5 is data exception address */ - lwz r9,Open_srr0(r1) /* get faulting instruction */ - addi r7,r9,4 /* bump instruction */ - stw r7,Open_srr0(r1) /* restore to image */ - lwz r9, 0(r9) /* retrieve actual instruction */ - rlwinm r6,r9,18,25,29 /* r6 is RA * 4 field from instruction */ - rlwinm r7,r9,6,26,31 /* r7 is primary opcode */ - bl ref_point /* establish addressibility */ -ref_point: - mflr r11 /* r11 is the anchor point for ref_point */ - addi r10, r7, -31 /* r10 = r7 - 31 */ - rlwinm r10,r10,2,2,31 /* r10 *= 4 */ - add r10, r10, r11 /* r10 += anchor point */ - lwz r10, primary_jt-ref_point(r10) - mtlr r10 - rlwinm r8,r9,13,25,29 /* r8 is RD * 4 */ - la r7,Open_gpr0(r1) /* r7 is address of GPR 0 in list */ - blr -primary_jt: - .long xform - .long lwz - .long lwzu - .long 0 - .long 0 - .long stw - .long stwu - .long 0 - .long 0 - .long lhz - .long lhzu - .long lha - .long lhau - .long sth - .long sthu - .long lmw - .long stmw -/* - * handlers - */ -/* - * xform instructions require an additional decode. Fortunately, a relatively - * simple hash step breaks the instructions out with no collisions - */ -xform: - rlwinm r7,r9,31,22,31 /* r7 is secondary opcode */ - rlwinm r10,r7,27,5,31 /* r10 = r7 >> 5 */ - add r10,r7,r10 /* r10 = r7 + r10 */ - rlwinm r10,r10,2,25,29 /* r10 = (r10 & 0x1F) * 4 */ - add r10,r10,r11 /* r10 += anchor point */ - lwz r10, secondary_ht-ref_point(r10) - mtlr r10 - la r7,Open_gpr0(r1) /* r7 is address of GPR 0 in list */ - rlwinm r8,r9,13,25,29 /* r8 is RD * 4 */ - blrl - -secondary_ht: - .long lhzux /* b 0 0x137 */ - .long lhax /* b 1 0x157 */ - .long lhaux /* b 2 0x177 */ - .long sthx /* b 3 0x197 */ - .long sthux /* b 4 0x1b7 */ - .long 0 /* b 5 */ - .long lwbrx /* b 6 0x216 */ - .long 0 /* b 7 */ - .long 0 /* b 8 */ - .long 0 /* b 9 */ - .long stwbrx /* b A 0x296 */ - .long 0 /* b B */ - .long 0 /* b C */ - .long 0 /* b D */ - .long lhbrx /* b E 0x316 */ - .long 0 /* b F */ - .long 0 /* b 10 */ - .long 0 /* b 11 */ - .long sthbrx /* b 12 0x396 */ - .long 0 /* b 13 */ - .long lwarx /* b 14 0x014 */ - .long dcbz /* b 15 0x3f6 */ - .long 0 /* b 16 */ - .long lwzx /* b 17 0x017 */ - .long lwzux /* b 18 0x037 */ - .long 0 /* b 19 */ - .long stwcx /* b 1A 0x096 */ - .long stwx /* b 1B 0x097 */ - .long stwux /* b 1C 0x0B7 */ - .long 0 /* b 1D */ - .long 0 /* b 1E */ - .long lhzx /* b 1F 0x117 */ - -/* - * for all handlers - * r4 - Addressability to interrupt context - * r5 - DEAR address (faulting data address) - * r6 - RA field * 4 - * r7 - Address of GPR 0 in image - * r8 - RD field * 4 - * r9 - Failing instruction - */ - -/* Load halfword algebraic with update */ -lhau: -/* Load halfword algebraic with update indexed */ -lhaux: - stwx r5,r7,r6 /* update RA with effective addr */ - -/* Load halfword algebraic */ -lha: -/* Load halfword algebraic indexed */ -lhax: - lswi r10,r5,2 /* load two bytes into r10 */ - srawi r10,r10,16 /* shift right 2 bytes, extending sign */ - stwx r10,r7,r8 /* update reg image */ - b align_complete /* return */ - -/* Load Half Word Byte-Reversed Indexed */ -lhbrx: - lswi r10,r5,2 /* load two bytes from DEAR into r10 */ - rlwinm r10,r10,0,0,15 /* mask off lower 2 bytes */ - stwbrx r10,r7,r8 /* store reversed in reg image */ - b align_complete /* return */ - -/* Load Half Word and Zero with Update */ -lhzu: -/* Load Half Word and Zero with Update Indexed */ -lhzux: - stwx r5,r7,r6 /* update RA with effective addr */ - -/* Load Half Word and Zero */ -lhz: -/* Load Half Word and Zero Indexed */ -lhzx: - lswi r10,r5,2 /* load two bytes from DEAR into r10 */ - rlwinm r10,r10,16,16,31 /* shift right 2 bytes, with zero fill */ - stwx r10,r7,r8 /* update reg image */ - b align_complete /* return */ - -/* - * Load Multiple Word - */ -lmw: - lwzx r9,r6,r7 /* R9 contains saved value of RA */ - addi r10,r7,32*4 /* r10 points to r31 in image + 4 */ - rlwinm r8,r8,30,2,31 /* r8 >>= 2 (recovers RT) */ - subfic r8,r8,32 /* r8 is reg count to load */ - mtctr r8 /* load counter */ - addi r8,r8,-1 /* r8-- */ - rlwinm r8,r8,2,2,31 /* r8 *= 4 */ - add r5,r5,r8 /* update DEAR to point to last reg */ -lwmloop: - lswi r11,r5,4 /* load r11 with 4 bytes from DEAR */ - stwu r11,-4(r10) /* load image and decrement pointer */ - addi r5,r5,-4 /* decrement effective address */ - bdnz lwmloop - stwx r9,r6,r7 /* restore RA (in case it was trashed) */ - b align_complete /* return */ - -/* - * Load Word and Reserve Indexed - */ -lwarx: - lswi r10,r5,4 /* load four bytes from DEAR into r10 */ - stwx r10,r7,r8 /* update reg image */ - rlwinm r5,r5,0,0,29 /* Word align address */ - lwarx r10,0,r5 /* Set reservation */ - b align_complete /* return */ - -/* - * Load Word Byte-Reversed Indexed - */ -lwbrx: - lswi r10,r5,4 /* load four bytes from DEAR into r10 */ - stwbrx r10,r7,r8 /* store reversed in reg image */ - b align_complete /* return */ - -/* Load Word and Zero with Update */ -lwzu: -/* Load Word and Zero with Update Indexed */ -lwzux: - stwx r5,r7,r6 /* update RA with effective addr */ - -/* Load Word and Zero */ -lwz: -/* Load Word and Zero Indexed */ -lwzx: - lswi r10,r5,4 /* load four bytes from DEAR into r10 */ - stwx r10,r7,r8 /* update reg image */ - b align_complete /* return */ - -/* Store instructions */ - -/* */ -/* Store Half Word and Update */ -sthu: -/* Store Half Word and Update Indexed */ -sthux: - stwx r5,r7,r6 /* Update RA with effective address */ - -/* Store Half Word */ -sth: -/* Store Half Word Indexed */ -sthx: - lwzx r10,r8,r7 /* retrieve source register value */ - rlwinm r10,r10,16,0,15 /* move two bytes to high end of reg */ - stswi r10,r5,2 /* store bytes to DEAR address */ - b align_complete /* return */ - -/* */ -/* Store Half Word Byte-Reversed Indexed */ -sthbrx: - lwbrx r10,r8,r7 /* retrieve src reg value byte reversed */ - stswi r10,r5,2 /* move two bytes to DEAR address */ - b align_complete /* return */ - -/* */ -/* Store Multiple Word */ -stmw: - addi r10,r7,32*4 /* r10 points to r31 in image + 4 */ - rlwinm r8,r8,30,2,31 /* r8 >>= 2 (recovers RT) */ - subfic r8,r8,32 /* r8 is reg count to load */ - mtctr r8 /* load counter */ - addi r8,r8,-1 /* r8-- */ - rlwinm r8,r8,2,2,31 /* r8 *= 4 */ - add r5,r5,r8 /* update DEAR to point to last reg */ -stmloop: - lwzu r11,-4(r10) /* get register value */ - stswi r11,r5,4 /* output to DEAR address */ - addi r5,r5,-4 /* decrement effective address */ - bdnz stmloop - b align_complete /* return */ - -/* */ -/* Store Word and Update */ -stwu: -/* Store Word and Update Indexed */ -stwux: - stwx r5,r7,r6 /* Update RA with effective address */ - -/* Store Word */ -stw: -/* Store Word Indexed */ -stwx: - lwzx r10,r8,r7 /* retrieve source register value */ - stswi r10,r5,4 /* store bytes to DEAR address */ - b align_complete /* return */ - -/* */ -/* Store Word Byte-Reversed Indexed */ -stwbrx: - lwbrx r10,r8,r7 /* retrieve src reg value byte reversed */ - stswi r10,r5,4 /* move two bytes to DEAR address */ - b align_complete /* return */ - -/* */ -/* Store Word Conditional Indexed */ -stwcx: - rlwinm r10,r5,0,0,29 /* r10 = word aligned DEAR */ - lwz r11,0(r10) /* save original value of store */ - stwcx. r11,r0,r10 /* attempt store to address */ - bne stwcx_moveon /* store failed, move on */ - stw r11,0(r10) /* repair damage */ - lwzx r9,r7,r8 /* get register value */ - stswi r10,r5,4 /* store bytes to DEAR address */ -stwcx_moveon: - mfcr r11 /* get condition reg */ - lwz r9,Open_cr(r1) /* get condition reg image */ - rlwimi r9,r11,0,0,2 /* insert 3 CR bits into cr image */ - lwz r11,Open_xer(r1) /* get XER reg */ - rlwimi r9,r11,29,2,2 /* insert XER SO bit into cr image */ - stw r9,Open_cr(r1) /* store cr image */ - b align_complete /* return */ - -/* */ -/* Data Cache Block Zero */ -dcbz: - rlwinm r5,r5,0,0,31-CACHE_SIZE_L2 - /* get address to nearest Cache line */ - addi r5,r5,-4 /* adjust by a word */ - addi r10,r0,CACHE_SIZE/4 /* set counter value */ - mtctr r10 - addi r11,r0,0 /* r11 = 0 */ -dcbz_loop: - stwu r11,4(r5) /* store a word and update EA */ - bdnz dcbz_loop - b align_complete /* return */ - -align_complete: - /*----------------------------------------------------------------------- - * Restore regs and return from the interrupt - *----------------------------------------------------------------------*/ - lmw r24,Open_xer+ALIGN_REGS(r0) - mtxer r24 - mtlr r25 - mtctr r26 - mtcrf 0xFF, r27 - mtspr srr2, r28 /* SRR 2 */ - mtspr srr3, r29 /* SRR 3 */ - mtspr srr0, r30 /* SRR 0 */ - mtspr srr1, r31 /* SRR 1 */ - lmw r1,Open_gpr1+ALIGN_REGS(r0) - lwz r0,Open_gpr0+ALIGN_REGS(r0) - rfi diff --git a/c/src/lib/libbsp/powerpc/psim/vectors/vectors.S b/c/src/lib/libbsp/powerpc/psim/vectors/vectors.S new file mode 100644 index 0000000000..448e9117e2 --- /dev/null +++ b/c/src/lib/libbsp/powerpc/psim/vectors/vectors.S @@ -0,0 +1,123 @@ +/* vectors.s 1.1 - 95/12/04 + * + * This file contains the assembly code for the PowerPC + * interrupt vectors for RTEMS. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +/* + * The issue with this file is getting it loaded at the right place. + * The first vector MUST be at address 0x????0100. + * How this is achieved is dependant on the tool chain. + * + * However the basic mechanism for ELF assemblers is to create a + * section called ".vectors", which will be loaded to an address + * between 0x????0000 and 0x????0100 (inclusive) via a link script. + * + * The basic mechanism for XCOFF assemblers is to place it in the + * normal text section, and arrange for this file to be located + * at an appropriate position on the linker command line. + * + * The variable 'PPC_VECTOR_FILE_BASE' must be defined to be the + * offset from 0x????0000 to the first location in the file. This + * will usually be 0x0000 or 0x0100. + */ + +#include "asm.h" + +#ifndef PPC_VECTOR_FILE_BASE +#error "PPC_VECTOR_FILE_BASE is not defined." +#endif + + /* Where this file will be loaded */ + .set file_base, PPC_VECTOR_FILE_BASE + + /* Offset to store reg 0 */ + + .set IP_LINK, 0 +#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) + .set IP_0, (IP_LINK + 56) +#else + .set IP_0, (IP_LINK + 8) +#endif + .set IP_2, (IP_0 + 4) + + .set IP_3, (IP_2 + 4) + .set IP_4, (IP_3 + 4) + .set IP_5, (IP_4 + 4) + .set IP_6, (IP_5 + 4) + + .set IP_7, (IP_6 + 4) + .set IP_8, (IP_7 + 4) + .set IP_9, (IP_8 + 4) + .set IP_10, (IP_9 + 4) + + .set IP_11, (IP_10 + 4) + .set IP_12, (IP_11 + 4) + .set IP_13, (IP_12 + 4) + .set IP_28, (IP_13 + 4) + + .set IP_29, (IP_28 + 4) + .set IP_30, (IP_29 + 4) + .set IP_31, (IP_30 + 4) + .set IP_CR, (IP_31 + 4) + + .set IP_CTR, (IP_CR + 4) + .set IP_XER, (IP_CTR + 4) + .set IP_LR, (IP_XER + 4) + .set IP_PC, (IP_LR + 4) + + .set IP_MSR, (IP_PC + 4) + + .set IP_END, (IP_MSR + 16) + + /* Vector offsets */ + .set begin_vector,0xFFF00000 + .set crit_vector,0xFFF00100 + .set mach_vector,0xFFF00200 + .set prot_vector,0xFFF00300 + .set ext_vector,0xFFF00500 + .set align_vector,0xFFF00600 + .set prog_vector,0xFFF00700 + .set dec_vector,0xFFF00900 + .set sys_vector,0xFFF00C00 + .set pit_vector,0xFFF01000 + .set fit_vector,0xFFF01010 + .set wadt_vector,0xFFF01020 + .set debug_vector,0xFFF02000 + +/* Go to the right section */ +#if PPC_ASM == PPC_ASM_ELF + .section .vectors,"awx",@progbits +#elif PPC_ASM == PPC_ASM_XCOFF + .csect .text[PR] +#endif + + PUBLIC_VAR (__vectors) +SYM (__vectors): + +/* Decrementer interrupt */ + .org dec_vector - file_base +#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) +#if (PPC_HAS_FPU) + stwu r1, -(20*4 + 18*8 + IP_END)(r1) +#else + stwu r1, -(20*4 + IP_END)(r1) +#endif +#else + stwu r1, -(IP_END)(r1) +#endif + stw r0, IP_0(r1) + + li r0, PPC_IRQ_DECREMENTER + b PROC (_ISR_Handler) + diff --git a/c/src/lib/libbsp/powerpc/psim/vectors/vectors.s b/c/src/lib/libbsp/powerpc/psim/vectors/vectors.s deleted file mode 100644 index 448e9117e2..0000000000 --- a/c/src/lib/libbsp/powerpc/psim/vectors/vectors.s +++ /dev/null @@ -1,123 +0,0 @@ -/* vectors.s 1.1 - 95/12/04 - * - * This file contains the assembly code for the PowerPC - * interrupt vectors for RTEMS. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -/* - * The issue with this file is getting it loaded at the right place. - * The first vector MUST be at address 0x????0100. - * How this is achieved is dependant on the tool chain. - * - * However the basic mechanism for ELF assemblers is to create a - * section called ".vectors", which will be loaded to an address - * between 0x????0000 and 0x????0100 (inclusive) via a link script. - * - * The basic mechanism for XCOFF assemblers is to place it in the - * normal text section, and arrange for this file to be located - * at an appropriate position on the linker command line. - * - * The variable 'PPC_VECTOR_FILE_BASE' must be defined to be the - * offset from 0x????0000 to the first location in the file. This - * will usually be 0x0000 or 0x0100. - */ - -#include "asm.h" - -#ifndef PPC_VECTOR_FILE_BASE -#error "PPC_VECTOR_FILE_BASE is not defined." -#endif - - /* Where this file will be loaded */ - .set file_base, PPC_VECTOR_FILE_BASE - - /* Offset to store reg 0 */ - - .set IP_LINK, 0 -#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) - .set IP_0, (IP_LINK + 56) -#else - .set IP_0, (IP_LINK + 8) -#endif - .set IP_2, (IP_0 + 4) - - .set IP_3, (IP_2 + 4) - .set IP_4, (IP_3 + 4) - .set IP_5, (IP_4 + 4) - .set IP_6, (IP_5 + 4) - - .set IP_7, (IP_6 + 4) - .set IP_8, (IP_7 + 4) - .set IP_9, (IP_8 + 4) - .set IP_10, (IP_9 + 4) - - .set IP_11, (IP_10 + 4) - .set IP_12, (IP_11 + 4) - .set IP_13, (IP_12 + 4) - .set IP_28, (IP_13 + 4) - - .set IP_29, (IP_28 + 4) - .set IP_30, (IP_29 + 4) - .set IP_31, (IP_30 + 4) - .set IP_CR, (IP_31 + 4) - - .set IP_CTR, (IP_CR + 4) - .set IP_XER, (IP_CTR + 4) - .set IP_LR, (IP_XER + 4) - .set IP_PC, (IP_LR + 4) - - .set IP_MSR, (IP_PC + 4) - - .set IP_END, (IP_MSR + 16) - - /* Vector offsets */ - .set begin_vector,0xFFF00000 - .set crit_vector,0xFFF00100 - .set mach_vector,0xFFF00200 - .set prot_vector,0xFFF00300 - .set ext_vector,0xFFF00500 - .set align_vector,0xFFF00600 - .set prog_vector,0xFFF00700 - .set dec_vector,0xFFF00900 - .set sys_vector,0xFFF00C00 - .set pit_vector,0xFFF01000 - .set fit_vector,0xFFF01010 - .set wadt_vector,0xFFF01020 - .set debug_vector,0xFFF02000 - -/* Go to the right section */ -#if PPC_ASM == PPC_ASM_ELF - .section .vectors,"awx",@progbits -#elif PPC_ASM == PPC_ASM_XCOFF - .csect .text[PR] -#endif - - PUBLIC_VAR (__vectors) -SYM (__vectors): - -/* Decrementer interrupt */ - .org dec_vector - file_base -#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) -#if (PPC_HAS_FPU) - stwu r1, -(20*4 + 18*8 + IP_END)(r1) -#else - stwu r1, -(20*4 + IP_END)(r1) -#endif -#else - stwu r1, -(IP_END)(r1) -#endif - stw r0, IP_0(r1) - - li r0, PPC_IRQ_DECREMENTER - b PROC (_ISR_Handler) - diff --git a/c/src/lib/libbsp/powerpc/psim/wrapup/Makefile.in b/c/src/lib/libbsp/powerpc/psim/wrapup/Makefile.in index bae5c6a1ba..db5b9212a9 100644 --- a/c/src/lib/libbsp/powerpc/psim/wrapup/Makefile.in +++ b/c/src/lib/libbsp/powerpc/psim/wrapup/Makefile.in @@ -13,6 +13,9 @@ BSP_PIECES=startup clock console timer vectors CPU_PIECES= GENERIC_PIECES= +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/lib.cfg + ifeq ($(HAS_MP),yes) GENERIC_PIECES += shmdr BSP_PIECES += shmsupp @@ -26,9 +29,6 @@ OBJS=$(foreach piece, $(BSP_PIECES), ../$(piece)/$(ARCH)/$(piece).rel) \ ../../../$(piece)/$(ARCH)/$(piece).rel) LIB=$(ARCH)/libbsp.a -include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg -include $(RTEMS_ROOT)/make/lib.cfg - # # (OPTIONAL) Add local stuff here using += # -- cgit v1.2.3