From acc25eec35e186abc118b9ca4f097e22fc6b4846 Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Thu, 2 Dec 1999 14:31:19 +0000 Subject: Merged of mcp750 and mvme2307 BSP by Eric Valette . As part of this effort, the mpc750 libcpu code is now shared with the ppc6xx. --- .../support/old_exception_processing/ppccache.c | 61 ++++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 c/src/lib/libbsp/powerpc/support/old_exception_processing/ppccache.c (limited to 'c/src/lib/libbsp/powerpc/support/old_exception_processing/ppccache.c') diff --git a/c/src/lib/libbsp/powerpc/support/old_exception_processing/ppccache.c b/c/src/lib/libbsp/powerpc/support/old_exception_processing/ppccache.c new file mode 100644 index 0000000000..ecfb4b96ca --- /dev/null +++ b/c/src/lib/libbsp/powerpc/support/old_exception_processing/ppccache.c @@ -0,0 +1,61 @@ +/* + * PowerPC Cache enable routines + * + * $Id$ + */ + +#include + +#define PPC_Get_HID0( _value ) \ + do { \ + _value = 0; /* to avoid warnings */ \ + asm volatile( \ + "mfspr %0, 0x3f0;" /* get HID0 */ \ + "isync" \ + : "=r" (_value) \ + : "0" (_value) \ + ); \ + } while (0) + +#define PPC_Set_HID0( _value ) \ + do { \ + asm volatile( \ + "isync;" \ + "mtspr 0x3f0, %0;" /* load HID0 */ \ + "isync" \ + : "=r" (_value) \ + : "0" (_value) \ + ); \ + } while (0) + + +void powerpc_instruction_cache_enable () +{ + unsigned32 value; + + /* + * Enable the instruction cache + */ + + PPC_Get_HID0( value ); + + value |= 0x00008000; /* Set ICE bit */ + + PPC_Set_HID0( value ); +} + +void powerpc_data_cache_enable () +{ + unsigned32 value; + + /* + * enable data cache + */ + + PPC_Get_HID0( value ); + + value |= 0x00004000; /* set DCE bit */ + + PPC_Set_HID0( value ); +} + -- cgit v1.2.3