From f5e7b4c36a00afccb90f7e87f667f068bcbb85ea Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Wed, 28 Nov 2001 18:20:10 +0000 Subject: 2001-11-28 Joel Sherrill , This was tracked as PR87. * README, configure.ac, include/Makefile.am, include/bsp.h, start/start.S, startup/FPGA.c, startup/Makefile.am, tod/Makefile.am: Eliminated conditional code for generation 1 boards as these are no longer available. * include/gen1.h, startup/82378zb.c, tod/tod_g1.c: Deleted. --- c/src/lib/libbsp/powerpc/score603e/README | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'c/src/lib/libbsp/powerpc/score603e/README') diff --git a/c/src/lib/libbsp/powerpc/score603e/README b/c/src/lib/libbsp/powerpc/score603e/README index f1b51821a0..4287a2404d 100644 --- a/c/src/lib/libbsp/powerpc/score603e/README +++ b/c/src/lib/libbsp/powerpc/score603e/README @@ -3,7 +3,7 @@ # BSP NAME: score603e -BOARD: VISTA SCORE 603e Generation I and II +BOARD: VISTA SCORE 603e Generation II and beyond BUS: N/A CPU FAMILY: ppc CPU: PowerPC 603e @@ -17,8 +17,7 @@ PERIPHERALS TIMERS: PPC internal Timebase register RESOLUTION: SERIAL PORTS: 2 Z85C30s -REAL-TIME CLOCK: Generation I: SGSM48T18 - Generation II: ICM7170AIBG +REAL-TIME CLOCK: Generation II and beyond: ICM7170AIBG DMA: none VIDEO: none SCSI: none @@ -51,5 +50,6 @@ the OAR Boot chip. The OAR Boot chip contains the basic initialization from the SDS debugger and a jump to flash location 0x04001200. -The compiler option SCORE603E_GENERATION is set to 1 or 2, -for the generation to be produced. +The SCORE603e first generation board is no longer available, +does not appear to be in use by any RTEMS users, and thus +is no longer supported. -- cgit v1.2.3