From 981b99faf208e2c7f6e2b83d73e1b89b669112ee Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Tue, 10 Aug 1999 16:41:44 +0000 Subject: Patch from Eric Valette and Emmanuel Raguet : - the dec21140 driver code has been hardened (various bug fixed) Emmanuel, - bug in the mcp750 init code have been fixed (interrupt stack/initial stack initialization), BSS correctly cleared (Eric V) - remote debugging over TCP/IP is nearly complete (berakpoints, backtrace, variables,...) (Eric V), - exception handling code has also been improved in order to fully support RDBG requirements (Eric V), --- .../powerpc/motorola_powerpc/dec21140/dec21140.c | 5 +-- .../libbsp/powerpc/motorola_powerpc/include/bsp.h | 1 + .../libbsp/powerpc/motorola_powerpc/irq/i8259.c | 15 +++++---- .../lib/libbsp/powerpc/motorola_powerpc/irq/irq.c | 2 +- .../lib/libbsp/powerpc/motorola_powerpc/irq/irq.h | 1 + .../libbsp/powerpc/motorola_powerpc/irq/irq_asm.S | 7 ++++ .../libbsp/powerpc/motorola_powerpc/start/start.S | 38 ++++++---------------- .../powerpc/motorola_powerpc/startup/bspstart.c | 12 +++++-- .../powerpc/motorola_powerpc/vectors/vectors.S | 24 ++++++++++---- .../powerpc/motorola_powerpc/vectors/vectors.h | 11 +++++-- .../motorola_powerpc/vectors/vectors_init.c | 18 +++++++--- 11 files changed, 81 insertions(+), 53 deletions(-) (limited to 'c/src/lib/libbsp/powerpc/motorola_powerpc') diff --git a/c/src/lib/libbsp/powerpc/motorola_powerpc/dec21140/dec21140.c b/c/src/lib/libbsp/powerpc/motorola_powerpc/dec21140/dec21140.c index 9f6252d78b..44a726844a 100644 --- a/c/src/lib/libbsp/powerpc/motorola_powerpc/dec21140/dec21140.c +++ b/c/src/lib/libbsp/powerpc/motorola_powerpc/dec21140/dec21140.c @@ -117,7 +117,7 @@ struct MD { /* * Receive buffer size -- Allow for a full ethernet packet including CRC */ -#define RBUF_SIZE 1520 +#define RBUF_SIZE 1536 #define ET_MINLEN 60 /* minimum message length */ @@ -419,7 +419,8 @@ dec21140Enet_initialize_hardware (struct dec21140_softc *sc) sc->rxBdCount = 0; cp = (char *)malloc((NRXBUFS+NTXBUFS)*(sizeof(struct MD)+ RBUF_SIZE) + PPC_CACHE_ALIGNMENT); sc->bufferBase = cp; - cp += (PPC_CACHE_ALIGNMENT - (int)cp) & MASK_OFFSET; + if ((unsigned int)cp & (PPC_CACHE_ALIGNMENT-1)) + cp = ((unsigned int)cp + PPC_CACHE_ALIGNMENT) & ~(PPC_CACHE_ALIGNMENT-1); #ifdef PCI_BRIDGE_DOES_NOT_ENSURE_CACHE_COHERENCY_FOR_DMA if (_CPU_is_paging_enabled()) _CPU_change_memory_mapping_attribute diff --git a/c/src/lib/libbsp/powerpc/motorola_powerpc/include/bsp.h b/c/src/lib/libbsp/powerpc/motorola_powerpc/include/bsp.h index 0686ee6010..9ec3778d7c 100644 --- a/c/src/lib/libbsp/powerpc/motorola_powerpc/include/bsp.h +++ b/c/src/lib/libbsp/powerpc/motorola_powerpc/include/bsp.h @@ -16,6 +16,7 @@ #include #include #include +#include #ifndef ASM #define outport_byte(port,value) outb(value,port) diff --git a/c/src/lib/libbsp/powerpc/motorola_powerpc/irq/i8259.c b/c/src/lib/libbsp/powerpc/motorola_powerpc/irq/i8259.c index c5c31e2d23..00ed073956 100644 --- a/c/src/lib/libbsp/powerpc/motorola_powerpc/irq/i8259.c +++ b/c/src/lib/libbsp/powerpc/motorola_powerpc/irq/i8259.c @@ -21,9 +21,8 @@ /* * lower byte is interrupt mask on the master PIC. * while upper bits are interrupt on the slave PIC. - * This cache is initialized in ldseg.s */ -volatile rtems_i8259_masks i8259s_cache; +volatile rtems_i8259_masks i8259s_cache = 0xfffb; /*-------------------------------------------------------------------------+ | Function: BSP_irq_disable_at_i8259s @@ -53,7 +52,7 @@ int BSP_irq_disable_at_i8259s (const rtems_irq_symbolic_name irqLine) } else { - outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) > 8)); + outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8)); } _CPU_ISR_Enable (level); @@ -88,7 +87,7 @@ int BSP_irq_enable_at_i8259s (const rtems_irq_symbolic_name irqLine) } else { - outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) > 8)); + outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8)); } _CPU_ISR_Enable (level); @@ -119,9 +118,12 @@ int BSP_irq_enabled_at_i8259s (const rtems_irq_symbolic_name irqLine) int BSP_irq_ack_at_i8259s (const rtems_irq_symbolic_name irqLine) { if (irqLine >= 8) { - outport_byte(PIC_SLAVE_COMMAND_IO_PORT, PIC_EOI); + outport_byte(PIC_MASTER_COMMAND_IO_PORT, SLAVE_PIC_EOSI); + outport_byte(PIC_SLAVE_COMMAND_IO_PORT, (PIC_EOSI | (irqLine - 8))); + } + else { + outport_byte(PIC_MASTER_COMMAND_IO_PORT, (PIC_EOSI | irqLine)); } - outport_byte(PIC_MASTER_COMMAND_IO_PORT, PIC_EOI); return 0; @@ -146,6 +148,5 @@ void BSP_i8259s_init(void) outport_byte(PIC_SLAVE_IMR_IO_PORT, 0x01); /* Select 8086 mode */ outport_byte(PIC_SLAVE_IMR_IO_PORT, 0xFF); /* Mask all */ - i8259s_cache = 0xFFFB; } diff --git a/c/src/lib/libbsp/powerpc/motorola_powerpc/irq/irq.c b/c/src/lib/libbsp/powerpc/motorola_powerpc/irq/irq.c index 54c11b5ee3..4c2226a48f 100644 --- a/c/src/lib/libbsp/powerpc/motorola_powerpc/irq/irq.c +++ b/c/src/lib/libbsp/powerpc/motorola_powerpc/irq/irq.c @@ -378,7 +378,7 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) -void _ThreadProcessSignalsFromIrq (exception_frame* ctx) +void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx) { /* * Process pending signals that have not already been diff --git a/c/src/lib/libbsp/powerpc/motorola_powerpc/irq/irq.h b/c/src/lib/libbsp/powerpc/motorola_powerpc/irq/irq.h index 6f80064847..aaf438c8dd 100644 --- a/c/src/lib/libbsp/powerpc/motorola_powerpc/irq/irq.h +++ b/c/src/lib/libbsp/powerpc/motorola_powerpc/irq/irq.h @@ -54,6 +54,7 @@ /* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */ #define PIC_EOSI 0x60 /* End of Specific Interrupt (EOSI) */ +#define SLAVE_PIC_EOSI 0x62 /* End of Specific Interrupt (EOSI) for cascade */ #define PIC_EOI 0x20 /* Generic End of Interrupt (EOI) */ #ifndef ASM diff --git a/c/src/lib/libbsp/powerpc/motorola_powerpc/irq/irq_asm.S b/c/src/lib/libbsp/powerpc/motorola_powerpc/irq/irq_asm.S index 47c8850510..3d09c16c15 100644 --- a/c/src/lib/libbsp/powerpc/motorola_powerpc/irq/irq_asm.S +++ b/c/src/lib/libbsp/powerpc/motorola_powerpc/irq/irq_asm.S @@ -212,6 +212,13 @@ nested: */ stmw r16, GPR16_OFFSET(r1) addi r3, r1, 0x8 + /* + * compute SP at exception entry + */ + addi r2, r1, EXCEPTION_FRAME_END + /* + * store it at the right place + */ bl _ISR_Signals_to_thread_executing /* * start restoring exception like frame diff --git a/c/src/lib/libbsp/powerpc/motorola_powerpc/start/start.S b/c/src/lib/libbsp/powerpc/motorola_powerpc/start/start.S index 6751f59a0d..cc2dabd2c7 100644 --- a/c/src/lib/libbsp/powerpc/motorola_powerpc/start/start.S +++ b/c/src/lib/libbsp/powerpc/motorola_powerpc/start/start.S @@ -1,35 +1,22 @@ /* - * arch/ppc/kernel/head.S + * start.S : RTEMS entry point * - * $Id$ - * - * PowerPC version - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr * - * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP - * Adapted for Power Macintosh by Paul Mackerras. - * Low-level exception handlers and MMU support - * rewritten by Paul Mackerras. - * Copyright (C) 1996 Paul Mackerras. - * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net). - * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk). + * The license and distribution terms for this file may be + * found in found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. * - * This file contains the low-level support and setup for the - * PowerPC platform, including trap and interrupt dispatch. - * Also included here is low-level thread/task switch support. + * $Id$ * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * */ #include #include #include +#include #include "asm.h" - + #define SYNC \ sync; \ isync @@ -91,8 +78,8 @@ enter_C_code: /* * stack = &__rtems_end + 4096 */ - addis r9,r0, __rtems_end+4096@ha - addi r9,r9, __rtems_end+4096@l + addis r9,r0, __rtems_end+(4096-CPU_MINIMUM_STACK_FRAME_SIZE)@ha + addi r9,r9, __rtems_end+(4096-CPU_MINIMUM_STACK_FRAME_SIZE)@l mr r1, r9 bl zero_bss /* @@ -142,8 +129,3 @@ _return_to_ppcbug: bl MMUon mtctr r30 bctr - - - - - diff --git a/c/src/lib/libbsp/powerpc/motorola_powerpc/startup/bspstart.c b/c/src/lib/libbsp/powerpc/motorola_powerpc/startup/bspstart.c index 63393e2c93..d6d3826c1a 100644 --- a/c/src/lib/libbsp/powerpc/motorola_powerpc/startup/bspstart.c +++ b/c/src/lib/libbsp/powerpc/motorola_powerpc/startup/bspstart.c @@ -131,7 +131,9 @@ void bsp_pretasking_hook(void) heap_size = (BSP_mem_size - heap_start) - BSP_Configuration.work_space_size; +#ifdef SHOW_MORE_INIT_SETTINGS printk(" HEAP start %x size %x\n", heap_start, heap_size); +#endif bsp_libc_init((void *) heap_start, heap_size, 0); #ifdef RTEMS_DEBUG @@ -141,7 +143,7 @@ void bsp_pretasking_hook(void) void zero_bss() { - memset(&__bss_start, 0, &__rtems_end - &__bss_start); + memset(&__bss_start, 0, ((unsigned) (&__rtems_end)) - ((unsigned) &__bss_start)); } void save_boot_params(RESIDUAL* r3, void *r4, void* r5, char *additional_boot_options) @@ -184,7 +186,7 @@ void bsp_start( void ) * the initial stack has aready been set to this value in start.S * so there is no need to set it in r1 again... */ - stack = ((unsigned char*) &__rtems_end) + INIT_STACK_SIZE; + stack = ((unsigned char*) &__rtems_end) + INIT_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE; /* * Initialize the interrupt related settings * SPRG0 = interrupt nesting level count @@ -193,7 +195,7 @@ void bsp_start( void ) * This could be done latter (e.g in IRQ_INIT) but it helps to understand * some settings below... */ - intrStack = ((unsigned char*) &__rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE; + intrStack = ((unsigned char*) &__rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE; asm volatile ("mtspr 273, %0" : "=r" (intrStack) : "0" (intrStack)); asm volatile ("mtspr 272, %0" : "=r" (intrNestingLevel) : "0" (intrNestingLevel)); /* @@ -286,7 +288,9 @@ void bsp_start( void ) Cpu_table.clicks_per_usec = BSP_processor_frequency/(BSP_time_base_divisor * 1000); Cpu_table.exceptions_in_RAM = TRUE; +#ifdef SHOW_MORE_INIT_SETTINGS printk("BSP_Configuration.work_space_size = %x\n", BSP_Configuration.work_space_size); +#endif work_space_start = (unsigned char *)BSP_mem_size - BSP_Configuration.work_space_size; @@ -306,5 +310,7 @@ void bsp_start( void ) * Initalize RTEMS IRQ system */ BSP_rtems_irq_mng_init(0); +#ifdef SHOW_MORE_INIT_SETTINGS printk("Exit from bspstart\n"); +#endif } diff --git a/c/src/lib/libbsp/powerpc/motorola_powerpc/vectors/vectors.S b/c/src/lib/libbsp/powerpc/motorola_powerpc/vectors/vectors.S index 7fe6a82f73..fca0cbfac1 100644 --- a/c/src/lib/libbsp/powerpc/motorola_powerpc/vectors/vectors.S +++ b/c/src/lib/libbsp/powerpc/motorola_powerpc/vectors/vectors.S @@ -86,6 +86,14 @@ SYM (push_normalized_frame): stw r30, EXC_CTR_OFFSET(r1) mfxer r28 stw r28, EXC_XER_OFFSET(r1) + /* + * compute SP at exception entry + */ + addi r2, r1, EXCEPTION_FRAME_END + /* + * store it at the right place + */ + stw r2, GPR1_OFFSET(r1) /* * Enable data and instruction address translation, exception nesting */ @@ -97,8 +105,17 @@ SYM (push_normalized_frame): /* * Call C exception handler */ + /* + * store the execption frame address in r3 (first param) + */ addi r3, r1, 0x8 - bl C_exception_handler + /* + * globalExceptHdl(r3) + */ + addis r4, 0, globalExceptHdl@ha + lwz r5, globalExceptHdl@l(r4) + mtlr r5 + blrl /* * Restore registers status */ @@ -135,8 +152,3 @@ SYM (push_normalized_frame): addi r1,r1, EXCEPTION_FRAME_END SYNC rfi - - - - - diff --git a/c/src/lib/libbsp/powerpc/motorola_powerpc/vectors/vectors.h b/c/src/lib/libbsp/powerpc/motorola_powerpc/vectors/vectors.h index 8b871d74e1..101f46f121 100644 --- a/c/src/lib/libbsp/powerpc/motorola_powerpc/vectors/vectors.h +++ b/c/src/lib/libbsp/powerpc/motorola_powerpc/vectors/vectors.h @@ -128,9 +128,16 @@ typedef struct { unsigned EXC_LR; unsigned EXC_MSR; unsigned EXC_DAR; -} exception_frame; +}BSP_Exception_frame; -extern void C_exception_handler(exception_frame* excPtr); + +typedef void (*exception_handler_t) (BSP_Exception_frame* excPtr); +extern exception_handler_t globalExceptHdl; +/* + * Compatibility with pc386 + */ +typedef BSP_Exception_frame CPU_Exception_frame; +typedef exception_handler_t cpuExcHandlerType; #endif /* ASM */ diff --git a/c/src/lib/libbsp/powerpc/motorola_powerpc/vectors/vectors_init.c b/c/src/lib/libbsp/powerpc/motorola_powerpc/vectors/vectors_init.c index 83adc22db1..7310fbd2c5 100644 --- a/c/src/lib/libbsp/powerpc/motorola_powerpc/vectors/vectors_init.c +++ b/c/src/lib/libbsp/powerpc/motorola_powerpc/vectors/vectors_init.c @@ -19,7 +19,9 @@ static rtems_raw_except_global_settings exception_config; static rtems_raw_except_connect_data exception_table[LAST_VALID_EXC + 1]; -void C_exception_handler(exception_frame* excPtr) +exception_handler_t globalExceptHdl; + +void C_exception_handler(BSP_Exception_frame* excPtr) { int recoverable = 0; @@ -81,9 +83,17 @@ int except_always_enabled(const rtems_raw_except_connect_data* ptr) void initialize_exceptions() { int i; - - exception_config.exceptSize = LAST_VALID_EXC + 1; - exception_config.rawExceptHdlTbl = &exception_table[0]; + + /* + * Initialize pointer used by low level execption handling + */ + globalExceptHdl = C_exception_handler; + /* + * Put default_exception_vector_code_prolog at relevant exception + * code entry addresses + */ + exception_config.exceptSize = LAST_VALID_EXC + 1; + exception_config.rawExceptHdlTbl = &exception_table[0]; exception_config.defaultRawEntry.exceptIndex = 0; exception_config.defaultRawEntry.hdl.vector = 0; exception_config.defaultRawEntry.hdl.raw_hdl = default_exception_vector_code_prolog; -- cgit v1.2.3