From 2d2de4eba16374ea05fc7ee9cd257ad0d4ebf2ca Mon Sep 17 00:00:00 2001 From: Thomas Doerfler Date: Fri, 23 Oct 2009 07:32:46 +0000 Subject: Update for exception support changes. --- c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog | 9 + c/src/lib/libbsp/powerpc/mbx8xx/Makefile.am | 17 +- c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c | 385 ++++++--------------- .../libbsp/powerpc/mbx8xx/make/custom/mbx8xx.inc | 3 +- c/src/lib/libbsp/powerpc/mbx8xx/preinstall.am | 14 +- c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c | 39 ++- c/src/lib/libbsp/powerpc/mbx8xx/startup/linkcmds | 80 ++--- 7 files changed, 200 insertions(+), 347 deletions(-) (limited to 'c/src/lib/libbsp/powerpc/mbx8xx') diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog b/c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog index 99b220dc65..43ed908a1d 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog +++ b/c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog @@ -1,3 +1,12 @@ +2009-10-23 Sebastian Huber + + * include/irq-config.h: New file. + * Makefile.am, preinstall.am: Update for exception support changes. + Use generic interrupt support. + * make/custom/mbx8xx.inc, startup/linkcmds: Enable EABI. + * irq/irq.c, startup/bspstart.c: Converted to generic interrupt + support. Update for exception support changes. + 2009-10-23 Ralf Corsépius * irq/irq.h: Add BSP_irq_enabled_at_cpm. diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/Makefile.am b/c/src/lib/libbsp/powerpc/mbx8xx/Makefile.am index f2e77e6b22..ed8ac4f748 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/Makefile.am +++ b/c/src/lib/libbsp/powerpc/mbx8xx/Makefile.am @@ -21,7 +21,10 @@ noinst_PROGRAMS = include_HEADERS += include/coverhd.h include_bsp_HEADERS = include/mbx.h include/commproc.h include/8xx_immap.h \ - irq/irq.h vectors/vectors.h + irq/irq.h \ + include/irq-config.h \ + ../../shared/include/irq-generic.h \ + ../../shared/include/irq-info.h EXTRA_DIST = times-mbx821 times-mbx860 @@ -35,12 +38,14 @@ libbsp_a_SOURCES += clock/p_clock.c # console libbsp_a_SOURCES += console/console.c # irq -libbsp_a_SOURCES += irq/irq.c irq/irq_asm.S irq/irq_init.c +libbsp_a_SOURCES += irq/irq.c \ + ../../shared/src/irq-generic.c \ + ../../shared/src/irq-legacy.c \ + ../../shared/src/irq-info.c \ + ../../shared/src/irq-shell.c \ + ../../shared/src/irq-server.c # ide libbsp_a_SOURCES += ide/idecfg.c ide/pcmcia_ide.c -# vectors -libbsp_a_SOURCES += vectors/vectors.h vectors/vectors_init.c \ - vectors/vectors.S # startup libbsp_a_SOURCES += ../../shared/bspclean.c ../../shared/bsplibc.c \ ../../shared/bsppost.c ../../shared/bsppredriverhook.c \ @@ -61,7 +66,7 @@ libbsp_a_LIBADD = \ ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \ ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \ ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \ - ../../../libcpu/@RTEMS_CPU@/@exceptions@/raw_exception.rel \ + ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \ ../../../libcpu/@RTEMS_CPU@/mpc8xx/clock.rel \ ../../../libcpu/@RTEMS_CPU@/mpc8xx/console-generic.rel \ ../../../libcpu/@RTEMS_CPU@/mpc8xx/cpm.rel \ diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c b/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c index 8d49448199..0e440984b6 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c +++ b/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c @@ -2,6 +2,8 @@ * * This file contains the implementation of the function described in irq.h * + * Copyright (c) 2009 embedded brains GmbH. + * * Copyright (C) 1998, 1999 valette@crf.canon.fr * * The license and distribution terms for this file may be @@ -14,25 +16,13 @@ #include #include #include -#include -#include -#include +#include #include #include #include #include -/* - * default handler connected on each irq after bsp initialization - */ -static rtems_irq_connect_data default_rtems_entry; - -/* - * location used to store initial tables used for interrupt - * management. - */ -static rtems_irq_global_settings* internal_config; -static rtems_irq_connect_data* rtems_hdl_tbl; +volatile unsigned int ppc_cached_irq_mask; /* * Check if symbolic IRQ name is an SIU IRQ @@ -40,8 +30,8 @@ static rtems_irq_connect_data* rtems_hdl_tbl; static inline int is_siu_irq(const rtems_irq_number irqLine) { return (((int) irqLine <= BSP_SIU_IRQ_MAX_OFFSET) & - ((int) irqLine >= BSP_SIU_IRQ_LOWEST_OFFSET) - ); + ((int) irqLine >= BSP_SIU_IRQ_LOWEST_OFFSET) + ); } /* @@ -50,18 +40,8 @@ static inline int is_siu_irq(const rtems_irq_number irqLine) static inline int is_cpm_irq(const rtems_irq_number irqLine) { return (((int) irqLine <= BSP_CPM_IRQ_MAX_OFFSET) & - ((int) irqLine >= BSP_CPM_IRQ_LOWEST_OFFSET) - ); -} - -/* - * Check if symbolic IRQ name is a Processor IRQ - */ -static inline int is_processor_irq(const rtems_irq_number irqLine) -{ - return (((int) irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) & - ((int) irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) - ); + ((int) irqLine >= BSP_CPM_IRQ_LOWEST_OFFSET) + ); } /* @@ -85,36 +65,6 @@ const static unsigned int SIU_IvectMask[BSP_SIU_IRQ_NUMBER] = 0xFFF00000, 0xFFF80000, 0xFFFC0000, 0xFFFE0000 }; -/* - * ------------------------ RTEMS Irq helper functions ---------------- - */ - -/* - * Caution : this function assumes the variable "internal_config" - * is already set and that the tables it contains are still valid - * and accessible. - */ -static void compute_SIU_IvectMask_from_prio (void) -{ - /* - * In theory this is feasible. No time to code it yet. See i386/shared/irq.c - * for an example based on 8259 controller mask. The actual masks defined - * correspond to the priorities defined for the SIU in irq_init.c. - */ -} - -/* - * This function check that the value given for the irq line - * is valid. - */ - -static int isValidInterrupt(int irq) -{ - if ( (irq < BSP_LOWEST_OFFSET) || (irq > BSP_MAX_OFFSET) || (irq == BSP_CPM_INTERRUPT) ) - return 0; - return 1; -} - int BSP_irq_enable_at_cpm(const rtems_irq_number irqLine) { int cpm_irq_index; @@ -180,7 +130,7 @@ int BSP_irq_disable_at_siu(const rtems_irq_number irqLine) return 0; } -int BSP_irq_enabled_at_siu (const rtems_irq_number irqLine) +int BSP_irq_enabled_at_siu (const rtems_irq_number irqLine) { int siu_irq_index; @@ -191,210 +141,6 @@ int BSP_irq_enabled_at_siu (const rtems_irq_number irqLine) return ppc_cached_irq_mask & (1 << (31-siu_irq_index)); } -/* - * ------------------------ RTEMS Single Irq Handler Mngt Routines ---------------- - */ - -int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) -{ - rtems_interrupt_level level; - - if (!isValidInterrupt(irq->name)) { - return 0; - } - /* - * Check if default handler is actually connected. If not issue an error. - * You must first get the current handler via i386_get_current_idt_entry - * and then disconnect it using i386_delete_idt_entry. - * RATIONALE : to always have the same transition by forcing the user - * to get the previous handler before accepting to disconnect. - */ - if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) { - return 0; - } - - rtems_interrupt_disable(level); - - /* - * store the data provided by user - */ - rtems_hdl_tbl[irq->name] = *irq; - - if (is_cpm_irq(irq->name)) { - /* - * Enable interrupt at PIC level - */ - BSP_irq_enable_at_cpm (irq->name); - } - - if (is_siu_irq(irq->name)) { - /* - * Enable interrupt at SIU level - */ - BSP_irq_enable_at_siu (irq->name); - } - - if (is_processor_irq(irq->name)) { - /* - * Should Enable exception at processor level but not needed. Will restore - * EE flags at the end of the routine anyway. - */ - } - /* - * Enable interrupt on device - */ - if (irq->on) - irq->on(irq); - - rtems_interrupt_enable(level); - - return 1; -} - -int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* irq) -{ - if (!isValidInterrupt(irq->name)) { - return 0; - } - *irq = rtems_hdl_tbl[irq->name]; - return 1; -} - -int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) -{ - rtems_interrupt_level level; - - if (!isValidInterrupt(irq->name)) { - return 0; - } - /* - * Check if default handler is actually connected. If not issue an error. - * You must first get the current handler via i386_get_current_idt_entry - * and then disconnect it using i386_delete_idt_entry. - * RATIONALE : to always have the same transition by forcing the user - * to get the previous handler before accepting to disconnect. - */ - if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) { - return 0; - } - rtems_interrupt_disable(level); - - if (is_cpm_irq(irq->name)) { - /* - * disable interrupt at PIC level - */ - BSP_irq_disable_at_cpm (irq->name); - } - if (is_siu_irq(irq->name)) { - /* - * disable interrupt at OPENPIC level - */ - BSP_irq_disable_at_siu (irq->name); - } - if (is_processor_irq(irq->name)) { - /* - * disable exception at processor level - */ - } - - /* - * Disable interrupt on device - */ - if (irq->off) - irq->off(irq); - - /* - * restore the default irq value - */ - rtems_hdl_tbl[irq->name] = default_rtems_entry; - - rtems_interrupt_enable(level); - - return 1; -} - -/* - * ------------------------ RTEMS Global Irq Handler Mngt Routines ---------------- - */ - -int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config) -{ - int i; - rtems_interrupt_level level; - - /* - * Store various code accelerators - */ - internal_config = config; - default_rtems_entry = config->defaultEntry; - rtems_hdl_tbl = config->irqHdlTbl; - - rtems_interrupt_disable(level); - /* - * start with CPM IRQ - */ - for (i=BSP_CPM_IRQ_LOWEST_OFFSET; i < BSP_CPM_IRQ_LOWEST_OFFSET + BSP_CPM_IRQ_NUMBER ; i++) { - if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { - BSP_irq_enable_at_cpm (i); - if (rtems_hdl_tbl[i].on) - rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); - } - else { - if (rtems_hdl_tbl[i].off) - rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); - BSP_irq_disable_at_cpm (i); - } - } - - /* - * continue with PCI IRQ - */ - /* - * set up internal tables used by rtems interrupt prologue - */ - compute_SIU_IvectMask_from_prio (); - - for (i=BSP_SIU_IRQ_LOWEST_OFFSET; i < BSP_SIU_IRQ_LOWEST_OFFSET + BSP_SIU_IRQ_NUMBER ; i++) { - if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { - BSP_irq_enable_at_siu (i); - if (rtems_hdl_tbl[i].on) - rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); - } - else { - if (rtems_hdl_tbl[i].off) - rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); - BSP_irq_disable_at_siu (i); - } - } - /* - * Must enable CPM interrupt on SIU. CPM on SIU Interrupt level has already been - * set up in BSP_CPM_irq_init. - */ - ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr |= CICR_IEN; - BSP_irq_enable_at_siu (BSP_CPM_INTERRUPT); - /* - * finish with Processor exceptions handled like IRQ - */ - for (i=BSP_PROCESSOR_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER; i++) { - if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { - if (rtems_hdl_tbl[i].on) - rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); - } - else { - if (rtems_hdl_tbl[i].off) - rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); - } - } - rtems_interrupt_enable(level); - return 1; -} - -int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config) -{ - *config = internal_config; - return 0; -} - #ifdef DISPATCH_HANDLER_STAT volatile unsigned int maxLoop = 0; #endif @@ -402,11 +148,11 @@ volatile unsigned int maxLoop = 0; /* * High level IRQ handler called from shared_raw_irq_code_entry */ -int C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) +int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum) { register unsigned int irq; register unsigned cpmIntr; /* boolean */ - register unsigned oldMask; /* old siu pic masks */ + register unsigned oldMask; /* old siu pic masks */ register unsigned msr; register unsigned new_msr; #ifdef DISPATCH_HANDLER_STAT @@ -420,7 +166,7 @@ int C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) new_msr = msr | MSR_EE; _CPU_MSR_SET(new_msr); - rtems_hdl_tbl[BSP_DECREMENTER].hdl(rtems_hdl_tbl[BSP_DECREMENTER].handle); + bsp_interrupt_handler_dispatch(BSP_DECREMENTER); _CPU_MSR_SET(msr); return 0; @@ -482,7 +228,7 @@ int C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) new_msr = msr | MSR_EE; _CPU_MSR_SET(new_msr); - rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle); + bsp_interrupt_handler_dispatch(irq); _CPU_MSR_SET(msr); @@ -505,21 +251,104 @@ int C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) return 0; } -void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx) +void BSP_SIU_irq_init(void) { /* - * Process pending signals that have not already been - * processed by _Thread_Displatch. This happens quite - * unfrequently : the ISR must have posted an action - * to the current running thread. + * In theory we should initialize two registers at least : + * SIMASK, SIEL. SIMASK is reset at 0 value meaning no interrupt. But + * we should take care that a monitor may have restoreed to another value. + * If someone find a reasonnable value for SIEL, AND THE NEED TO CHANGE IT + * please feel free to add it here. */ - if ( _Thread_Do_post_task_switch_extension || - _Thread_Executing->do_post_task_switch_extension ) { - _Thread_Executing->do_post_task_switch_extension = false; - _API_extensions_Run_postswitch(); + ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = 0; + ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_sipend = 0xffff0000; + ppc_cached_irq_mask = 0; + ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel = ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel; +} + +/* + * Initialize CPM interrupt management + */ +void +BSP_CPM_irq_init(void) +{ + /* + * Initialize the CPM interrupt controller. + */ + ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr = +#ifdef mpc860 + (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) | +#else + (CICR_SCB_SCC2 | CICR_SCA_SCC1) | +#endif + ((BSP_CPM_INTERRUPT/2) << 13) | CICR_HP_MASK; + ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr = 0; + + ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr |= CICR_IEN; +} + +rtems_status_code bsp_interrupt_vector_enable( rtems_vector_number irqnum) +{ + if (is_cpm_irq(irqnum)) { + /* + * Enable interrupt at PIC level + */ + BSP_irq_enable_at_cpm (irqnum); + } + + if (is_siu_irq(irqnum)) { + /* + * Enable interrupt at SIU level + */ + BSP_irq_enable_at_siu (irqnum); } + + return RTEMS_SUCCESSFUL; +} + +rtems_status_code bsp_interrupt_vector_disable( rtems_vector_number irqnum) +{ + if (is_cpm_irq(irqnum)) { + /* + * disable interrupt at PIC level + */ + BSP_irq_disable_at_cpm (irqnum); + } + if (is_siu_irq(irqnum)) { + /* + * disable interrupt at OPENPIC level + */ + BSP_irq_disable_at_siu (irqnum); + } + + return RTEMS_SUCCESSFUL; +} + +rtems_status_code bsp_interrupt_facility_initialize() +{ + /* Install exception handler */ + if (ppc_exc_set_handler( ASM_EXT_VECTOR, C_dispatch_irq_handler)) { + return RTEMS_IO_ERROR; + } + if (ppc_exc_set_handler( ASM_DEC_VECTOR, C_dispatch_irq_handler)) { + return RTEMS_IO_ERROR; + } + + /* Initialize the interrupt controller */ + BSP_SIU_irq_init(); + BSP_CPM_irq_init(); + /* - * I plan to process other thread related events here. - * This will include DEBUG session requested from keyboard... + * Must enable CPM interrupt on SIU. CPM on SIU Interrupt level has already been + * set up in BSP_CPM_irq_init. */ + ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr |= CICR_IEN; + BSP_irq_enable_at_siu (BSP_CPM_INTERRUPT); + + return RTEMS_SUCCESSFUL; +} + +void bsp_interrupt_handler_default( rtems_vector_number vector) +{ + printk( "Spurious interrupt: 0x%08x\n", vector); } diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx8xx.inc b/c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx8xx.inc index af7295bdaa..c1a22352e6 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx8xx.inc +++ b/c/src/lib/libbsp/powerpc/mbx8xx/make/custom/mbx8xx.inc @@ -40,7 +40,8 @@ RTEMS_CPU_MODEL=mpc$(8XX_CPU_TYPE) # This contains the compiler options necessary to select the CPU model # and (hopefully) optimize for it. # -CPU_CFLAGS = -mcpu=$(8XX_CPU_TYPE) -Dmpc$(8XX_CPU_TYPE) -D$(RTEMS_MBX_MODEL) +CPU_CFLAGS = -mcpu=$(8XX_CPU_TYPE) -Dmpc$(8XX_CPU_TYPE) -D$(RTEMS_MBX_MODEL) \ + -meabi -msdata -fno-common # optimize flag: typically -O2 CFLAGS_OPTIMIZE_V = -O2 -g -fno-keep-inline-functions diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/preinstall.am b/c/src/lib/libbsp/powerpc/mbx8xx/preinstall.am index 8d95e4580c..5267b248ed 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/preinstall.am +++ b/c/src/lib/libbsp/powerpc/mbx8xx/preinstall.am @@ -68,9 +68,17 @@ $(PROJECT_INCLUDE)/bsp/irq.h: irq/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h -$(PROJECT_INCLUDE)/bsp/vectors.h: vectors/vectors.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vectors.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vectors.h +$(PROJECT_INCLUDE)/bsp/irq-config.h: include/irq-config.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-config.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-config.h + +$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h + +$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h $(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c b/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c index b04323b118..2450f4f83f 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c +++ b/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c @@ -18,8 +18,6 @@ * $Id$ */ -#warning The interrupt disable mask is now stored in SPRG0, please verify that this is compatible to this BSP (see also bootcard.c). - #include #include #include @@ -29,8 +27,6 @@ SPR_RW(SPRG1) -extern unsigned long intrStackPtr; - /* * Driver configuration parameters */ @@ -45,6 +41,9 @@ uint32_t bsp_timer_average_overhead; /* Average overhead of timer in ticks */ uint32_t bsp_timer_least_valid; /* Least valid number from timer */ bool bsp_timer_internal_clock; /* TRUE, when timer runs with CPU clk */ +extern char IntrStack_start []; +extern char intrStack []; + void BSP_panic(char *s) { printk("%s PANIC %s\n",_RTEMS_version, s); @@ -83,9 +82,9 @@ void _BSP_Fatal_error(unsigned int v) */ void bsp_start(void) { + rtems_status_code sc = RTEMS_SUCCESSFUL; ppc_cpu_id_t myCpu; ppc_cpu_revision_t myCpuRevision; - register unsigned char* intrStack; /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function @@ -112,17 +111,22 @@ void bsp_start(void) rtems_cache_enable_data(); #endif #endif - /* - * Initialize some SPRG registers related to irq handling - */ - intrStack = (((unsigned char*)&intrStackPtr) - PPC_MINIMUM_STACK_FRAME_SIZE); - _write_SPRG1((unsigned int)intrStack); - - /* - * Install our own set of exception vectors - */ - initialize_exceptions(); + /* Initialize exception handler */ + sc = ppc_exc_initialize( + PPC_INTERRUPT_DISABLE_MASK_DEFAULT, + (uintptr_t) IntrStack_start, + (uintptr_t) intrStack - (uintptr_t) IntrStack_start + ); + if ( sc != RTEMS_SUCCESSFUL ) { + BSP_panic( "cannot initialize exceptions" ); + } + + /* Initalize interrupt support */ + sc = bsp_interrupt_initialize(); + if ( sc != RTEMS_SUCCESSFUL ) { + BSP_panic( "cannot initialize interrupts" ); + } /* * initialize the device driver parameters @@ -165,10 +169,7 @@ void bsp_start(void) m8xx.scc2p.rbase=0; m8xx.scc2p.tbase=0; m8xx_cp_execute_cmd( M8xx_CR_OP_STOP_TX | M8xx_CR_CHAN_SCC2 ); - /* - * Initalize RTEMS IRQ system - */ - BSP_rtems_irq_mng_init(0); + #ifdef SHOW_MORE_INIT_SETTINGS printk("Exit from bspstart\n"); #endif diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/linkcmds b/c/src/lib/libbsp/powerpc/mbx8xx/startup/linkcmds index a090366a4d..85b0b133b5 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/linkcmds +++ b/c/src/lib/libbsp/powerpc/mbx8xx/startup/linkcmds @@ -21,13 +21,13 @@ RamSize = DEFINED(RamSize) ? RamSize : 4M; HeapSize = DEFINED(HeapSize) ? HeapSize : 0x0; MEMORY - { - ram : org = 0x0, l = 4M - nvram : org = 0xfa000000, l = 32K - dpram : org = 0xfa200000, l = 16K - flash : org = 0xfc000000, l = 2M - immr : org = 0xfa200000, l = 16K - } + { + ram : org = 0x0, l = 4M + nvram : org = 0xfa000000, l = 32K + dpram : org = 0xfa200000, l = 16K + flash : org = 0xfc000000, l = 2M + immr : org = 0xfa200000, l = 16K + } SECTIONS @@ -45,7 +45,7 @@ SECTIONS * The stack will live in this area - between the vectors and * the text section. */ - + .text 0x10000: { /* Read-only sections, merged into text segment: */ @@ -58,10 +58,10 @@ SECTIONS /* Actual code */ *(.text*) - + /* C++ constructors/destructors */ *(.gnu.linkonce.t*) - + /* Initialization and finalization code. * * Various files can provide initialization and finalization functions. @@ -91,14 +91,14 @@ SECTIONS * end terminate with a NULL entry. */ - PROVIDE (__CTOR_LIST__ = .); + PROVIDE (__CTOR_LIST__ = .); /* LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2) */ *crtbegin.o(.ctors) *(.ctors) *crtend.o(.ctors) LONG(0) PROVIDE (__CTOR_END__ = .); - + PROVIDE (__DTOR_LIST__ = .); /* LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2) */ *crtbegin.o(.dtors) @@ -106,7 +106,7 @@ SECTIONS *crtend.o(.dtors) LONG(0) PROVIDE (__DTOR_END__ = .); - + /* * Special FreeBSD sysctl sections. */ @@ -192,12 +192,6 @@ SECTIONS *(.data.*) *(.data1) - PROVIDE (__SDATA_START__ = .); - *(.sdata*) - *(.gnu.linkonce.d*) - *(.gnu.linkonce.s.*) - PROVIDE (__SDATA_END__ = .); - PROVIDE (__EXCEPT_START__ = .); *(.gcc_except_table*) PROVIDE (__EXCEPT_END__ = .); @@ -206,7 +200,7 @@ SECTIONS *(.got.plt) *(.got) PROVIDE(__GOT_END__ = .); - + *(.got1) PROVIDE (__GOT2_START__ = .); @@ -214,40 +208,46 @@ SECTIONS *(.got2) PROVIDE (__GOT2_END__ = .); PROVIDE (_GOT2_END_ = .); - + PROVIDE (__FIXUP_START__ = .); PROVIDE (_FIXUP_START_ = .); *(.fixup) PROVIDE (_FIXUP_END_ = .); PROVIDE (__FIXUP_END__ = .); + } > ram + + .sdata : { + PROVIDE (_SDA_BASE_ = 32768); + *(.sdata .sdata.* .gnu.linkonce.s.*) + } > ram - /* We want the small data sections together, so single-instruction offsets - * can access them all. - */ - PROVIDE (__SDATA2_START__ = .); - *(.sdata2) - *(.gnu.linkonce.s2.*) - *(.sbss2) - PROVIDE (__SDATA2_END__ = .); + .sbss : { + __bss_start = .; + + PROVIDE (__sbss_start = .); PROVIDE (___sbss_start = .); + *(.scommon) + *(.dynsbss) + *(.sbss .sbss.* .gnu.linkonce.sb.*) + PROVIDE (__sbss_end = .); PROVIDE (___sbss_end = .); } > ram - - + + .sdata2 : { + PROVIDE (_SDA2_BASE_ = 32768); + + *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) + } > ram =0 + + .sbss2 : { + *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) + } > ram =0 + .bss : { - PROVIDE (__SBSS_START__ = .); - - PROVIDE (__SBSS2_START__ = .); - *(.sbss2) - PROVIDE (__SBSS2_END__ = .); - bss.start = .; *(.bss .bss* .gnu.linkonce.b*) - *(.sbss*) *(COMMON) . = ALIGN(4); bss.end = .; - - PROVIDE (__SBSS_END__ = .); } > ram -- cgit v1.2.3