From 168ba07c847c15c6911483a965da0942a5a01fcf Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Thu, 6 Jul 2000 20:36:48 +0000 Subject: Patch from Eric Valette and Yacine El Kolli to add support for the mbx860_005b. --- c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c | 58 ++++++++++++++++++-- .../lib/libbsp/powerpc/mbx8xx/startup/mmutlbtab.c | 62 ++++++++++++++++++---- 2 files changed, 107 insertions(+), 13 deletions(-) (limited to 'c/src/lib/libbsp/powerpc/mbx8xx/startup') diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c b/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c index 423f933079..cee1926adc 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c +++ b/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c @@ -274,12 +274,33 @@ void _InitMBX8xx (void) m8xx.plprck = M8xx_UNLOCK_KEY; /* unlock PLPRCR */ #if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) ) m8xx.plprcr = 0x5F500000; -#else +#elif ( defined(mbx860_005b) ) + /* Set the multiplication factor to 0 and clear the timer interrupt status*/ + m8xx.plprcr = 0x00005000; +#elif ( defined(mbx860_001) || \ + defined(mbx860_002) || \ + defined(mbx860_003) || \ + defined(mbx860_004) || \ + defined(mbx860_005) || \ + defined(mbx860_002b) || \ + defined(mbx860_003b) || \ + defined(mbx860_004b) || \ + defined(mbx860_006b) || \ + defined(mbx821_002) || \ + defined(mbx821_003) || \ + defined(mbx821_004) || \ + defined(mbx821_005) || \ + defined(mbx821_002b) || \ + defined(mbx821_003b) || \ + defined(mbx821_004b) || \ + defined(mbx821_005b) ) + defined(mbx821_006b) ) m8xx.plprcr = 0x4C400000; +#else +#error "MBX board not defined" #endif /* Unlock the timebase and decrementer registers. */ m8xx.tbk = M8xx_UNLOCK_KEY; - /* * Initialize decrementer register to a large value to * guarantee that a decrementer interrupt will not be @@ -458,8 +479,37 @@ void _InitMBX8xx (void) * m8xx.memc[1]._or = 0xFFC00400; * m8xx.memc[1]._br = 0x00000081; */ - m8xx.memc[1]._or = M8xx_MEMC_OR_4M | M8xx_MEMC_OR_ATM(0) | - M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0); +#if ( defined(mbx860_001b) ) + m8xx.memc[1]._or = M8xx_MEMC_OR_2M | M8xx_MEMC_OR_ATM(0) | + M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0); +#elif ( defined(mbx860_002b) || \ + defined(mbx860_003b) || \ + defined(mbx821_001b) || \ + defined(mbx821_002b) || \ + defined(mbx821_003b) || \ + defined(mbx860_001) || \ + defined(mbx860_002) || \ + defined(mbx860_003) || \ + defined(mbx821_001) || \ + defined(mbx821_002) || \ + defined(mbx821_003) ) + m8xx.memc[1]._or = M8xx_MEMC_OR_4M | M8xx_MEMC_OR_ATM(0) | + M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0); +#elif ( defined(mbx860_004) || \ + defined(mbx860_005) || \ + defined(mbx860_004b) || \ + defined(mbx860_005b) || \ + defined(mbx860_006b) || \ + defined(mbx821_004) || \ + defined(mbx821_005) || \ + defined(mbx821_004b) || \ + defined(mbx821_005b) || \ + defined(mbx821_006b) ) + m8xx.memc[1]._or = M8xx_MEMC_OR_16M | M8xx_MEMC_OR_ATM(0) | + M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0); +#else +#error "MBX board not defined" +#endif m8xx.memc[1]._br = M8xx_BR_BA(0x00000000) | M8xx_BR_AT(0) | M8xx_BR_PS32 | M8xx_BR_MS_UPMA | M8xx_MEMC_BR_V; diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/mmutlbtab.c b/c/src/lib/libbsp/powerpc/mbx8xx/startup/mmutlbtab.c index 45c22d8951..50e1a57abd 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/mmutlbtab.c +++ b/c/src/lib/libbsp/powerpc/mbx8xx/startup/mmutlbtab.c @@ -31,21 +31,65 @@ * location is equal to its real address. */ MMU_TLB_table_t MMU_TLB_table[] = { - /* +#if ( defined(mbx860_001b) ) + /* + * DRAM: CS1, Start address 0x00000000, 2M, + * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, + * R/W,X for all, no ASID comparison, not cache-inhibited. + * Last 512K block is cache-inhibited, but not guarded for use by EPPCBug. + * EPN TWC RPN + */ + { 0x00000200, 0x05, 0x000009FD }, /* DRAM - PS=512K */ + { 0x00080200, 0x05, 0x000809FD }, /* DRAM - PS=512K */ + { 0x00100200, 0x05, 0x001009FD }, /* DRAM - PS=512K */ + { 0x00180200, 0x05, 0x001809FF }, /* DRAM - PS=512K, cache-inhibited */ +#elif ( defined(mbx860_002b) || \ + defined(mbx860_003b) || \ + defined(mbx821_001b) || \ + defined(mbx821_002b) || \ + defined(mbx821_003b) || \ + defined(mbx860_001) || \ + defined(mbx860_002) || \ + defined(mbx860_003) || \ + defined(mbx821_001) || \ + defined(mbx821_002) || \ + defined(mbx821_003) ) + /* * DRAM: CS1, Start address 0x00000000, 4M, * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, * R/W,X for all, no ASID comparison, not cache-inhibited. * Last 512K block is cache-inhibited, but not guarded for use by EPPCBug. * EPN TWC RPN */ - { 0x00000200, 0x05, 0x000009FD }, /* DRAM - PS=512K */ - { 0x00080200, 0x05, 0x000809FD }, /* DRAM - PS=512K */ - { 0x00100200, 0x05, 0x001009FD }, /* DRAM - PS=512K */ - { 0x00180200, 0x05, 0x001809FD }, /* DRAM - PS=512K */ - { 0x00200200, 0x05, 0x002009FD }, /* DRAM - PS=512K */ - { 0x00280200, 0x05, 0x002809FD }, /* DRAM - PS=512K */ - { 0x00300200, 0x05, 0x003009FD }, /* DRAM - PS=512K */ - { 0x00380200, 0x05, 0x003809FF }, /* DRAM - PS=512K, cache-inhibited */ + { 0x00000200, 0x05, 0x000009FD }, /* DRAM - PS=512K */ + { 0x00080200, 0x05, 0x000809FD }, /* DRAM - PS=512K */ + { 0x00100200, 0x05, 0x001009FD }, /* DRAM - PS=512K */ + { 0x00180200, 0x05, 0x001809FD }, /* DRAM - PS=512K */ + { 0x00200200, 0x05, 0x002009FD }, /* DRAM - PS=512K */ + { 0x00280200, 0x05, 0x002809FD }, /* DRAM - PS=512K */ + { 0x00300200, 0x05, 0x003009FD }, /* DRAM - PS=512K */ + { 0x00380200, 0x05, 0x003809FF }, /* DRAM - PS=512K, cache-inhibited */ +#elif ( defined(mbx860_004) || \ + defined(mbx860_005) || \ + defined(mbx860_004b) || \ + defined(mbx860_005b) || \ + defined(mbx860_006b) || \ + defined(mbx821_004) || \ + defined(mbx821_005) || \ + defined(mbx821_004b) || \ + defined(mbx821_005b) || \ + defined(mbx821_006b) ) + /* + * DRAM: CS1, Start address 0x00000000, 16M, + * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, + * R/W,X for all, no ASID comparison, not cache-inhibited. + * EPN TWC RPN + */ + { 0x00000200, 0x0D, 0x000009FD }, /* DRAM - PS=8M */ + { 0x00800200, 0x0D, 0x008009FD }, /* DRAM - PS=8M */ +#else +#error "MBX board not defined" +#endif /* * * NVRAM: CS4, Start address 0xFA000000, 32K, -- cgit v1.2.3