From a42d8b00fe65a26d923c3bf1429252ee8f1405a0 Mon Sep 17 00:00:00 2001 From: Ralf Corsepius Date: Fri, 11 Feb 2011 12:46:34 +0000 Subject: =?UTF-8?q?2011-02-11=09Ralf=20Cors=C3=A9pius=20?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * console/console.c, irq/irq.c: Use "__asm__" instead of "asm" for improved c99-compliance. --- c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c') diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c b/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c index b2cb7d72f0..f3a32ef668 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c +++ b/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c @@ -222,7 +222,7 @@ int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum) * make sure, that the masking operations in * ICTL and MSR are executed in order */ - asm volatile("sync":::"memory"); + __asm__ volatile("sync":::"memory"); _CPU_MSR_GET(msr); new_msr = msr | MSR_EE; @@ -236,7 +236,7 @@ int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum) * make sure, that the masking operations in * ICTL and MSR are executed in order */ - asm volatile("sync":::"memory"); + __asm__ volatile("sync":::"memory"); if (cpmIntr) { irq -= BSP_CPM_IRQ_LOWEST_OFFSET; -- cgit v1.2.3