From 566c05c896f4431f10d6cb7575eb693924bde975 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Wed, 19 Dec 2012 13:41:27 +0100 Subject: bsp/gen83xx: Fix CSB clock calculation for MPC8309 --- c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'c/src/lib/libbsp/powerpc/gen83xx') diff --git a/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h b/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h index c7c3d2ac14..49ababb672 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h +++ b/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h @@ -361,7 +361,12 @@ * derived values for all boards */ /* value of input clock divider (derived from pll mode reg) */ -#define BSP_SYSPLL_CKID (((mpc83xx.clk.spmr>>(31-8))&0x01)+1) +#if MPC83XX_CHIP_TYPE != 8309 + #define BSP_SYSPLL_CKID (((mpc83xx.clk.spmr>>(31-8))&0x01)+1) +#else + /* On the MPC8309 this bit is reserved */ + #define BSP_SYSPLL_CKID 1 +#endif /* value of system pll (derived from pll mode reg) */ #define BSP_SYSPLL_MF ((mpc83xx.clk.spmr>>(31-7))&0x0f) /* value of system pll (derived from pll mode reg) */ -- cgit v1.2.3