From 7a677fd7d3127d3fd93e32140532d4bad637bb71 Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Wed, 13 Dec 2000 22:16:28 +0000 Subject: 2000-12-13 Joel Sherrill * README: Updated. We are now vectoring a clock tick ISR handler. But RTEMS is not returning from the ISR properly. * clock/clockdrv.c: Now causes interrupts but has not been calibrated. * include/bsp.h: Use * startup/Makefile.am: Add setvec.c from shared. * startup/bspstart.c: Initialize the status register (SR) so no interrupts are masked but global interrupts (SR_IEC) are off. Added call to install the ISR prologue code. * wrapup/Makefile.am: Pick up more pieces from libcpu. --- c/src/lib/libbsp/mips/jmr3904/wrapup/Makefile.am | 2 ++ 1 file changed, 2 insertions(+) (limited to 'c/src/lib/libbsp/mips/jmr3904/wrapup/Makefile.am') diff --git a/c/src/lib/libbsp/mips/jmr3904/wrapup/Makefile.am b/c/src/lib/libbsp/mips/jmr3904/wrapup/Makefile.am index 81b4604e8a..f5c532a23f 100644 --- a/c/src/lib/libbsp/mips/jmr3904/wrapup/Makefile.am +++ b/c/src/lib/libbsp/mips/jmr3904/wrapup/Makefile.am @@ -12,6 +12,8 @@ include $(top_srcdir)/../../../../../../automake/lib.am # bummer; have to use $foreach since % pattern subst rules only replace 1x OBJS = $(foreach piece, $(BSP_FILES), $(wildcard ../$(piece)/$(ARCH)/*.o)) \ + $(wildcard ../../../../libcpu/$(RTEMS_CPU)/shared/*/$(ARCH)/*.o) \ + $(wildcard ../../../../libcpu/$(RTEMS_CPU)/tx39/*/$(ARCH)/*.o) \ $(wildcard ../../../../libcpu/$(RTEMS_CPU)/$(RTEMS_CPU_MODEL)/$(ARCH)/*.o) \ $(foreach piece, $(GENERIC_FILES), ../../../$(piece)/$(ARCH)/$(piece).rel) -- cgit v1.2.3