From 01629105c2817a59a4f1f05039593f211cf5ddaa Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Mon, 14 Dec 1998 23:15:38 +0000 Subject: Patch from Ralf Corsepius to rename all .s files to .S in conformance with GNU conventions. This is a minor step along the way to supporting automake. --- c/src/lib/libbsp/m68k/dmv152/timer/Makefile.in | 6 +- c/src/lib/libbsp/m68k/dmv152/timer/timerisr.S | 38 + c/src/lib/libbsp/m68k/dmv152/timer/timerisr.s | 38 - c/src/lib/libbsp/m68k/gen68302/start/Makefile.in | 6 +- c/src/lib/libbsp/m68k/gen68302/start/start.S | 267 +++++++ c/src/lib/libbsp/m68k/gen68302/start/start302.s | 267 ------- .../lib/libbsp/m68k/gen68302/start302/Makefile.in | 6 +- c/src/lib/libbsp/m68k/gen68302/start302/start302.S | 267 +++++++ c/src/lib/libbsp/m68k/gen68302/start302/start302.s | 267 ------- c/src/lib/libbsp/m68k/gen68302/timer/Makefile.in | 6 +- c/src/lib/libbsp/m68k/gen68302/timer/timerisr.S | 28 + c/src/lib/libbsp/m68k/gen68302/timer/timerisr.s | 28 - c/src/lib/libbsp/m68k/gen68340/console/Makefile.in | 6 +- .../libbsp/m68k/gen68340/console/Modif_cpu_asm.S | 184 +++++ .../libbsp/m68k/gen68340/console/Modif_cpu_asm.s | 184 ----- c/src/lib/libbsp/m68k/gen68340/start/Makefile.in | 6 +- c/src/lib/libbsp/m68k/gen68340/start/start.S | 874 +++++++++++++++++++++ c/src/lib/libbsp/m68k/gen68340/start/start340.s | 874 --------------------- .../libbsp/m68k/gen68340/start/startfor340only.S | 499 ++++++++++++ .../libbsp/m68k/gen68340/start/startfor340only.s | 499 ------------ .../lib/libbsp/m68k/gen68340/start340/Makefile.in | 6 +- c/src/lib/libbsp/m68k/gen68340/start340/start340.S | 874 +++++++++++++++++++++ c/src/lib/libbsp/m68k/gen68340/start340/start340.s | 874 --------------------- .../m68k/gen68340/start340/startfor340only.S | 499 ++++++++++++ .../m68k/gen68340/start340/startfor340only.s | 499 ------------ c/src/lib/libbsp/m68k/gen68360/start/Makefile.in | 6 +- c/src/lib/libbsp/m68k/gen68360/start/start.S | 432 ++++++++++ c/src/lib/libbsp/m68k/gen68360/start/start360.s | 432 ---------- .../lib/libbsp/m68k/gen68360/start360/Makefile.in | 6 +- c/src/lib/libbsp/m68k/gen68360/start360/start360.S | 432 ++++++++++ c/src/lib/libbsp/m68k/gen68360/start360/start360.s | 432 ---------- c/src/lib/libbsp/m68k/idp/timer/Makefile.in | 6 +- c/src/lib/libbsp/m68k/idp/timer/timerisr.S | 38 + c/src/lib/libbsp/m68k/idp/timer/timerisr.s | 38 - c/src/lib/libbsp/m68k/mvme136/timer/Makefile.in | 6 +- c/src/lib/libbsp/m68k/mvme136/timer/timerisr.S | 39 + c/src/lib/libbsp/m68k/mvme136/timer/timerisr.s | 39 - c/src/lib/libbsp/m68k/mvme136/wrapup/Makefile.in | 15 +- c/src/lib/libbsp/m68k/mvme147/timer/Makefile.in | 6 +- c/src/lib/libbsp/m68k/mvme147/timer/timerisr.s | 28 - c/src/lib/libbsp/m68k/mvme147/wrapup/Makefile.in | 4 +- c/src/lib/libbsp/m68k/mvme147s/timer/Makefile.in | 6 +- c/src/lib/libbsp/m68k/mvme147s/wrapup/Makefile.in | 15 +- c/src/lib/libbsp/m68k/mvme162/timer/Makefile.in | 6 +- c/src/lib/libbsp/m68k/mvme162/timer/timerisr.S | 47 ++ c/src/lib/libbsp/m68k/mvme162/timer/timerisr.s | 47 -- c/src/lib/libbsp/m68k/ods68302/start/Makefile.in | 6 +- .../lib/libbsp/m68k/ods68302/start302/Makefile.in | 6 +- c/src/lib/libbsp/m68k/ods68302/timer/Makefile.in | 6 +- c/src/lib/libbsp/m68k/ods68302/timer/timerisr.S | 28 + c/src/lib/libbsp/m68k/ods68302/timer/timerisr.s | 28 - c/src/lib/libbsp/m68k/shared/start.S | 153 ++++ 52 files changed, 4772 insertions(+), 4637 deletions(-) create mode 100644 c/src/lib/libbsp/m68k/dmv152/timer/timerisr.S delete mode 100644 c/src/lib/libbsp/m68k/dmv152/timer/timerisr.s create mode 100644 c/src/lib/libbsp/m68k/gen68302/start/start.S delete mode 100644 c/src/lib/libbsp/m68k/gen68302/start/start302.s create mode 100644 c/src/lib/libbsp/m68k/gen68302/start302/start302.S delete mode 100644 c/src/lib/libbsp/m68k/gen68302/start302/start302.s create mode 100644 c/src/lib/libbsp/m68k/gen68302/timer/timerisr.S delete mode 100644 c/src/lib/libbsp/m68k/gen68302/timer/timerisr.s create mode 100644 c/src/lib/libbsp/m68k/gen68340/console/Modif_cpu_asm.S delete mode 100644 c/src/lib/libbsp/m68k/gen68340/console/Modif_cpu_asm.s create mode 100644 c/src/lib/libbsp/m68k/gen68340/start/start.S delete mode 100644 c/src/lib/libbsp/m68k/gen68340/start/start340.s create mode 100644 c/src/lib/libbsp/m68k/gen68340/start/startfor340only.S delete mode 100644 c/src/lib/libbsp/m68k/gen68340/start/startfor340only.s create mode 100644 c/src/lib/libbsp/m68k/gen68340/start340/start340.S delete mode 100644 c/src/lib/libbsp/m68k/gen68340/start340/start340.s create mode 100644 c/src/lib/libbsp/m68k/gen68340/start340/startfor340only.S delete mode 100644 c/src/lib/libbsp/m68k/gen68340/start340/startfor340only.s create mode 100644 c/src/lib/libbsp/m68k/gen68360/start/start.S delete mode 100644 c/src/lib/libbsp/m68k/gen68360/start/start360.s create mode 100644 c/src/lib/libbsp/m68k/gen68360/start360/start360.S delete mode 100644 c/src/lib/libbsp/m68k/gen68360/start360/start360.s create mode 100644 c/src/lib/libbsp/m68k/idp/timer/timerisr.S delete mode 100644 c/src/lib/libbsp/m68k/idp/timer/timerisr.s create mode 100644 c/src/lib/libbsp/m68k/mvme136/timer/timerisr.S delete mode 100644 c/src/lib/libbsp/m68k/mvme136/timer/timerisr.s delete mode 100644 c/src/lib/libbsp/m68k/mvme147/timer/timerisr.s create mode 100644 c/src/lib/libbsp/m68k/mvme162/timer/timerisr.S delete mode 100644 c/src/lib/libbsp/m68k/mvme162/timer/timerisr.s create mode 100644 c/src/lib/libbsp/m68k/ods68302/timer/timerisr.S delete mode 100644 c/src/lib/libbsp/m68k/ods68302/timer/timerisr.s create mode 100644 c/src/lib/libbsp/m68k/shared/start.S (limited to 'c/src/lib/libbsp/m68k') diff --git a/c/src/lib/libbsp/m68k/dmv152/timer/Makefile.in b/c/src/lib/libbsp/m68k/dmv152/timer/Makefile.in index 24809cbed8..21ca9675e7 100644 --- a/c/src/lib/libbsp/m68k/dmv152/timer/Makefile.in +++ b/c/src/lib/libbsp/m68k/dmv152/timer/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=timerisr -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/m68k/dmv152/timer/timerisr.S b/c/src/lib/libbsp/m68k/dmv152/timer/timerisr.S new file mode 100644 index 0000000000..ef0ed8d212 --- /dev/null +++ b/c/src/lib/libbsp/m68k/dmv152/timer/timerisr.S @@ -0,0 +1,38 @@ +/* timer_isr() + * + * This routine provides the ISR for the Z8536 timer on the DMV152 + * board. The timer is set up to generate an interrupt at maximum + * intervals. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include "asm.h" + +BEGIN_CODE + +.set TIMER, 0x0c000007 | port A +.set CT1_CMD_STATUS, 0x0a | command status register +.set RELOAD, 0x26 | clr IP & IUS,allow countdown + + PUBLIC(timerisr) +SYM (timerisr): + movb #CT1_CMD_STATUS,TIMER | set pointer to cmd status reg + movb #RELOAD,TIMER | reload countdown + addql #1, SYM (Ttimer_val) | increment timer value + rte + +END_CODE +END diff --git a/c/src/lib/libbsp/m68k/dmv152/timer/timerisr.s b/c/src/lib/libbsp/m68k/dmv152/timer/timerisr.s deleted file mode 100644 index ef0ed8d212..0000000000 --- a/c/src/lib/libbsp/m68k/dmv152/timer/timerisr.s +++ /dev/null @@ -1,38 +0,0 @@ -/* timer_isr() - * - * This routine provides the ISR for the Z8536 timer on the DMV152 - * board. The timer is set up to generate an interrupt at maximum - * intervals. - * - * Input parameters: NONE - * - * Output parameters: NONE - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include "asm.h" - -BEGIN_CODE - -.set TIMER, 0x0c000007 | port A -.set CT1_CMD_STATUS, 0x0a | command status register -.set RELOAD, 0x26 | clr IP & IUS,allow countdown - - PUBLIC(timerisr) -SYM (timerisr): - movb #CT1_CMD_STATUS,TIMER | set pointer to cmd status reg - movb #RELOAD,TIMER | reload countdown - addql #1, SYM (Ttimer_val) | increment timer value - rte - -END_CODE -END diff --git a/c/src/lib/libbsp/m68k/gen68302/start/Makefile.in b/c/src/lib/libbsp/m68k/gen68302/start/Makefile.in index d96348b19d..b89be869e6 100644 --- a/c/src/lib/libbsp/m68k/gen68302/start/Makefile.in +++ b/c/src/lib/libbsp/m68k/gen68302/start/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=start302 -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/m68k/gen68302/start/start.S b/c/src/lib/libbsp/m68k/gen68302/start/start.S new file mode 100644 index 0000000000..2a7c652c87 --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68302/start/start.S @@ -0,0 +1,267 @@ +/* entry.s + * + * This file contains the entry point for the application. + * The name of this entry point is compiler dependent. + * It jumps to the BSP which is responsible for performing + * all initialization. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include "asm.h" + + .set BAR, 0xF2 | Base Address Register location + .set SCR, 0xF4 | System Control Register location + .set BAR_VAL, 0x0f7f | BAR value + .set SCR_VAL, 0x00080f00 | SCR value + .set GIMR_VAL, 0x8780 |Global Interrupt Mode Register. (MUST BE WRITTEN). + .set BaseAddr,(BAR_VAL&0x0fff)<<12 | MC68302 internal base address + + .set oSYSRAM, 0x000 | 576 bytes of internal system RAM + + .set oGIMR, 0x812 + + .set oCS0_Base, 0x830 | 16 bits, Chip Sel 0 Base Reg + .set oCS0_Option, 0x832 | 16 bits, Chip Sel 0 Option Reg + .set oCS1_Base, 0x834 | 16 bits, Chip Sel 1 Base Reg + .set oCS1_Option, 0x836 | 16 bits, Chip Sel 1 Option Reg + .set oCS2_Base, 0x838 | 16 bits, Chip Sel 2 Base Reg + .set oCS2_Option, 0x83a | 16 bits, Chip Sel 2 Option Reg + .set oCS3_Base, 0x83c | 16 bits, Chip Sel 3 Base Reg + .set oCS3_Option, 0x83e | 16 bits, Chip Sel 3 Option Reg + + .set tmpSRAM_BASE, 0x400000 | start of temporary SRAM + .set FLASH_BASE, 0xc00000 | start of FLASH''s normal location + + +BEGIN_CODE + PUBLIC (M68Kvec) | Vector Table +SYM (M68Kvec): | standard location for vectors +V___ISSP: .long 0x00001000 |00 0 Reset: Initial SSP +V____IPC: .long SYM(start)-V___ISSP |04 1 Reset: Initial PC +V_BUSERR: .long Bad-V___ISSP |08 2 Bus Error +V_ADRERR: .long Bad-V___ISSP |0c 3 Address Error + .space 240 | reserve space for reset of vectors + +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) +SYM (lowintstack): + .space 4092 | reserve for interrupt stack +SYM (hiintstack): + .space 4 | end of interrupt stack +#endif + + PUBLIC (start) | Default entry point for GNU +SYM (start): + move.w #0x2700,sr | Disable all interrupts + move.w #BAR_VAL,BAR | Set Base Address Register + move.l #SCR_VAL,SCR | Set System Control Register + lea BaseAddr,a5 + move.w #GIMR_VAL,a5@(oGIMR) | Set Global Interrupt Mode Register + +| +| Set up chip select registers for the remapping process. +| + +| +| 0 X x x x x +| 0 000 0 0-- - --- ---- ---- ---- +| x xxx x xxx x xx +| + move.w #0xc001,a5@(oCS0_Base) | Expand CS0 to full size (FLASH) + move.w #0x1f82,a5@(oCS0_Option) | 000000-03ffff, R, 0 WS + +| +| X x x x x x +| 0 100 0 0-- - --- ---- ---- ---- +| x xxx x xxx x xx +| + move.w #0xa801,a5@(oCS1_Base) | Set up and enable CS1 (SRAM) + move.w #0x1f80,a5@(oCS1_Option) | 400000-43ffff, RW, 0 WS + +| +| Copy the initial boot FLASH area to the temporary SRAM location. +| + moveq #0,d0 + movea.l d0,a0 | a0 -> start of FLASH + lea tmpSRAM_BASE,a1 | a1 -> start of tmp SRAM +| moveq #(endPreBoot-V___ISSP)/4,d0 | # longs to copy + moveq #127,d0 +cpy_flash: move.l (a0)+,(a1)+ | copy + subq.l #1,d0 + bne cpy_flash + +| +| Copy remap code to 68302''s internal system RAM. +| + movea.w #begRemap-V___ISSP,a0 | a0 -> remap code + lea a5@(oSYSRAM),a1 | a1 -> internal system RAM +| moveq #(endRemap-begRemap)/2-1,d0 | d0 = # words to copy + moveq #11,d0 +cpy_remap: move.w (a0)+,(a1)+ | copy + dbra d0,cpy_remap + +| +| Jump to the remap code in the 68302''s internal system RAM. +| + jmp a5@(oSYSRAM) | (effectively a jmp begRemap) + +| +| This remap code, when executed from the 68302''s internal system RAM +| will 1) remap CS1 so that SRAM is at 0 +| 2) remap CS0 so that FLASH is at FLASH_BASE +| and 3) jump to executable code in the remapped FLASH. +| +begRemap: move.w #0xa001,a5@(oCS1_Base) | Move CS1 (SRAM) + move.w #0xd801,a5@(oCS0_Base) | Move CS0 (FLASH) + lea FLASH_BASE,a0 + jmp a0@(endRemap-V___ISSP.w) | Jump back to FLASH +endRemap: +| +| Now set up the remaining chip select registers. +| + +| +| 4 0 x x x x +| 1 000 1 111 0 000 0--- ---- ---- +| x xxx x xxx x xx +| + move.w #0xb1e1,a5@(oCS2_Base) | Set up and enable CS2 (dpRAM) + move.w #0x1ff0,a5@(oCS2_Option) | 8f0000-8f07ff, RW, 0 WS + +| +| 8 X x x x x +| 1 000 0 0-- - --- ---- ---- ---- +| x xxx x xxx x xx +| + move.w #0xd001,a5@(oCS3_Base) | Set up and enable CS3 (IO) + move.w #0x1f80,a5@(oCS3_Option) | 800000-83ffff, RW, 0 WS + +endPreBoot: + + move.b #0x30,0x800001 | set status LED amber + + .set oPIOB_Ctrl, 0x824 + .set oPIOB_DDR, 0x826 + .set oPIOB_Data, 0x828 + + .set oPIOA_Ctrl, 0x81e + .set oPIOA_DDR, 0x820 + .set oPIOA_Data, 0x822 + + move.w #0x0ff8,a5@(oPIOB_Data) | Make output follow resistors. + move.w #0x00ff,a5@(oPIOB_DDR) | Set up PB7-PB0 for output. + move.w #0x0080,a5@(oPIOB_Ctrl) | Set up WDOG* as dedicated + | peripheral pins. + + move.w #0x1fff,a5@(oPIOA_Data) | Make output follow resistors. + move.w #0xea2a,a5@(oPIOA_DDR) | Set up PA15-PA0 for in/output. + move.w #0x0003,a5@(oPIOA_Ctrl) | Set up TXD2/RXD2 as dedicated + | peripheral pins. + +| +| Place "Bad" in all vectors from 010 thru 0ec. Vectors 0f0 and 0f4 +| are not set because they are the 68302''s BAR and SCR. +| + movea.w #0x010,a0 + moveq #(0x0f0-0x010)/4-1,d0 + move.l #Bad,d1 +cpy_Bad: move.l d1,(a0)+ + dbra d0,cpy_Bad + + .set vbase, 0x0200 + + lea vbase,a0 + moveq #31,d0 +cpy_Bad1: move.l d1,(a0)+ + dbra d0,cpy_Bad1 + +| +| Fill in special locations to configure OS +| + move.l #Bad,0x008 | Bus Error + move.l #Bad,0x00c | Address Error + move.l #Bad,0x024 | Trace +| move.l #KE_IRET,$0b4 | pSOS+ RET_I Call + +| move.l #_cnsl_isr,vbase+0x028 | SCC2 + move.l #timerisr,vbase+0x018 | Timer ISR + + | + | zero out uninitialized data area + | +zerobss: + moveal # SYM (end),a0 | find end of .bss + moveal # SYM (bss_start),a1 | find beginning of .bss + moveq #0,d0 + +loop: movel d0,a1@+ | to zero out uninitialized + cmpal a0,a1 + jlt loop | loop until _end reached + + movel # SYM (end),d0 | d0 = end of bss/start of heap + addl # SYM (heap_size),d0 | d0 = end of heap + movel d0, SYM (stack_start) | Save for brk() routine + addl # SYM (stack_size),d0 | make room for stack + andl #0xffffffc0,d0 | align it on 16 byte boundary + movw #0x3700,sr | SUPV MODE,INTERRUPTS OFF!!! + movel d0,a7 | set master stack pointer + movel d0,a6 | set base pointer + + /* + * RTEMS should maintain a separate interrupt stack on CPUs + * without one in hardware. This is currently not supported + * on versions of the m68k without a HW intr stack. + */ + +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) + lea SYM (hiintstack),a0 | a0 = high end of intr stack + movec a0,isp | set interrupt stack +#endif + + move.l #0,a7@- | environp + move.l #0,a7@- | argv + move.l #0,a7@- | argc + jsr SYM (boot_card) + + nop +Bad: bra Bad + + nop +END_CODE + + +BEGIN_DATA + + PUBLIC (start_frame) +SYM (start_frame): + .space 4,0 + + PUBLIC (stack_start) +SYM (stack_start): + .space 4,0 +END_DATA + +BEGIN_BSS + + PUBLIC (environ) + .align 2 +SYM (environ): + .long 0 + + PUBLIC (heap_size) + .set SYM (heap_size),0x2000 + + PUBLIC (stack_size) + .set SYM (stack_size),0x1000 + + +END_DATA +END diff --git a/c/src/lib/libbsp/m68k/gen68302/start/start302.s b/c/src/lib/libbsp/m68k/gen68302/start/start302.s deleted file mode 100644 index 2a7c652c87..0000000000 --- a/c/src/lib/libbsp/m68k/gen68302/start/start302.s +++ /dev/null @@ -1,267 +0,0 @@ -/* entry.s - * - * This file contains the entry point for the application. - * The name of this entry point is compiler dependent. - * It jumps to the BSP which is responsible for performing - * all initialization. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include "asm.h" - - .set BAR, 0xF2 | Base Address Register location - .set SCR, 0xF4 | System Control Register location - .set BAR_VAL, 0x0f7f | BAR value - .set SCR_VAL, 0x00080f00 | SCR value - .set GIMR_VAL, 0x8780 |Global Interrupt Mode Register. (MUST BE WRITTEN). - .set BaseAddr,(BAR_VAL&0x0fff)<<12 | MC68302 internal base address - - .set oSYSRAM, 0x000 | 576 bytes of internal system RAM - - .set oGIMR, 0x812 - - .set oCS0_Base, 0x830 | 16 bits, Chip Sel 0 Base Reg - .set oCS0_Option, 0x832 | 16 bits, Chip Sel 0 Option Reg - .set oCS1_Base, 0x834 | 16 bits, Chip Sel 1 Base Reg - .set oCS1_Option, 0x836 | 16 bits, Chip Sel 1 Option Reg - .set oCS2_Base, 0x838 | 16 bits, Chip Sel 2 Base Reg - .set oCS2_Option, 0x83a | 16 bits, Chip Sel 2 Option Reg - .set oCS3_Base, 0x83c | 16 bits, Chip Sel 3 Base Reg - .set oCS3_Option, 0x83e | 16 bits, Chip Sel 3 Option Reg - - .set tmpSRAM_BASE, 0x400000 | start of temporary SRAM - .set FLASH_BASE, 0xc00000 | start of FLASH''s normal location - - -BEGIN_CODE - PUBLIC (M68Kvec) | Vector Table -SYM (M68Kvec): | standard location for vectors -V___ISSP: .long 0x00001000 |00 0 Reset: Initial SSP -V____IPC: .long SYM(start)-V___ISSP |04 1 Reset: Initial PC -V_BUSERR: .long Bad-V___ISSP |08 2 Bus Error -V_ADRERR: .long Bad-V___ISSP |0c 3 Address Error - .space 240 | reserve space for reset of vectors - -#if ( M68K_HAS_SEPARATE_STACKS == 1 ) -SYM (lowintstack): - .space 4092 | reserve for interrupt stack -SYM (hiintstack): - .space 4 | end of interrupt stack -#endif - - PUBLIC (start) | Default entry point for GNU -SYM (start): - move.w #0x2700,sr | Disable all interrupts - move.w #BAR_VAL,BAR | Set Base Address Register - move.l #SCR_VAL,SCR | Set System Control Register - lea BaseAddr,a5 - move.w #GIMR_VAL,a5@(oGIMR) | Set Global Interrupt Mode Register - -| -| Set up chip select registers for the remapping process. -| - -| -| 0 X x x x x -| 0 000 0 0-- - --- ---- ---- ---- -| x xxx x xxx x xx -| - move.w #0xc001,a5@(oCS0_Base) | Expand CS0 to full size (FLASH) - move.w #0x1f82,a5@(oCS0_Option) | 000000-03ffff, R, 0 WS - -| -| X x x x x x -| 0 100 0 0-- - --- ---- ---- ---- -| x xxx x xxx x xx -| - move.w #0xa801,a5@(oCS1_Base) | Set up and enable CS1 (SRAM) - move.w #0x1f80,a5@(oCS1_Option) | 400000-43ffff, RW, 0 WS - -| -| Copy the initial boot FLASH area to the temporary SRAM location. -| - moveq #0,d0 - movea.l d0,a0 | a0 -> start of FLASH - lea tmpSRAM_BASE,a1 | a1 -> start of tmp SRAM -| moveq #(endPreBoot-V___ISSP)/4,d0 | # longs to copy - moveq #127,d0 -cpy_flash: move.l (a0)+,(a1)+ | copy - subq.l #1,d0 - bne cpy_flash - -| -| Copy remap code to 68302''s internal system RAM. -| - movea.w #begRemap-V___ISSP,a0 | a0 -> remap code - lea a5@(oSYSRAM),a1 | a1 -> internal system RAM -| moveq #(endRemap-begRemap)/2-1,d0 | d0 = # words to copy - moveq #11,d0 -cpy_remap: move.w (a0)+,(a1)+ | copy - dbra d0,cpy_remap - -| -| Jump to the remap code in the 68302''s internal system RAM. -| - jmp a5@(oSYSRAM) | (effectively a jmp begRemap) - -| -| This remap code, when executed from the 68302''s internal system RAM -| will 1) remap CS1 so that SRAM is at 0 -| 2) remap CS0 so that FLASH is at FLASH_BASE -| and 3) jump to executable code in the remapped FLASH. -| -begRemap: move.w #0xa001,a5@(oCS1_Base) | Move CS1 (SRAM) - move.w #0xd801,a5@(oCS0_Base) | Move CS0 (FLASH) - lea FLASH_BASE,a0 - jmp a0@(endRemap-V___ISSP.w) | Jump back to FLASH -endRemap: -| -| Now set up the remaining chip select registers. -| - -| -| 4 0 x x x x -| 1 000 1 111 0 000 0--- ---- ---- -| x xxx x xxx x xx -| - move.w #0xb1e1,a5@(oCS2_Base) | Set up and enable CS2 (dpRAM) - move.w #0x1ff0,a5@(oCS2_Option) | 8f0000-8f07ff, RW, 0 WS - -| -| 8 X x x x x -| 1 000 0 0-- - --- ---- ---- ---- -| x xxx x xxx x xx -| - move.w #0xd001,a5@(oCS3_Base) | Set up and enable CS3 (IO) - move.w #0x1f80,a5@(oCS3_Option) | 800000-83ffff, RW, 0 WS - -endPreBoot: - - move.b #0x30,0x800001 | set status LED amber - - .set oPIOB_Ctrl, 0x824 - .set oPIOB_DDR, 0x826 - .set oPIOB_Data, 0x828 - - .set oPIOA_Ctrl, 0x81e - .set oPIOA_DDR, 0x820 - .set oPIOA_Data, 0x822 - - move.w #0x0ff8,a5@(oPIOB_Data) | Make output follow resistors. - move.w #0x00ff,a5@(oPIOB_DDR) | Set up PB7-PB0 for output. - move.w #0x0080,a5@(oPIOB_Ctrl) | Set up WDOG* as dedicated - | peripheral pins. - - move.w #0x1fff,a5@(oPIOA_Data) | Make output follow resistors. - move.w #0xea2a,a5@(oPIOA_DDR) | Set up PA15-PA0 for in/output. - move.w #0x0003,a5@(oPIOA_Ctrl) | Set up TXD2/RXD2 as dedicated - | peripheral pins. - -| -| Place "Bad" in all vectors from 010 thru 0ec. Vectors 0f0 and 0f4 -| are not set because they are the 68302''s BAR and SCR. -| - movea.w #0x010,a0 - moveq #(0x0f0-0x010)/4-1,d0 - move.l #Bad,d1 -cpy_Bad: move.l d1,(a0)+ - dbra d0,cpy_Bad - - .set vbase, 0x0200 - - lea vbase,a0 - moveq #31,d0 -cpy_Bad1: move.l d1,(a0)+ - dbra d0,cpy_Bad1 - -| -| Fill in special locations to configure OS -| - move.l #Bad,0x008 | Bus Error - move.l #Bad,0x00c | Address Error - move.l #Bad,0x024 | Trace -| move.l #KE_IRET,$0b4 | pSOS+ RET_I Call - -| move.l #_cnsl_isr,vbase+0x028 | SCC2 - move.l #timerisr,vbase+0x018 | Timer ISR - - | - | zero out uninitialized data area - | -zerobss: - moveal # SYM (end),a0 | find end of .bss - moveal # SYM (bss_start),a1 | find beginning of .bss - moveq #0,d0 - -loop: movel d0,a1@+ | to zero out uninitialized - cmpal a0,a1 - jlt loop | loop until _end reached - - movel # SYM (end),d0 | d0 = end of bss/start of heap - addl # SYM (heap_size),d0 | d0 = end of heap - movel d0, SYM (stack_start) | Save for brk() routine - addl # SYM (stack_size),d0 | make room for stack - andl #0xffffffc0,d0 | align it on 16 byte boundary - movw #0x3700,sr | SUPV MODE,INTERRUPTS OFF!!! - movel d0,a7 | set master stack pointer - movel d0,a6 | set base pointer - - /* - * RTEMS should maintain a separate interrupt stack on CPUs - * without one in hardware. This is currently not supported - * on versions of the m68k without a HW intr stack. - */ - -#if ( M68K_HAS_SEPARATE_STACKS == 1 ) - lea SYM (hiintstack),a0 | a0 = high end of intr stack - movec a0,isp | set interrupt stack -#endif - - move.l #0,a7@- | environp - move.l #0,a7@- | argv - move.l #0,a7@- | argc - jsr SYM (boot_card) - - nop -Bad: bra Bad - - nop -END_CODE - - -BEGIN_DATA - - PUBLIC (start_frame) -SYM (start_frame): - .space 4,0 - - PUBLIC (stack_start) -SYM (stack_start): - .space 4,0 -END_DATA - -BEGIN_BSS - - PUBLIC (environ) - .align 2 -SYM (environ): - .long 0 - - PUBLIC (heap_size) - .set SYM (heap_size),0x2000 - - PUBLIC (stack_size) - .set SYM (stack_size),0x1000 - - -END_DATA -END diff --git a/c/src/lib/libbsp/m68k/gen68302/start302/Makefile.in b/c/src/lib/libbsp/m68k/gen68302/start302/Makefile.in index d96348b19d..b89be869e6 100644 --- a/c/src/lib/libbsp/m68k/gen68302/start302/Makefile.in +++ b/c/src/lib/libbsp/m68k/gen68302/start302/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=start302 -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/m68k/gen68302/start302/start302.S b/c/src/lib/libbsp/m68k/gen68302/start302/start302.S new file mode 100644 index 0000000000..2a7c652c87 --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68302/start302/start302.S @@ -0,0 +1,267 @@ +/* entry.s + * + * This file contains the entry point for the application. + * The name of this entry point is compiler dependent. + * It jumps to the BSP which is responsible for performing + * all initialization. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include "asm.h" + + .set BAR, 0xF2 | Base Address Register location + .set SCR, 0xF4 | System Control Register location + .set BAR_VAL, 0x0f7f | BAR value + .set SCR_VAL, 0x00080f00 | SCR value + .set GIMR_VAL, 0x8780 |Global Interrupt Mode Register. (MUST BE WRITTEN). + .set BaseAddr,(BAR_VAL&0x0fff)<<12 | MC68302 internal base address + + .set oSYSRAM, 0x000 | 576 bytes of internal system RAM + + .set oGIMR, 0x812 + + .set oCS0_Base, 0x830 | 16 bits, Chip Sel 0 Base Reg + .set oCS0_Option, 0x832 | 16 bits, Chip Sel 0 Option Reg + .set oCS1_Base, 0x834 | 16 bits, Chip Sel 1 Base Reg + .set oCS1_Option, 0x836 | 16 bits, Chip Sel 1 Option Reg + .set oCS2_Base, 0x838 | 16 bits, Chip Sel 2 Base Reg + .set oCS2_Option, 0x83a | 16 bits, Chip Sel 2 Option Reg + .set oCS3_Base, 0x83c | 16 bits, Chip Sel 3 Base Reg + .set oCS3_Option, 0x83e | 16 bits, Chip Sel 3 Option Reg + + .set tmpSRAM_BASE, 0x400000 | start of temporary SRAM + .set FLASH_BASE, 0xc00000 | start of FLASH''s normal location + + +BEGIN_CODE + PUBLIC (M68Kvec) | Vector Table +SYM (M68Kvec): | standard location for vectors +V___ISSP: .long 0x00001000 |00 0 Reset: Initial SSP +V____IPC: .long SYM(start)-V___ISSP |04 1 Reset: Initial PC +V_BUSERR: .long Bad-V___ISSP |08 2 Bus Error +V_ADRERR: .long Bad-V___ISSP |0c 3 Address Error + .space 240 | reserve space for reset of vectors + +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) +SYM (lowintstack): + .space 4092 | reserve for interrupt stack +SYM (hiintstack): + .space 4 | end of interrupt stack +#endif + + PUBLIC (start) | Default entry point for GNU +SYM (start): + move.w #0x2700,sr | Disable all interrupts + move.w #BAR_VAL,BAR | Set Base Address Register + move.l #SCR_VAL,SCR | Set System Control Register + lea BaseAddr,a5 + move.w #GIMR_VAL,a5@(oGIMR) | Set Global Interrupt Mode Register + +| +| Set up chip select registers for the remapping process. +| + +| +| 0 X x x x x +| 0 000 0 0-- - --- ---- ---- ---- +| x xxx x xxx x xx +| + move.w #0xc001,a5@(oCS0_Base) | Expand CS0 to full size (FLASH) + move.w #0x1f82,a5@(oCS0_Option) | 000000-03ffff, R, 0 WS + +| +| X x x x x x +| 0 100 0 0-- - --- ---- ---- ---- +| x xxx x xxx x xx +| + move.w #0xa801,a5@(oCS1_Base) | Set up and enable CS1 (SRAM) + move.w #0x1f80,a5@(oCS1_Option) | 400000-43ffff, RW, 0 WS + +| +| Copy the initial boot FLASH area to the temporary SRAM location. +| + moveq #0,d0 + movea.l d0,a0 | a0 -> start of FLASH + lea tmpSRAM_BASE,a1 | a1 -> start of tmp SRAM +| moveq #(endPreBoot-V___ISSP)/4,d0 | # longs to copy + moveq #127,d0 +cpy_flash: move.l (a0)+,(a1)+ | copy + subq.l #1,d0 + bne cpy_flash + +| +| Copy remap code to 68302''s internal system RAM. +| + movea.w #begRemap-V___ISSP,a0 | a0 -> remap code + lea a5@(oSYSRAM),a1 | a1 -> internal system RAM +| moveq #(endRemap-begRemap)/2-1,d0 | d0 = # words to copy + moveq #11,d0 +cpy_remap: move.w (a0)+,(a1)+ | copy + dbra d0,cpy_remap + +| +| Jump to the remap code in the 68302''s internal system RAM. +| + jmp a5@(oSYSRAM) | (effectively a jmp begRemap) + +| +| This remap code, when executed from the 68302''s internal system RAM +| will 1) remap CS1 so that SRAM is at 0 +| 2) remap CS0 so that FLASH is at FLASH_BASE +| and 3) jump to executable code in the remapped FLASH. +| +begRemap: move.w #0xa001,a5@(oCS1_Base) | Move CS1 (SRAM) + move.w #0xd801,a5@(oCS0_Base) | Move CS0 (FLASH) + lea FLASH_BASE,a0 + jmp a0@(endRemap-V___ISSP.w) | Jump back to FLASH +endRemap: +| +| Now set up the remaining chip select registers. +| + +| +| 4 0 x x x x +| 1 000 1 111 0 000 0--- ---- ---- +| x xxx x xxx x xx +| + move.w #0xb1e1,a5@(oCS2_Base) | Set up and enable CS2 (dpRAM) + move.w #0x1ff0,a5@(oCS2_Option) | 8f0000-8f07ff, RW, 0 WS + +| +| 8 X x x x x +| 1 000 0 0-- - --- ---- ---- ---- +| x xxx x xxx x xx +| + move.w #0xd001,a5@(oCS3_Base) | Set up and enable CS3 (IO) + move.w #0x1f80,a5@(oCS3_Option) | 800000-83ffff, RW, 0 WS + +endPreBoot: + + move.b #0x30,0x800001 | set status LED amber + + .set oPIOB_Ctrl, 0x824 + .set oPIOB_DDR, 0x826 + .set oPIOB_Data, 0x828 + + .set oPIOA_Ctrl, 0x81e + .set oPIOA_DDR, 0x820 + .set oPIOA_Data, 0x822 + + move.w #0x0ff8,a5@(oPIOB_Data) | Make output follow resistors. + move.w #0x00ff,a5@(oPIOB_DDR) | Set up PB7-PB0 for output. + move.w #0x0080,a5@(oPIOB_Ctrl) | Set up WDOG* as dedicated + | peripheral pins. + + move.w #0x1fff,a5@(oPIOA_Data) | Make output follow resistors. + move.w #0xea2a,a5@(oPIOA_DDR) | Set up PA15-PA0 for in/output. + move.w #0x0003,a5@(oPIOA_Ctrl) | Set up TXD2/RXD2 as dedicated + | peripheral pins. + +| +| Place "Bad" in all vectors from 010 thru 0ec. Vectors 0f0 and 0f4 +| are not set because they are the 68302''s BAR and SCR. +| + movea.w #0x010,a0 + moveq #(0x0f0-0x010)/4-1,d0 + move.l #Bad,d1 +cpy_Bad: move.l d1,(a0)+ + dbra d0,cpy_Bad + + .set vbase, 0x0200 + + lea vbase,a0 + moveq #31,d0 +cpy_Bad1: move.l d1,(a0)+ + dbra d0,cpy_Bad1 + +| +| Fill in special locations to configure OS +| + move.l #Bad,0x008 | Bus Error + move.l #Bad,0x00c | Address Error + move.l #Bad,0x024 | Trace +| move.l #KE_IRET,$0b4 | pSOS+ RET_I Call + +| move.l #_cnsl_isr,vbase+0x028 | SCC2 + move.l #timerisr,vbase+0x018 | Timer ISR + + | + | zero out uninitialized data area + | +zerobss: + moveal # SYM (end),a0 | find end of .bss + moveal # SYM (bss_start),a1 | find beginning of .bss + moveq #0,d0 + +loop: movel d0,a1@+ | to zero out uninitialized + cmpal a0,a1 + jlt loop | loop until _end reached + + movel # SYM (end),d0 | d0 = end of bss/start of heap + addl # SYM (heap_size),d0 | d0 = end of heap + movel d0, SYM (stack_start) | Save for brk() routine + addl # SYM (stack_size),d0 | make room for stack + andl #0xffffffc0,d0 | align it on 16 byte boundary + movw #0x3700,sr | SUPV MODE,INTERRUPTS OFF!!! + movel d0,a7 | set master stack pointer + movel d0,a6 | set base pointer + + /* + * RTEMS should maintain a separate interrupt stack on CPUs + * without one in hardware. This is currently not supported + * on versions of the m68k without a HW intr stack. + */ + +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) + lea SYM (hiintstack),a0 | a0 = high end of intr stack + movec a0,isp | set interrupt stack +#endif + + move.l #0,a7@- | environp + move.l #0,a7@- | argv + move.l #0,a7@- | argc + jsr SYM (boot_card) + + nop +Bad: bra Bad + + nop +END_CODE + + +BEGIN_DATA + + PUBLIC (start_frame) +SYM (start_frame): + .space 4,0 + + PUBLIC (stack_start) +SYM (stack_start): + .space 4,0 +END_DATA + +BEGIN_BSS + + PUBLIC (environ) + .align 2 +SYM (environ): + .long 0 + + PUBLIC (heap_size) + .set SYM (heap_size),0x2000 + + PUBLIC (stack_size) + .set SYM (stack_size),0x1000 + + +END_DATA +END diff --git a/c/src/lib/libbsp/m68k/gen68302/start302/start302.s b/c/src/lib/libbsp/m68k/gen68302/start302/start302.s deleted file mode 100644 index 2a7c652c87..0000000000 --- a/c/src/lib/libbsp/m68k/gen68302/start302/start302.s +++ /dev/null @@ -1,267 +0,0 @@ -/* entry.s - * - * This file contains the entry point for the application. - * The name of this entry point is compiler dependent. - * It jumps to the BSP which is responsible for performing - * all initialization. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include "asm.h" - - .set BAR, 0xF2 | Base Address Register location - .set SCR, 0xF4 | System Control Register location - .set BAR_VAL, 0x0f7f | BAR value - .set SCR_VAL, 0x00080f00 | SCR value - .set GIMR_VAL, 0x8780 |Global Interrupt Mode Register. (MUST BE WRITTEN). - .set BaseAddr,(BAR_VAL&0x0fff)<<12 | MC68302 internal base address - - .set oSYSRAM, 0x000 | 576 bytes of internal system RAM - - .set oGIMR, 0x812 - - .set oCS0_Base, 0x830 | 16 bits, Chip Sel 0 Base Reg - .set oCS0_Option, 0x832 | 16 bits, Chip Sel 0 Option Reg - .set oCS1_Base, 0x834 | 16 bits, Chip Sel 1 Base Reg - .set oCS1_Option, 0x836 | 16 bits, Chip Sel 1 Option Reg - .set oCS2_Base, 0x838 | 16 bits, Chip Sel 2 Base Reg - .set oCS2_Option, 0x83a | 16 bits, Chip Sel 2 Option Reg - .set oCS3_Base, 0x83c | 16 bits, Chip Sel 3 Base Reg - .set oCS3_Option, 0x83e | 16 bits, Chip Sel 3 Option Reg - - .set tmpSRAM_BASE, 0x400000 | start of temporary SRAM - .set FLASH_BASE, 0xc00000 | start of FLASH''s normal location - - -BEGIN_CODE - PUBLIC (M68Kvec) | Vector Table -SYM (M68Kvec): | standard location for vectors -V___ISSP: .long 0x00001000 |00 0 Reset: Initial SSP -V____IPC: .long SYM(start)-V___ISSP |04 1 Reset: Initial PC -V_BUSERR: .long Bad-V___ISSP |08 2 Bus Error -V_ADRERR: .long Bad-V___ISSP |0c 3 Address Error - .space 240 | reserve space for reset of vectors - -#if ( M68K_HAS_SEPARATE_STACKS == 1 ) -SYM (lowintstack): - .space 4092 | reserve for interrupt stack -SYM (hiintstack): - .space 4 | end of interrupt stack -#endif - - PUBLIC (start) | Default entry point for GNU -SYM (start): - move.w #0x2700,sr | Disable all interrupts - move.w #BAR_VAL,BAR | Set Base Address Register - move.l #SCR_VAL,SCR | Set System Control Register - lea BaseAddr,a5 - move.w #GIMR_VAL,a5@(oGIMR) | Set Global Interrupt Mode Register - -| -| Set up chip select registers for the remapping process. -| - -| -| 0 X x x x x -| 0 000 0 0-- - --- ---- ---- ---- -| x xxx x xxx x xx -| - move.w #0xc001,a5@(oCS0_Base) | Expand CS0 to full size (FLASH) - move.w #0x1f82,a5@(oCS0_Option) | 000000-03ffff, R, 0 WS - -| -| X x x x x x -| 0 100 0 0-- - --- ---- ---- ---- -| x xxx x xxx x xx -| - move.w #0xa801,a5@(oCS1_Base) | Set up and enable CS1 (SRAM) - move.w #0x1f80,a5@(oCS1_Option) | 400000-43ffff, RW, 0 WS - -| -| Copy the initial boot FLASH area to the temporary SRAM location. -| - moveq #0,d0 - movea.l d0,a0 | a0 -> start of FLASH - lea tmpSRAM_BASE,a1 | a1 -> start of tmp SRAM -| moveq #(endPreBoot-V___ISSP)/4,d0 | # longs to copy - moveq #127,d0 -cpy_flash: move.l (a0)+,(a1)+ | copy - subq.l #1,d0 - bne cpy_flash - -| -| Copy remap code to 68302''s internal system RAM. -| - movea.w #begRemap-V___ISSP,a0 | a0 -> remap code - lea a5@(oSYSRAM),a1 | a1 -> internal system RAM -| moveq #(endRemap-begRemap)/2-1,d0 | d0 = # words to copy - moveq #11,d0 -cpy_remap: move.w (a0)+,(a1)+ | copy - dbra d0,cpy_remap - -| -| Jump to the remap code in the 68302''s internal system RAM. -| - jmp a5@(oSYSRAM) | (effectively a jmp begRemap) - -| -| This remap code, when executed from the 68302''s internal system RAM -| will 1) remap CS1 so that SRAM is at 0 -| 2) remap CS0 so that FLASH is at FLASH_BASE -| and 3) jump to executable code in the remapped FLASH. -| -begRemap: move.w #0xa001,a5@(oCS1_Base) | Move CS1 (SRAM) - move.w #0xd801,a5@(oCS0_Base) | Move CS0 (FLASH) - lea FLASH_BASE,a0 - jmp a0@(endRemap-V___ISSP.w) | Jump back to FLASH -endRemap: -| -| Now set up the remaining chip select registers. -| - -| -| 4 0 x x x x -| 1 000 1 111 0 000 0--- ---- ---- -| x xxx x xxx x xx -| - move.w #0xb1e1,a5@(oCS2_Base) | Set up and enable CS2 (dpRAM) - move.w #0x1ff0,a5@(oCS2_Option) | 8f0000-8f07ff, RW, 0 WS - -| -| 8 X x x x x -| 1 000 0 0-- - --- ---- ---- ---- -| x xxx x xxx x xx -| - move.w #0xd001,a5@(oCS3_Base) | Set up and enable CS3 (IO) - move.w #0x1f80,a5@(oCS3_Option) | 800000-83ffff, RW, 0 WS - -endPreBoot: - - move.b #0x30,0x800001 | set status LED amber - - .set oPIOB_Ctrl, 0x824 - .set oPIOB_DDR, 0x826 - .set oPIOB_Data, 0x828 - - .set oPIOA_Ctrl, 0x81e - .set oPIOA_DDR, 0x820 - .set oPIOA_Data, 0x822 - - move.w #0x0ff8,a5@(oPIOB_Data) | Make output follow resistors. - move.w #0x00ff,a5@(oPIOB_DDR) | Set up PB7-PB0 for output. - move.w #0x0080,a5@(oPIOB_Ctrl) | Set up WDOG* as dedicated - | peripheral pins. - - move.w #0x1fff,a5@(oPIOA_Data) | Make output follow resistors. - move.w #0xea2a,a5@(oPIOA_DDR) | Set up PA15-PA0 for in/output. - move.w #0x0003,a5@(oPIOA_Ctrl) | Set up TXD2/RXD2 as dedicated - | peripheral pins. - -| -| Place "Bad" in all vectors from 010 thru 0ec. Vectors 0f0 and 0f4 -| are not set because they are the 68302''s BAR and SCR. -| - movea.w #0x010,a0 - moveq #(0x0f0-0x010)/4-1,d0 - move.l #Bad,d1 -cpy_Bad: move.l d1,(a0)+ - dbra d0,cpy_Bad - - .set vbase, 0x0200 - - lea vbase,a0 - moveq #31,d0 -cpy_Bad1: move.l d1,(a0)+ - dbra d0,cpy_Bad1 - -| -| Fill in special locations to configure OS -| - move.l #Bad,0x008 | Bus Error - move.l #Bad,0x00c | Address Error - move.l #Bad,0x024 | Trace -| move.l #KE_IRET,$0b4 | pSOS+ RET_I Call - -| move.l #_cnsl_isr,vbase+0x028 | SCC2 - move.l #timerisr,vbase+0x018 | Timer ISR - - | - | zero out uninitialized data area - | -zerobss: - moveal # SYM (end),a0 | find end of .bss - moveal # SYM (bss_start),a1 | find beginning of .bss - moveq #0,d0 - -loop: movel d0,a1@+ | to zero out uninitialized - cmpal a0,a1 - jlt loop | loop until _end reached - - movel # SYM (end),d0 | d0 = end of bss/start of heap - addl # SYM (heap_size),d0 | d0 = end of heap - movel d0, SYM (stack_start) | Save for brk() routine - addl # SYM (stack_size),d0 | make room for stack - andl #0xffffffc0,d0 | align it on 16 byte boundary - movw #0x3700,sr | SUPV MODE,INTERRUPTS OFF!!! - movel d0,a7 | set master stack pointer - movel d0,a6 | set base pointer - - /* - * RTEMS should maintain a separate interrupt stack on CPUs - * without one in hardware. This is currently not supported - * on versions of the m68k without a HW intr stack. - */ - -#if ( M68K_HAS_SEPARATE_STACKS == 1 ) - lea SYM (hiintstack),a0 | a0 = high end of intr stack - movec a0,isp | set interrupt stack -#endif - - move.l #0,a7@- | environp - move.l #0,a7@- | argv - move.l #0,a7@- | argc - jsr SYM (boot_card) - - nop -Bad: bra Bad - - nop -END_CODE - - -BEGIN_DATA - - PUBLIC (start_frame) -SYM (start_frame): - .space 4,0 - - PUBLIC (stack_start) -SYM (stack_start): - .space 4,0 -END_DATA - -BEGIN_BSS - - PUBLIC (environ) - .align 2 -SYM (environ): - .long 0 - - PUBLIC (heap_size) - .set SYM (heap_size),0x2000 - - PUBLIC (stack_size) - .set SYM (stack_size),0x1000 - - -END_DATA -END diff --git a/c/src/lib/libbsp/m68k/gen68302/timer/Makefile.in b/c/src/lib/libbsp/m68k/gen68302/timer/Makefile.in index 24809cbed8..21ca9675e7 100644 --- a/c/src/lib/libbsp/m68k/gen68302/timer/Makefile.in +++ b/c/src/lib/libbsp/m68k/gen68302/timer/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=timerisr -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/m68k/gen68302/timer/timerisr.S b/c/src/lib/libbsp/m68k/gen68302/timer/timerisr.S new file mode 100644 index 0000000000..c804b9dfa6 --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68302/timer/timerisr.S @@ -0,0 +1,28 @@ +/* + * Handle 68302 TIMER2 interrupts. + * + * All code in this routine is pure overhead which can perturb the + * accuracy of RTEMS' timing test suite. + * + * See also: Read_timer() + * + * To reduce overhead this is best to be the "rawest" hardware interupt + * handler you can write. This should be the only interrupt which can + * occur during the measured time period. + * + * An external counter, Timer_interrupts, is incremented. + * + * $Id$ + */ + +#include "asm.h" + +BEGIN_CODE + PUBLIC(timerisr) +SYM(timerisr): + move.w #0x0040,SYM(m302)+2072 | clear interrupt in-service bit + move.b #3,SYM(m302)+2137 | clear timer interrupt event register + addq.l #1,SYM(Timer_interrupts) | increment timer value + rte +END_CODE +END diff --git a/c/src/lib/libbsp/m68k/gen68302/timer/timerisr.s b/c/src/lib/libbsp/m68k/gen68302/timer/timerisr.s deleted file mode 100644 index c804b9dfa6..0000000000 --- a/c/src/lib/libbsp/m68k/gen68302/timer/timerisr.s +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Handle 68302 TIMER2 interrupts. - * - * All code in this routine is pure overhead which can perturb the - * accuracy of RTEMS' timing test suite. - * - * See also: Read_timer() - * - * To reduce overhead this is best to be the "rawest" hardware interupt - * handler you can write. This should be the only interrupt which can - * occur during the measured time period. - * - * An external counter, Timer_interrupts, is incremented. - * - * $Id$ - */ - -#include "asm.h" - -BEGIN_CODE - PUBLIC(timerisr) -SYM(timerisr): - move.w #0x0040,SYM(m302)+2072 | clear interrupt in-service bit - move.b #3,SYM(m302)+2137 | clear timer interrupt event register - addq.l #1,SYM(Timer_interrupts) | increment timer value - rte -END_CODE -END diff --git a/c/src/lib/libbsp/m68k/gen68340/console/Makefile.in b/c/src/lib/libbsp/m68k/gen68340/console/Makefile.in index 62a52b15e6..c26ac13b81 100644 --- a/c/src/lib/libbsp/m68k/gen68340/console/Makefile.in +++ b/c/src/lib/libbsp/m68k/gen68340/console/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=Modif_cpu_asm -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/m68k/gen68340/console/Modif_cpu_asm.S b/c/src/lib/libbsp/m68k/gen68340/console/Modif_cpu_asm.S new file mode 100644 index 0000000000..0da5865fb3 --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68340/console/Modif_cpu_asm.S @@ -0,0 +1,184 @@ +/* cpu_asm.s + * + * This file contains all assembly code for the MC68020 implementation + * of RTEMS. + * + * ATTENTION: Modified for benchmarks + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + + +#include + + .text + +/*PAGE + * void _Debug_ISR_Handler_Console() + * + * This routine provides the RTEMS interrupt management. + * + * NOTE: + * Upon entry, the master stack will contain an interrupt stack frame + * back to the interrupted thread and the interrupt stack will contain + * a throwaway interrupt stack frame. If dispatching is enabled, this + * is the outer most interrupt, and (a context switch is necessary or + * the current thread has signals), then set up the master stack to + * transfer control to the interrupt dispatcher. + * NOTE: + * USED TO MESURE THE TIME SPENT IN THE INTERRUPT SUBROUTINE + * CS5 - CS8 are linked to an oscilloscope so that you can mesure + * RTEMS overhead (BTW it's very short :) ) + */ + +/* + * With this approach, lower priority interrupts may + * execute twice if a higher priority interrupt is + * acknowledged before _Thread_Dispatch_disable is + * increamented and the higher priority interrupt + * preforms a context switch after executing. The lower + * priority intterrupt will execute (1) at the end of the + * higher priority interrupt in the new context if + * permitted by the new interrupt level mask, and (2) when + * the original context regains the cpu. + */ + +#if ( M68K_HAS_VBR == 1) +.set SR_OFFSET, 0 | Status register offset +.set PC_OFFSET, 2 | Program Counter offset +.set FVO_OFFSET, 6 | Format/vector offset +#else +.set SR_OFFSET, 2 | Status register offset +.set PC_OFFSET, 4 | Program Counter offset +.set FVO_OFFSET, 0 | Format/vector offset placed in the stack +#endif /* M68K_HAS_VBR */ + +.set SAVED, 16 | space for saved registers + + .align 4 + .global SYM (_Debug_ISR_Handler_Console) + +SYM (_Debug_ISR_Handler_Console): + + | + tst.w 0x14000000 | ALLUME CS5 + | + + addql #1,SYM (_Thread_Dispatch_disable_level) | disable multitasking + moveml d0-d1/a0-a1,a7@- | save d0-d1,a0-a1 + movew a7@(SAVED+FVO_OFFSET),d0 | d0 = F/VO + andl #0x0fff,d0 | d0 = vector offset in vbr + + +#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 ) + movew sr,d1 | Save status register + oriw #0x700,sr | Disable interrupts + tstl SYM (_ISR_Nest_level) | Interrupting an interrupt handler? + bne 1f | Yes, just skip over stack switch code + movel SYM(_CPU_Interrupt_stack_high),a0 | End of interrupt stack + movel a7,a0@- | Save task stack pointer + movel a0,a7 | Switch to interrupt stack +1: + addql #1,SYM(_ISR_Nest_level) | one nest level deeper + movew d1,sr | Restore status register +#else + addql #1,SYM (_ISR_Nest_level) | one nest level deeper +#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */ + +#if ( M68K_HAS_PREINDEXING == 1 ) + movel @( SYM (_ISR_Vector_table),d0:w:1),a0| fetch the ISR +#else + movel # SYM (_ISR_Vector_table),a0 | a0 = base of RTEMS table + addal d0,a0 | a0 = address of vector + movel (a0),a0 | a0 = address of user routine +#endif + + lsrl #2,d0 | d0 = vector number + movel d0,a7@- | push vector number + + | + tst.w 0x18000000 | ALLUME CS6 + | + + jbsr a0@ | invoke the user ISR + + | + tst.w 0x18000000 | ALLUME CS6 + | + + addql #4,a7 | remove vector number + +#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 ) + movew sr,d0 | Save status register + oriw #0x700,sr | Disable interrupts + subql #1,SYM(_ISR_Nest_level) | Reduce interrupt-nesting count + bne 1f | Skip if return to interrupt + movel (a7),a7 | Restore task stack pointer +1: + movew d0,sr | Restore status register +#else + subql #1,SYM (_ISR_Nest_level) | one less nest level +#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */ + + subql #1,SYM (_Thread_Dispatch_disable_level) + | unnest multitasking + bne Debug_exit | If dispatch disabled, Debug_exit + +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) + movew #0xf000,d0 | isolate format nibble + andw a7@(SAVED+FVO_OFFSET),d0 | get F/VO + cmpiw #0x1000,d0 | is it a throwaway isf? + bne Debug_exit | NOT outer level, so branch +#endif + + tstl SYM (_Context_Switch_necessary) + | Is thread switch necessary? + bne bframe | Yes, invoke dispatcher + + tstl SYM (_ISR_Signals_to_thread_executing) + | signals sent to Run_thread + | while in interrupt handler? + beq Debug_exit | No, then Debug_exit + + +bframe: clrl SYM (_ISR_Signals_to_thread_executing) + | If sent, will be processed +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) + movec msp,a0 | a0 = master stack pointer + movew #0,a0@- | push format word + movel # SYM (_ISR_Dispatch),a0@- | push return addr + | filter out the trace bit to stop single step debugging breaking + movew a0@(6+SR_OFFSET),d0 + andw #0x7FFF,d0 + movew d0,a0@- | push thread sr + movec a0,msp | set master stack pointer +#else + + | filter out the trace bit to stop single step debugging breaking + movew a7@(16+SR_OFFSET),d0 + andw #0x7FFF,d0 + movew d0,sr + jsr SYM (_Thread_Dispatch) +#endif + +Debug_exit: moveml a7@+,d0-d1/a0-a1 | restore d0-d1,a0-a1 +#if ( M68K_HAS_VBR == 0 ) + addql #2,a7 | pop format/id +#endif /* M68K_HAS_VBR */ + + | + tst.w 0x1C000000 | ALLUME CS7 + | + + rte | return to thread + | OR _Isr_dispatch + + diff --git a/c/src/lib/libbsp/m68k/gen68340/console/Modif_cpu_asm.s b/c/src/lib/libbsp/m68k/gen68340/console/Modif_cpu_asm.s deleted file mode 100644 index 0da5865fb3..0000000000 --- a/c/src/lib/libbsp/m68k/gen68340/console/Modif_cpu_asm.s +++ /dev/null @@ -1,184 +0,0 @@ -/* cpu_asm.s - * - * This file contains all assembly code for the MC68020 implementation - * of RTEMS. - * - * ATTENTION: Modified for benchmarks - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - - -#include - - .text - -/*PAGE - * void _Debug_ISR_Handler_Console() - * - * This routine provides the RTEMS interrupt management. - * - * NOTE: - * Upon entry, the master stack will contain an interrupt stack frame - * back to the interrupted thread and the interrupt stack will contain - * a throwaway interrupt stack frame. If dispatching is enabled, this - * is the outer most interrupt, and (a context switch is necessary or - * the current thread has signals), then set up the master stack to - * transfer control to the interrupt dispatcher. - * NOTE: - * USED TO MESURE THE TIME SPENT IN THE INTERRUPT SUBROUTINE - * CS5 - CS8 are linked to an oscilloscope so that you can mesure - * RTEMS overhead (BTW it's very short :) ) - */ - -/* - * With this approach, lower priority interrupts may - * execute twice if a higher priority interrupt is - * acknowledged before _Thread_Dispatch_disable is - * increamented and the higher priority interrupt - * preforms a context switch after executing. The lower - * priority intterrupt will execute (1) at the end of the - * higher priority interrupt in the new context if - * permitted by the new interrupt level mask, and (2) when - * the original context regains the cpu. - */ - -#if ( M68K_HAS_VBR == 1) -.set SR_OFFSET, 0 | Status register offset -.set PC_OFFSET, 2 | Program Counter offset -.set FVO_OFFSET, 6 | Format/vector offset -#else -.set SR_OFFSET, 2 | Status register offset -.set PC_OFFSET, 4 | Program Counter offset -.set FVO_OFFSET, 0 | Format/vector offset placed in the stack -#endif /* M68K_HAS_VBR */ - -.set SAVED, 16 | space for saved registers - - .align 4 - .global SYM (_Debug_ISR_Handler_Console) - -SYM (_Debug_ISR_Handler_Console): - - | - tst.w 0x14000000 | ALLUME CS5 - | - - addql #1,SYM (_Thread_Dispatch_disable_level) | disable multitasking - moveml d0-d1/a0-a1,a7@- | save d0-d1,a0-a1 - movew a7@(SAVED+FVO_OFFSET),d0 | d0 = F/VO - andl #0x0fff,d0 | d0 = vector offset in vbr - - -#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 ) - movew sr,d1 | Save status register - oriw #0x700,sr | Disable interrupts - tstl SYM (_ISR_Nest_level) | Interrupting an interrupt handler? - bne 1f | Yes, just skip over stack switch code - movel SYM(_CPU_Interrupt_stack_high),a0 | End of interrupt stack - movel a7,a0@- | Save task stack pointer - movel a0,a7 | Switch to interrupt stack -1: - addql #1,SYM(_ISR_Nest_level) | one nest level deeper - movew d1,sr | Restore status register -#else - addql #1,SYM (_ISR_Nest_level) | one nest level deeper -#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */ - -#if ( M68K_HAS_PREINDEXING == 1 ) - movel @( SYM (_ISR_Vector_table),d0:w:1),a0| fetch the ISR -#else - movel # SYM (_ISR_Vector_table),a0 | a0 = base of RTEMS table - addal d0,a0 | a0 = address of vector - movel (a0),a0 | a0 = address of user routine -#endif - - lsrl #2,d0 | d0 = vector number - movel d0,a7@- | push vector number - - | - tst.w 0x18000000 | ALLUME CS6 - | - - jbsr a0@ | invoke the user ISR - - | - tst.w 0x18000000 | ALLUME CS6 - | - - addql #4,a7 | remove vector number - -#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 ) - movew sr,d0 | Save status register - oriw #0x700,sr | Disable interrupts - subql #1,SYM(_ISR_Nest_level) | Reduce interrupt-nesting count - bne 1f | Skip if return to interrupt - movel (a7),a7 | Restore task stack pointer -1: - movew d0,sr | Restore status register -#else - subql #1,SYM (_ISR_Nest_level) | one less nest level -#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */ - - subql #1,SYM (_Thread_Dispatch_disable_level) - | unnest multitasking - bne Debug_exit | If dispatch disabled, Debug_exit - -#if ( M68K_HAS_SEPARATE_STACKS == 1 ) - movew #0xf000,d0 | isolate format nibble - andw a7@(SAVED+FVO_OFFSET),d0 | get F/VO - cmpiw #0x1000,d0 | is it a throwaway isf? - bne Debug_exit | NOT outer level, so branch -#endif - - tstl SYM (_Context_Switch_necessary) - | Is thread switch necessary? - bne bframe | Yes, invoke dispatcher - - tstl SYM (_ISR_Signals_to_thread_executing) - | signals sent to Run_thread - | while in interrupt handler? - beq Debug_exit | No, then Debug_exit - - -bframe: clrl SYM (_ISR_Signals_to_thread_executing) - | If sent, will be processed -#if ( M68K_HAS_SEPARATE_STACKS == 1 ) - movec msp,a0 | a0 = master stack pointer - movew #0,a0@- | push format word - movel # SYM (_ISR_Dispatch),a0@- | push return addr - | filter out the trace bit to stop single step debugging breaking - movew a0@(6+SR_OFFSET),d0 - andw #0x7FFF,d0 - movew d0,a0@- | push thread sr - movec a0,msp | set master stack pointer -#else - - | filter out the trace bit to stop single step debugging breaking - movew a7@(16+SR_OFFSET),d0 - andw #0x7FFF,d0 - movew d0,sr - jsr SYM (_Thread_Dispatch) -#endif - -Debug_exit: moveml a7@+,d0-d1/a0-a1 | restore d0-d1,a0-a1 -#if ( M68K_HAS_VBR == 0 ) - addql #2,a7 | pop format/id -#endif /* M68K_HAS_VBR */ - - | - tst.w 0x1C000000 | ALLUME CS7 - | - - rte | return to thread - | OR _Isr_dispatch - - diff --git a/c/src/lib/libbsp/m68k/gen68340/start/Makefile.in b/c/src/lib/libbsp/m68k/gen68340/start/Makefile.in index ce91b95e3b..4dfebd249f 100644 --- a/c/src/lib/libbsp/m68k/gen68340/start/Makefile.in +++ b/c/src/lib/libbsp/m68k/gen68340/start/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=start340 -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/m68k/gen68340/start/start.S b/c/src/lib/libbsp/m68k/gen68340/start/start.S new file mode 100644 index 0000000000..58ea0c92d0 --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68340/start/start.S @@ -0,0 +1,874 @@ +/* + * This file contains the entry point for the application. + * The name of this entry point is compiler dependent. + * It jumps to the BSP which is responsible for performing + * all initialization. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * Based on the `gen68360' board support package, and covered by the + * original distribution terms. + * + * Geoffroy Montel + * France Telecom - CNET/DSM/TAM/CAT + * 4, rue du Clos Courtel + * 35512 CESSON-SEVIGNE + * FRANCE + * + * e-mail: g_montel@yahoo.com + * + * $Id$ + */ + +#include "asm.h" +#include + +#define _OLD_ASTECC 1 /* old addresses for AST68340 only, undefine for AST68349 */ + +BEGIN_CODE + /* + * Step 1: Decide on Reset Stack Pointer and Initial Program Counter + */ +Entry: + .long SYM(m340)+1024 | 0: Initial SSP + .long start | 1: Initial PC + .long SYM(_uhoh) | 2: Bus error + .long SYM(_uhoh) | 3: Address error + .long SYM(_uhoh) | 4: Illegal instruction + .long SYM(_uhoh) | 5: Zero division + .long SYM(_uhoh) | 6: CHK, CHK2 instruction + .long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions + .long SYM(_uhoh) | 8: Privilege violation + .long SYM(_uhoh) | 9: Trace + .long SYM(_uhoh) | 10: Line 1010 emulator + .long SYM(_uhoh) | 11: Line 1111 emulator + .long SYM(_uhoh) | 12: Hardware breakpoint + .long SYM(_uhoh) | 13: Reserved for coprocessor violation + .long SYM(_uhoh) | 14: Format error + .long SYM(_uhoh) | 15: Uninitialized interrupt + .long SYM(_uhoh) | 16: Unassigned, reserved + .long SYM(_uhoh) | 17: + .long SYM(_uhoh) | 18: + .long SYM(_uhoh) | 19: + .long SYM(_uhoh) | 20: + .long SYM(_uhoh) | 21: + .long SYM(_uhoh) | 22: + .long SYM(_uhoh) | 23: + .long SYM(_spuriousInterrupt) | 24: Spurious interrupt + .long SYM(_uhoh) | 25: Level 1 interrupt autovector + .long SYM(_uhoh) | 26: Level 2 interrupt autovector + .long SYM(_uhoh) | 27: Level 3 interrupt autovector + .long SYM(_uhoh) | 28: Level 4 interrupt autovector + .long SYM(_uhoh) | 29: Level 5 interrupt autovector + .long SYM(_uhoh) | 30: Level 6 interrupt autovector + .long SYM(_uhoh) | 31: Level 7 interrupt autovector + .long SYM(_uhoh) | 32: Trap instruction (0-15) + .long SYM(_uhoh) | 33: + .long SYM(_uhoh) | 34: + .long SYM(_uhoh) | 35: + .long SYM(_uhoh) | 36: + .long SYM(_uhoh) | 37: + .long SYM(_uhoh) | 38: + .long SYM(_uhoh) | 39: + .long SYM(_uhoh) | 40: + .long SYM(_uhoh) | 41: + .long SYM(_uhoh) | 42: + .long SYM(_uhoh) | 43: + .long SYM(_uhoh) | 44: + .long SYM(_uhoh) | 45: + .long SYM(_uhoh) | 46: + .long SYM(_uhoh) | 47: + .long SYM(_uhoh) | 48: Reserved for coprocessor + .long SYM(_uhoh) | 49: + .long SYM(_uhoh) | 50: + .long SYM(_uhoh) | 51: + .long SYM(_uhoh) | 52: + .long SYM(_uhoh) | 53: + .long SYM(_uhoh) | 54: + .long SYM(_uhoh) | 55: + .long SYM(_uhoh) | 56: + .long SYM(_uhoh) | 57: + .long SYM(_uhoh) | 58: + .long SYM(_uhoh) | 59: Unassigned, reserved + .long SYM(_uhoh) | 60: + .long SYM(_uhoh) | 61: + .long SYM(_uhoh) | 62: + .long SYM(_uhoh) | 63: + .long SYM(_uhoh) | 64: User defined vectors (192) + .long SYM(_uhoh) | 65: + .long SYM(_uhoh) | 66: + .long SYM(_uhoh) | 67: + .long SYM(_uhoh) | 68: + .long SYM(_uhoh) | 69: + .long SYM(_uhoh) | 70: + .long SYM(_uhoh) | 71: + .long SYM(_uhoh) | 72: + .long SYM(_uhoh) | 73: + .long SYM(_uhoh) | 74: + .long SYM(_uhoh) | 75: + .long SYM(_uhoh) | 76: + .long SYM(_uhoh) | 77: + .long SYM(_uhoh) | 78: + .long SYM(_uhoh) | 79: + .long SYM(_uhoh) | 80: + .long SYM(_uhoh) | 81: + .long SYM(_uhoh) | 82: + .long SYM(_uhoh) | 83: + .long SYM(_uhoh) | 84: + .long SYM(_uhoh) | 85: + .long SYM(_uhoh) | 86: + .long SYM(_uhoh) | 87: + .long SYM(_uhoh) | 88: + .long SYM(_uhoh) | 89: + .long SYM(_uhoh) | 90: + .long SYM(_uhoh) | 91: + .long SYM(_uhoh) | 92: + .long SYM(_uhoh) | 93: + .long SYM(_uhoh) | 94: + .long SYM(_uhoh) | 95: + .long SYM(_uhoh) | 96: + .long SYM(_uhoh) | 97: + .long SYM(_uhoh) | 98: + .long SYM(_uhoh) | 99: + .long SYM(_uhoh) | 100: + .long SYM(_uhoh) | 101: + .long SYM(_uhoh) | 102: + .long SYM(_uhoh) | 103: + .long SYM(_uhoh) | 104: + .long SYM(_uhoh) | 105: + .long SYM(_uhoh) | 106: + .long SYM(_uhoh) | 107: + .long SYM(_uhoh) | 108: + .long SYM(_uhoh) | 109: + .long SYM(_uhoh) | 110: + .long SYM(_uhoh) | 111: + .long SYM(_uhoh) | 112: + .long SYM(_uhoh) | 113: + .long SYM(_uhoh) | 114: + .long SYM(_uhoh) | 115: + .long SYM(_uhoh) | 116: + .long SYM(_uhoh) | 117: + .long SYM(_uhoh) | 118: + .long SYM(_uhoh) | 119: + .long SYM(_uhoh) | 120: + .long SYM(_uhoh) | 121: + .long SYM(_uhoh) | 122: + .long SYM(_uhoh) | 123: + .long SYM(_uhoh) | 124: + .long SYM(_uhoh) | 125: + .long SYM(_uhoh) | 126: + .long SYM(_uhoh) | 127: + .long SYM(_uhoh) | 128: + .long SYM(_uhoh) | 129: + .long SYM(_uhoh) | 130: + .long SYM(_uhoh) | 131: + .long SYM(_uhoh) | 132: + .long SYM(_uhoh) | 133: + .long SYM(_uhoh) | 134: + .long SYM(_uhoh) | 135: + .long SYM(_uhoh) | 136: + .long SYM(_uhoh) | 137: + .long SYM(_uhoh) | 138: + .long SYM(_uhoh) | 139: + .long SYM(_uhoh) | 140: + .long SYM(_uhoh) | 141: + .long SYM(_uhoh) | 142: + .long SYM(_uhoh) | 143: + .long SYM(_uhoh) | 144: + .long SYM(_uhoh) | 145: + .long SYM(_uhoh) | 146: + .long SYM(_uhoh) | 147: + .long SYM(_uhoh) | 148: + .long SYM(_uhoh) | 149: + .long SYM(_uhoh) | 150: + .long SYM(_uhoh) | 151: + .long SYM(_uhoh) | 152: + .long SYM(_uhoh) | 153: + .long SYM(_uhoh) | 154: + .long SYM(_uhoh) | 155: + .long SYM(_uhoh) | 156: + .long SYM(_uhoh) | 157: + .long SYM(_uhoh) | 158: + .long SYM(_uhoh) | 159: + .long SYM(_uhoh) | 160: + .long SYM(_uhoh) | 161: + .long SYM(_uhoh) | 162: + .long SYM(_uhoh) | 163: + .long SYM(_uhoh) | 164: + .long SYM(_uhoh) | 165: + .long SYM(_uhoh) | 166: + .long SYM(_uhoh) | 167: + .long SYM(_uhoh) | 168: + .long SYM(_uhoh) | 169: + .long SYM(_uhoh) | 170: + .long SYM(_uhoh) | 171: + .long SYM(_uhoh) | 172: + .long SYM(_uhoh) | 173: + .long SYM(_uhoh) | 174: + .long SYM(_uhoh) | 175: + .long SYM(_uhoh) | 176: + .long SYM(_uhoh) | 177: + .long SYM(_uhoh) | 178: + .long SYM(_uhoh) | 179: + .long SYM(_uhoh) | 180: + .long SYM(_uhoh) | 181: + .long SYM(_uhoh) | 182: + .long SYM(_uhoh) | 183: + .long SYM(_uhoh) | 184: + .long SYM(_uhoh) | 185: + .long SYM(_uhoh) | 186: + .long SYM(_uhoh) | 187: + .long SYM(_uhoh) | 188: + .long SYM(_uhoh) | 189: + .long SYM(_uhoh) | 190: + .long SYM(_uhoh) | 191: + .long SYM(_uhoh) | 192: + .long SYM(_uhoh) | 193: + .long SYM(_uhoh) | 194: + .long SYM(_uhoh) | 195: + .long SYM(_uhoh) | 196: + .long SYM(_uhoh) | 197: + .long SYM(_uhoh) | 198: + .long SYM(_uhoh) | 199: + .long SYM(_uhoh) | 200: + .long SYM(_uhoh) | 201: + .long SYM(_uhoh) | 202: + .long SYM(_uhoh) | 203: + .long SYM(_uhoh) | 204: + .long SYM(_uhoh) | 205: + .long SYM(_uhoh) | 206: + .long SYM(_uhoh) | 207: + .long SYM(_uhoh) | 208: + .long SYM(_uhoh) | 209: + .long SYM(_uhoh) | 210: + .long SYM(_uhoh) | 211: + .long SYM(_uhoh) | 212: + .long SYM(_uhoh) | 213: + .long SYM(_uhoh) | 214: + .long SYM(_uhoh) | 215: + .long SYM(_uhoh) | 216: + .long SYM(_uhoh) | 217: + .long SYM(_uhoh) | 218: + .long SYM(_uhoh) | 219: + .long SYM(_uhoh) | 220: + .long SYM(_uhoh) | 221: + .long SYM(_uhoh) | 222: + .long SYM(_uhoh) | 223: + .long SYM(_uhoh) | 224: + .long SYM(_uhoh) | 225: + .long SYM(_uhoh) | 226: + .long SYM(_uhoh) | 227: + .long SYM(_uhoh) | 228: + .long SYM(_uhoh) | 229: + .long SYM(_uhoh) | 230: + .long SYM(_uhoh) | 231: + .long SYM(_uhoh) | 232: + .long SYM(_uhoh) | 233: + .long SYM(_uhoh) | 234: + .long SYM(_uhoh) | 235: + .long SYM(_uhoh) | 236: + .long SYM(_uhoh) | 237: + .long SYM(_uhoh) | 238: + .long SYM(_uhoh) | 239: + .long SYM(_uhoh) | 240: + .long SYM(_uhoh) | 241: + .long SYM(_uhoh) | 242: + .long SYM(_uhoh) | 243: + .long SYM(_uhoh) | 244: + .long SYM(_uhoh) | 245: + .long SYM(_uhoh) | 246: + .long SYM(_uhoh) | 247: + .long SYM(_uhoh) | 248: + .long SYM(_uhoh) | 249: + .long SYM(_uhoh) | 250: + .long SYM(_uhoh) | 251: + .long SYM(_uhoh) | 252: + .long SYM(_uhoh) | 253: + .long SYM(_uhoh) | 254: + .long SYM(_uhoh) | 255: + +/* + * Default trap handler + * With an oscilloscope you can see AS* stop + */ + PUBLIC (_uhoh) +SYM(_uhoh): nop | Leave spot for breakpoint +/* stop #0x2700 | Stop with interrupts disabled */ + move.w #0x2700,sr + move.w (a7),_boot_panic_registers+4 | SR + move.l 2(a7),_boot_panic_registers | PC + move.w 6(a7),_boot_panic_registers+6 | format & vector + movem.l d0-d7/a0-a7, _boot_panic_registers+8 + movec sfc, d0 + movem.l d0, _boot_panic_registers+72 + movec dfc, d0 + movem.l d0, _boot_panic_registers+76 + movec vbr, d0 + movem.l d0, _boot_panic_registers+80 + jmp SYM(_dbug_dumpanic) + bra.s _crt0_cold_start + +/* + * Log, but otherwise ignore, spurious interrupts + */ + PUBLIC (_spuriousInterrupt) +SYM(_spuriousInterrupt): + addql #1,SYM(_M68kSpuriousInterruptCount) + rte + +/* + * Place the low-order 3 octets of the board's ethernet address at + * a `well-known' fixed location relative to the startup location. + */ + .align 2 + .word 0 | Padding +ethernet_address_buffer: + .word 0x08F3 | Default address + .word 0xDEAD + .word 0xCAFE + +BEGIN_DATA + +/* equates */ + +.equ _CPU340, 0x0 +.equ _CPU349, 0x31 + +#ifdef _OLD_ASTECC /* old addresses for AST68340 only */ +.equ _EPLD_CS_BASE, 0x1 +.equ _PROM_Start, 0x01000000 /* CS0 */ +.equ _FLEX_Start, 0x08000000 /* CS2 */ +.equ _I2C_Start, 0x0c000000 /* CS3 */ + +.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */ +.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */ + +.equ _ExtRam_Start, 0x10000000 /* SRAM */ +.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */ + +.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */ +.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */ + +#else /* new addresses for AST68349 and 68340 */ + +.equ _EPLD_CS_BASE, 0x5 +.equ _PROM_Start, 0x50000000 /* CS0 */ +.equ _FLEX_Start, 0x08000000 /* CS2 */ +.equ _I2C_Start, 0x0c000000 /* CS3 */ + +.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */ +.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */ + +.equ _ExtRam_Start, 0x80000000 /* DRAM */ +.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */ + +.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */ +.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */ +#endif + +.equ _SPEED349, 0xD680 /* 24 Mhz */ +.equ _SPEED340, 0xD700 /* 25 Mhz */ +/* .equ _SPEED340, 0xCE00 16 Mhz */ + +#define crt0_boot_type d0 /* cold/warm start (must be D0) */ +#define crt0_temp d1 +#define crt0_cpu_type d2 +#define crt0_csswitch d3 +#define crt0_buswidth d4 +#define crt0_pdcs d5 +#define crt0_spare6 d6 +#define crt0_spare7 d7 +#define crt0_sim_base a0 +#define crt0_glue a1 +#define crt0_dram a2 +#define crt0_ptr3 a3 +#define crt0_ptr4 a4 +#define crt0_ptr5 a5 +#define crt0_ptr6 a6 + +/* -- PDCS buffer equates -- */ +.equ pdcs_mask, 0x1F /* DRAM configuration */ +.equ pdcs_sw12, 7 /* switch 12 */ +.equ pdcs_sw11, 6 /* switch 11 */ +.equ pdcs_sw14, 5 /* switch 14 */ + +.equ bit_cache, pdcs_sw12 /* enable cache if on */ +.equ bit_meminit, pdcs_sw11 /* init memory if on */ + +/* -- Initialization stack and vars -- */ + +_AsteccBusWidth: ds.b 1 +_AsteccCsSwitch: ds.b 1 +_AsteccCpuName: ds.l 1 + +.align 4 + +_crt0_init_stack: + ds.l 500 +_crt0_init_stktop: + +/* -- Initialization code -- */ +BEGIN_CODE + +.align 4 + dc.l _crt0_init_stktop /* reset SP */ + dc.l _crt0_cold_start /* reset PC */ + dc.l _crt0_warm_start + + .ascii "BOOT XHM68K/Spectra for ASTECC 68349 and 68340 boards" + dc.w 0 +.align 4 + +.globl start +start: + +_crt0_cold_start: + moveq.l #0,crt0_boot_type | signal cold reset + bra.s _crt0_common_start + +_crt0_warm_start: + moveq.l #1,crt0_boot_type | signal warm reset + +_crt0_common_start: + move.w #0x2700,sr | disable interrupts and switch to interrupt mode + movea.l #_crt0_init_stktop,sp | set up initialization stack + + move.l #Entry,crt0_temp | VBR initialization + movec.l crt0_temp,vbr | + moveq.l #0x07,crt0_temp + movec.l crt0_temp,dfc | prepare access in CPU space + move.l #(BASE_SIM+0x111),crt0_temp | mask CPU, RESERVED USER SPACES + moves.l crt0_temp,BASE_REG | base initialization (must be MOVES, PCC-130795) + + movea.l #BASE_SIM,crt0_sim_base + + /* -- disable Bus Monitor -- */ + move.b #0,SIM_SYPCR(crt0_sim_base) | system protection control register + + /* -- enable A31-A24 -- */ + clr.b SIM_PPRA1(crt0_sim_base) + + /* -- show cycles, user acces to SIM, 4 /CS & 4 /IT -- */ + move.w #0x427F,SIM_MCR(crt0_sim_base) + + /* -- enable /IRQ3, 5, 6, 7 -- */ + move.b #0xE8,SIM_PPRB(crt0_sim_base) + + /* -- enable autovector on /IRQ7 -- */ + move.b #0x80,SIM_AVR(crt0_sim_base) + + /* -- test CPU type -- */ + cmp.b #_CPU349,SIM_IDR(crt0_sim_base) + bne cpu_is_68340 + +/*-------------------------------------------------------------------------------------------*/ +cpu_is_68349: + + /* -- set cpu clock -- */ + move.w #_SPEED349,SIM_SYNCR(crt0_sim_base) | clock + +sync_wait349: + btst.b #3,(SIM_SYNCR+1)(crt0_sim_base) + beq sync_wait349 + + /* to allow access to the EPLD internal registers, it is necessary + to disable the global chip-select /CS0 (which decodes every external + cycles). To do that, we initialize the 68349 internal RAM, + copy a part of the initialization code in it, and jump there. + from that moment, /CS0 is not used, therefore it can be initialized + with its default value. Its width may be incorrect, but it will be + adjusted later. The goal is to avoid any conflict with + the accesses to the EPLD registers. + When this is done, we read the RESET parameters (boot prom width + and chip-select switch) and proceed with the initialization + when all is done, we jump back to the boot prom now + decoded with a properly configured /CS0 */ + + /*-------------------------------------*/ + /* -- configure internal SRAM banks -- */ + + move.l #0x00000000,QDMM_MCR(crt0_sim_base) + move.l #_FastRam_Start+0x0005,QDMM_QBAR0(crt0_sim_base) + move.l #_FastRam_Start+0x0405,QDMM_QBAR1(crt0_sim_base) + move.l #_FastRam_Start+0x0805,QDMM_QBAR2(crt0_sim_base) + move.l #_FastRam_Start+0x0c05,QDMM_QBAR3(crt0_sim_base) + + /*--------------------------------------------------------*/ + /* -- copy to address of the 68349 initialization code -- */ + + lea.l _copy_start(%pc),crt0_ptr3 + lea.l _copy_end(%pc),crt0_ptr4 + move.l crt0_ptr4,crt0_temp + sub.l crt0_ptr3,crt0_temp + add.l #3,crt0_temp | adjust to next long word + lsr.l #2,crt0_temp + + move.l #_FastRam_Start,crt0_ptr4 +_copy_loop: + move.l (crt0_ptr3)+,(crt0_ptr4)+ + subq.l #1,crt0_temp + bne.s _copy_loop + bra.l _FastRam_Start | jump to code in internal RAM + + /*------------------------------------*/ + /* -- start of initialization code -- */ + +_copy_start: + bra.l _begin_68349_init + + /*----------------------------------------------------------*/ + /* Astecc 68349 board : chip-select initialization values */ + +_table_csepld: + dc.b (_EPLD_CS_BASE&0x0F)+0x80 | 16 bits, 0ws + dc.b 0x80 | 16 bits, 0 ws + dc.b 0x90 | 16 bits, ext /dsack + dc.b 0x90 | 16 bits, ext /dsack + +_table_cs349: + dc.l 0x003FFFF4 | Mask CS0 (4Mbytes PROM, 32bits, 1WS) + dc.l (_PROM_Start&0xFFFFFF00)+0x00000003 | Base CS0 + dc.l 0x003FFFF1 | MASK CS1 (4Mbytes RAM, 16bits, 0WS) + dc.l (_BCCram_Start&0xFFFFFF00)+0x00000003 | Base CS1 + dc.l 0x000000FF | MASK CS2 (FLEX, ext DTACK, 256 bytes) + dc.l (_FLEX_Start&0xFFFFFF00)+0x00000003 | Base CS2 + dc.l 0x000000FF | Mask CS3 (I2C, ext DTACK, 256 bytes) + dc.l (_I2C_Start&0xFFFFFF00)+0x00000003 | Base CS3 + + /*-------------------------------------------------*/ +_begin_68349_init: + + /*-------------------------------------------------*/ + /* 68349 chip select initialization + + at this stage, the width of /CS0 may be incorrect + it will be corrected later + */ + +_cs68349_init: + lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 + lea.l _table_cs349(%pc),crt0_ptr3 + + moveq.l #0x07,crt0_temp +_cs349_init2: + move.l (crt0_ptr3)+,(crt0_ptr4)+ + dbra crt0_temp,_cs349_init2 + + /*-----------------------------------------------*/ + /* -- prepare access to the internal registers --*/ + moveq.l #EPLD_SPACE,crt0_temp + movec.l crt0_temp,dfc + movec.l crt0_temp,sfc + move.l #GLUE_EPLD,crt0_glue + move.l #DRAM_EPLD,crt0_dram + + /*-------------------------------------------*/ + /* EPLD generated /CS[3..0] must be disabled */ + +_csepld_clear: + move.l crt0_glue,crt0_ptr4 + move.w #3,crt0_spare6 + clr.b crt0_temp + +_csepld_clear1: + moves.b crt0_temp,(crt0_ptr4)+ + dbra crt0_spare6,_csepld_clear1 + + /*---------------------------------------------------------*/ + /* -- get width of boot PROM, and active chip-select set --*/ + moves.b REG_BUSWIDTH(crt0_dram),crt0_csswitch + move.b crt0_csswitch,crt0_buswidth + + /* state of CS_SWITCH : sel == 0 => CPU chip_selects (/CS[3..0]) + : sel == 1 => EPLD chip_selects (/CS[3..0]) */ + and.b #1,crt0_csswitch + + /* bus width of /CS0 during reset bw[1..0] : 0 1 2 3 + bus width : 32 16 8 ext./dsackx */ + rol.b #2,crt0_buswidth + and.b #3,crt0_buswidth + + /*----------------------------------------------------*/ + /* -- configure chip select 0 with boot prom width -- */ + lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 + lea.l _table_cs349(%pc),crt0_ptr3 + move.l (crt0_ptr3)+,crt0_temp + and.b #0xFC,crt0_temp | clear PS0 & PS1 + or.b crt0_buswidth,crt0_temp | set boot PROM bus width + move.l crt0_temp,(crt0_ptr4)+ + + /*------------------------*/ + /* -- read PDCS buffer -- */ + moves.b REG_PDCS(crt0_glue),crt0_pdcs +/* move.b #0x3F,crt0_pdcs pour test */ + + + /*---------------------------------------*/ + /* -- EPLD chip-select initialization -- */ + /*---------------------------------------*/ + btst.b #0,crt0_csswitch + beq _cs_init_end + + /*--------------------------------------------*/ + /* 68349 generated /CS[3..0] must be disabled */ + lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 + lea.l _table_cs349(%pc),crt0_ptr3 + moveq.l #0x03,crt0_temp +_cs349_clear: + move.l (crt0_ptr3)+,(crt0_ptr4)+ + move.l (crt0_ptr3)+,crt0_spare6 + and.b #0xFE,crt0_spare6 | disable chip-select + move.l crt0_spare6,(crt0_ptr4)+ + dbra crt0_temp,_cs349_clear + + /*---------------------------------------------*/ + /* EPLD generated /CS[3..0] must be configured */ +_csepld_init: + move.l crt0_glue,crt0_ptr4 + lea.l _table_csepld(%pc),crt0_ptr3 + + move.b (crt0_ptr3)+,crt0_temp + or.b #0x20,crt0_temp | default width is 32 bits + tst.b crt0_buswidth | is boot PROM bus width 32 bits ? + beq _csepld1 | if not + and.b #0xDF,crt0_temp | set width to 16 bits +_csepld1: + moves.b crt0_temp,(crt0_ptr4)+ + + moveq.l #0x02,crt0_spare6 +_csepld2: + move.b (crt0_ptr3)+,crt0_temp + moves.b crt0_temp,(crt0_ptr4)+ + dbra crt0_spare6,_csepld2 + +_cs_init_end: + + /*--------------------------------------*/ + /* -- DRAM controller initialization -- */ +_dram_init: + move.w #15,crt0_temp + move.l #_ExtRam_Start,crt0_ptr3 + +_dram_init1: + clr.l (crt0_ptr3)+ | must access DRAM + dbra crt0_temp,_dram_init1 | prior to init refresh + +_dram_init2: + move.b #3,crt0_temp + moves.b crt0_temp,REG_WS(crt0_dram) | set 3 wait-states + + move.b #0x81,crt0_temp + moves.b crt0_temp,REG_REFRESH(crt0_dram) | refresh every 10µs + + move.b #0,crt0_temp + moves.b crt0_temp,REG_CONFIG(crt0_dram) | default size = 4Mbytes + + /*-----------------------*/ + /* -- configure cache -- */ +_init_cache: + move.l #0x000001E0,CACHE_MCR(crt0_sim_base) + btst.b #bit_cache,crt0_pdcs + bne _init_cache_end + or.l #0x00000001,CACHE_MCR(crt0_sim_base) + +_init_cache_end: + + /*-----------------------------*/ + /* -- timers initialization -- */ + + clr.b crt0_temp + moves.b crt0_temp,REG_TIMER1(crt0_glue) | disable timer 1 + moves.b crt0_temp,REG_TIMER2(crt0_glue) | disable timer 2 + + /*--------------------------*/ + /* -- I2C initialization -- */ + move.b #3,crt0_temp + moves.b crt0_temp,REG_I2C(crt0_glue) | tri-states I2C ports + + /*-----------------------------------------*/ + /* -- baudrate generator initialization -- */ + move.b #2,crt0_temp + moves.b crt0_temp,REG_BAUDRATE(crt0_glue) | baudrate = 38400 + + /*-------------------------------*/ + /* -- IO port initialization -- */ + clr.b crt0_temp + moves.b crt0_temp,REG_IO(crt0_glue) | set port as input + + /* -- */ + + move.l #68349,crt0_cpu_type + + + /* -- jump back to PROM -- */ + + jmp.l (_fill_test) | must be absolute long + +_copy_end: + +/*------------------------------------------------- + initialization code for the 68340 board + -------------------------------------------------*/ + + /* Astecc 68340 board : chip-select initialization values */ +_table_cs340: + dc.l 0x003FFFF0 /* Mask CS0 (4Mbytes PROM, 32bits, 0WS) */ + dc.l ((_PROM_Start&0xFFFFFF00)+0x00000003) /* Base CS0 */ + dc.l 0x0000FFFD /* MASK CS1 (RAMBCC340, 0WS, FTE) */ + dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000003) /* Base CS1 */ + dc.l 0x000000FF /* MASK CS2 (FLEX, ext DTACK, 256 bytes) */ + dc.l ((_FLEX_Start&0xFFFFFF00)+0x00000003) /* Base CS2 */ + dc.l 0x000000FF /* Mask CS3 (I2C, ext DTACK, 256 bytes) */ + dc.l ((_I2C_Start&0xFFFFFF00)+0x00000003) /* Base CS3 */ + +cpu_is_68340: + + /* -- set cpu clock -- */ + move.w #_SPEED340,SIM_SYNCR(crt0_sim_base) | clock +sync_wait340: + btst.b #3,(SIM_SYNCR+1)(crt0_sim_base) + beq sync_wait340 + + /* -- chip select initialization -- */ + lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 + lea.l _table_cs340(%pc),crt0_ptr3 + moveq.l #0x07,crt0_temp +_b_cs340: + move.l (crt0_ptr3)+,crt0_ptr5 + move.l crt0_ptr5,(crt0_ptr4)+ | pour test + dbra crt0_temp,_b_cs340 + + move.l #68340,crt0_cpu_type + move.b #0,crt0_csswitch | CPU + move.b #1,crt0_buswidth | 16 bits + + + /*------------------------------------------------- + fill RAM if COLDSTART + -------------------------------------------------*/ +_fill_test: + + tst.l crt0_boot_type + bne _dont_fill + + cmp.b #_CPU349,SIM_IDR(crt0_sim_base) + bne _fill + btst.b #bit_meminit,crt0_pdcs + bne _dont_fill + + /* fill main memory */ +_fill: + move.l #_crt0_init_stack,crt0_ptr3 | skip Astecc vars + move.l #_ExtRam_Start,crt0_temp + sub.l #_crt0_init_stack,crt0_temp + add.l #_ExtRam_Size,crt0_temp | get size + lsr.l #2,crt0_temp | ajust for long word +_fill_loop: + clr.l (crt0_ptr3)+ + subq.l #1,crt0_temp + bne _fill_loop + + cmp.b #_CPU349,SIM_IDR(crt0_sim_base) + bne _fill_bccram + + /* fill QDMM memory */ + movea.l #_FastRam_Start,crt0_ptr3 | get start + move.l #_FastRam_Size,crt0_temp | get size + lsr.l #2,crt0_temp | ajust for long word + +_QDMMfill_loop: + clr.l (crt0_ptr3)+ + subq.l #1,crt0_temp + bne _QDMMfill_loop + bra _dont_fill + + /* fill BCC memory */ +_fill_bccram: + movea.l #_BCCram_Start,crt0_ptr3 | get start + move.l #_BCCram_Size,crt0_temp | get size + lsr.l #2,crt0_temp | ajust for long word +_BCCfill_loop: + clr.l (crt0_ptr3)+ + subq.l #1,crt0_temp + bne _BCCfill_loop + + *-------------------------------------------------*/ +_dont_fill: + move.b crt0_csswitch,_AsteccCsSwitch + move.b crt0_buswidth,_AsteccBusWidth + move.l crt0_cpu_type,_AsteccCpuName + + jmp SYM(_Init68340) | Start C code (which never returns) + +/* + * Copy DATA segment, clear BSS segment, set up real stack, + * initialize heap, start C program. + * Assume that DATA and BSS sizes are multiples of 4. + */ + PUBLIC (_CopyDataClearBSSAndStart) +SYM(_CopyDataClearBSSAndStart): + lea copy_start,a0 | Get start of DATA in RAM + lea SYM(etext),a2 | Get start of DATA in ROM + cmpl a0,a2 | Are they the same? + beq.s NOCOPY | Yes, no copy necessary + lea copy_end,a1 | Get end of DATA in RAM + bra.s COPYLOOPTEST | Branch into copy loop +COPYLOOP: + movel a2@+,a0@+ | Copy word from ROM to RAM +COPYLOOPTEST: + cmpl a1,a0 | Done? + bcs.s COPYLOOP | No, skip +NOCOPY: + + lea clear_start,a0 | Get start of BSS + lea clear_end,a1 | Get end of BSS + clrl d0 | Value to set + bra.s ZEROLOOPTEST | Branch into clear loop +ZEROLOOP: + movel d0,a0@+ | Clear a word +ZEROLOOPTEST: + cmpl a1,a0 | Done? + bcs.s ZEROLOOP | No, skip + + movel #stack_init,a7 | set master stack pointer + movel d0,a7@- | environp + movel d0,a7@- | argv + movel d0,a7@- | argc + jsr SYM(boot_card) | Call C main + + PUBLIC (_mainDone) +SYM(_mainDone): + nop | Leave spot for breakpoint + movew #1,a7 | Force a double bus error + movel d0,a7@- | This should cause a RESET +/* stop #0x2700 | Stop with interrupts disabled */ + move.w #0x2700,sr + bra.s SYM(_mainDone) | Stuck forever + + .align 2 + PUBLIC (_HeapSize) +SYM (_HeapSize): + .long HeapSize + PUBLIC (_StackSize) +SYM (_StackSize): + .long StackSize +END_CODE + +BEGIN_DATA_DCL + .align 2 + PUBLIC (environ) +SYM (environ): + .long 0 + PUBLIC (_M68kSpuriousInterruptCount) +SYM (_M68kSpuriousInterruptCount): + .long 0 +END_DATA_DCL + +END + diff --git a/c/src/lib/libbsp/m68k/gen68340/start/start340.s b/c/src/lib/libbsp/m68k/gen68340/start/start340.s deleted file mode 100644 index 58ea0c92d0..0000000000 --- a/c/src/lib/libbsp/m68k/gen68340/start/start340.s +++ /dev/null @@ -1,874 +0,0 @@ -/* - * This file contains the entry point for the application. - * The name of this entry point is compiler dependent. - * It jumps to the BSP which is responsible for performing - * all initialization. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may in - * the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * Based on the `gen68360' board support package, and covered by the - * original distribution terms. - * - * Geoffroy Montel - * France Telecom - CNET/DSM/TAM/CAT - * 4, rue du Clos Courtel - * 35512 CESSON-SEVIGNE - * FRANCE - * - * e-mail: g_montel@yahoo.com - * - * $Id$ - */ - -#include "asm.h" -#include - -#define _OLD_ASTECC 1 /* old addresses for AST68340 only, undefine for AST68349 */ - -BEGIN_CODE - /* - * Step 1: Decide on Reset Stack Pointer and Initial Program Counter - */ -Entry: - .long SYM(m340)+1024 | 0: Initial SSP - .long start | 1: Initial PC - .long SYM(_uhoh) | 2: Bus error - .long SYM(_uhoh) | 3: Address error - .long SYM(_uhoh) | 4: Illegal instruction - .long SYM(_uhoh) | 5: Zero division - .long SYM(_uhoh) | 6: CHK, CHK2 instruction - .long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions - .long SYM(_uhoh) | 8: Privilege violation - .long SYM(_uhoh) | 9: Trace - .long SYM(_uhoh) | 10: Line 1010 emulator - .long SYM(_uhoh) | 11: Line 1111 emulator - .long SYM(_uhoh) | 12: Hardware breakpoint - .long SYM(_uhoh) | 13: Reserved for coprocessor violation - .long SYM(_uhoh) | 14: Format error - .long SYM(_uhoh) | 15: Uninitialized interrupt - .long SYM(_uhoh) | 16: Unassigned, reserved - .long SYM(_uhoh) | 17: - .long SYM(_uhoh) | 18: - .long SYM(_uhoh) | 19: - .long SYM(_uhoh) | 20: - .long SYM(_uhoh) | 21: - .long SYM(_uhoh) | 22: - .long SYM(_uhoh) | 23: - .long SYM(_spuriousInterrupt) | 24: Spurious interrupt - .long SYM(_uhoh) | 25: Level 1 interrupt autovector - .long SYM(_uhoh) | 26: Level 2 interrupt autovector - .long SYM(_uhoh) | 27: Level 3 interrupt autovector - .long SYM(_uhoh) | 28: Level 4 interrupt autovector - .long SYM(_uhoh) | 29: Level 5 interrupt autovector - .long SYM(_uhoh) | 30: Level 6 interrupt autovector - .long SYM(_uhoh) | 31: Level 7 interrupt autovector - .long SYM(_uhoh) | 32: Trap instruction (0-15) - .long SYM(_uhoh) | 33: - .long SYM(_uhoh) | 34: - .long SYM(_uhoh) | 35: - .long SYM(_uhoh) | 36: - .long SYM(_uhoh) | 37: - .long SYM(_uhoh) | 38: - .long SYM(_uhoh) | 39: - .long SYM(_uhoh) | 40: - .long SYM(_uhoh) | 41: - .long SYM(_uhoh) | 42: - .long SYM(_uhoh) | 43: - .long SYM(_uhoh) | 44: - .long SYM(_uhoh) | 45: - .long SYM(_uhoh) | 46: - .long SYM(_uhoh) | 47: - .long SYM(_uhoh) | 48: Reserved for coprocessor - .long SYM(_uhoh) | 49: - .long SYM(_uhoh) | 50: - .long SYM(_uhoh) | 51: - .long SYM(_uhoh) | 52: - .long SYM(_uhoh) | 53: - .long SYM(_uhoh) | 54: - .long SYM(_uhoh) | 55: - .long SYM(_uhoh) | 56: - .long SYM(_uhoh) | 57: - .long SYM(_uhoh) | 58: - .long SYM(_uhoh) | 59: Unassigned, reserved - .long SYM(_uhoh) | 60: - .long SYM(_uhoh) | 61: - .long SYM(_uhoh) | 62: - .long SYM(_uhoh) | 63: - .long SYM(_uhoh) | 64: User defined vectors (192) - .long SYM(_uhoh) | 65: - .long SYM(_uhoh) | 66: - .long SYM(_uhoh) | 67: - .long SYM(_uhoh) | 68: - .long SYM(_uhoh) | 69: - .long SYM(_uhoh) | 70: - .long SYM(_uhoh) | 71: - .long SYM(_uhoh) | 72: - .long SYM(_uhoh) | 73: - .long SYM(_uhoh) | 74: - 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152: - .long SYM(_uhoh) | 153: - .long SYM(_uhoh) | 154: - .long SYM(_uhoh) | 155: - .long SYM(_uhoh) | 156: - .long SYM(_uhoh) | 157: - .long SYM(_uhoh) | 158: - .long SYM(_uhoh) | 159: - .long SYM(_uhoh) | 160: - .long SYM(_uhoh) | 161: - .long SYM(_uhoh) | 162: - .long SYM(_uhoh) | 163: - .long SYM(_uhoh) | 164: - .long SYM(_uhoh) | 165: - .long SYM(_uhoh) | 166: - .long SYM(_uhoh) | 167: - .long SYM(_uhoh) | 168: - .long SYM(_uhoh) | 169: - .long SYM(_uhoh) | 170: - .long SYM(_uhoh) | 171: - .long SYM(_uhoh) | 172: - .long SYM(_uhoh) | 173: - .long SYM(_uhoh) | 174: - .long SYM(_uhoh) | 175: - .long SYM(_uhoh) | 176: - .long SYM(_uhoh) | 177: - .long SYM(_uhoh) | 178: - .long SYM(_uhoh) | 179: - .long SYM(_uhoh) | 180: - .long SYM(_uhoh) | 181: - .long SYM(_uhoh) | 182: - .long SYM(_uhoh) | 183: - .long SYM(_uhoh) | 184: - .long SYM(_uhoh) | 185: - .long SYM(_uhoh) | 186: - .long SYM(_uhoh) | 187: - .long SYM(_uhoh) | 188: - .long SYM(_uhoh) | 189: - .long SYM(_uhoh) | 190: - .long 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229: - .long SYM(_uhoh) | 230: - .long SYM(_uhoh) | 231: - .long SYM(_uhoh) | 232: - .long SYM(_uhoh) | 233: - .long SYM(_uhoh) | 234: - .long SYM(_uhoh) | 235: - .long SYM(_uhoh) | 236: - .long SYM(_uhoh) | 237: - .long SYM(_uhoh) | 238: - .long SYM(_uhoh) | 239: - .long SYM(_uhoh) | 240: - .long SYM(_uhoh) | 241: - .long SYM(_uhoh) | 242: - .long SYM(_uhoh) | 243: - .long SYM(_uhoh) | 244: - .long SYM(_uhoh) | 245: - .long SYM(_uhoh) | 246: - .long SYM(_uhoh) | 247: - .long SYM(_uhoh) | 248: - .long SYM(_uhoh) | 249: - .long SYM(_uhoh) | 250: - .long SYM(_uhoh) | 251: - .long SYM(_uhoh) | 252: - .long SYM(_uhoh) | 253: - .long SYM(_uhoh) | 254: - .long SYM(_uhoh) | 255: - -/* - * Default trap handler - * With an oscilloscope you can see AS* stop - */ - PUBLIC (_uhoh) -SYM(_uhoh): nop | Leave spot for breakpoint -/* stop #0x2700 | Stop with interrupts disabled */ - move.w #0x2700,sr - move.w (a7),_boot_panic_registers+4 | SR - move.l 2(a7),_boot_panic_registers | PC - move.w 6(a7),_boot_panic_registers+6 | format & vector - movem.l d0-d7/a0-a7, _boot_panic_registers+8 - movec sfc, d0 - movem.l d0, _boot_panic_registers+72 - movec dfc, d0 - movem.l d0, _boot_panic_registers+76 - movec vbr, d0 - movem.l d0, _boot_panic_registers+80 - jmp SYM(_dbug_dumpanic) - bra.s _crt0_cold_start - -/* - * Log, but otherwise ignore, spurious interrupts - */ - PUBLIC (_spuriousInterrupt) -SYM(_spuriousInterrupt): - addql #1,SYM(_M68kSpuriousInterruptCount) - rte - -/* - * Place the low-order 3 octets of the board's ethernet address at - * a `well-known' fixed location relative to the startup location. - */ - .align 2 - .word 0 | Padding -ethernet_address_buffer: - .word 0x08F3 | Default address - .word 0xDEAD - .word 0xCAFE - -BEGIN_DATA - -/* equates */ - -.equ _CPU340, 0x0 -.equ _CPU349, 0x31 - -#ifdef _OLD_ASTECC /* old addresses for AST68340 only */ -.equ _EPLD_CS_BASE, 0x1 -.equ _PROM_Start, 0x01000000 /* CS0 */ -.equ _FLEX_Start, 0x08000000 /* CS2 */ -.equ _I2C_Start, 0x0c000000 /* CS3 */ - -.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */ -.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */ - -.equ _ExtRam_Start, 0x10000000 /* SRAM */ -.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */ - -.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */ -.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */ - -#else /* new addresses for AST68349 and 68340 */ - -.equ _EPLD_CS_BASE, 0x5 -.equ _PROM_Start, 0x50000000 /* CS0 */ -.equ _FLEX_Start, 0x08000000 /* CS2 */ -.equ _I2C_Start, 0x0c000000 /* CS3 */ - -.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */ -.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */ - -.equ _ExtRam_Start, 0x80000000 /* DRAM */ -.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */ - -.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */ -.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */ -#endif - -.equ _SPEED349, 0xD680 /* 24 Mhz */ -.equ _SPEED340, 0xD700 /* 25 Mhz */ -/* .equ _SPEED340, 0xCE00 16 Mhz */ - -#define crt0_boot_type d0 /* cold/warm start (must be D0) */ -#define crt0_temp d1 -#define crt0_cpu_type d2 -#define crt0_csswitch d3 -#define crt0_buswidth d4 -#define crt0_pdcs d5 -#define crt0_spare6 d6 -#define crt0_spare7 d7 -#define crt0_sim_base a0 -#define crt0_glue a1 -#define crt0_dram a2 -#define crt0_ptr3 a3 -#define crt0_ptr4 a4 -#define crt0_ptr5 a5 -#define crt0_ptr6 a6 - -/* -- PDCS buffer equates -- */ -.equ pdcs_mask, 0x1F /* DRAM configuration */ -.equ pdcs_sw12, 7 /* switch 12 */ -.equ pdcs_sw11, 6 /* switch 11 */ -.equ pdcs_sw14, 5 /* switch 14 */ - -.equ bit_cache, pdcs_sw12 /* enable cache if on */ -.equ bit_meminit, pdcs_sw11 /* init memory if on */ - -/* -- Initialization stack and vars -- */ - -_AsteccBusWidth: ds.b 1 -_AsteccCsSwitch: ds.b 1 -_AsteccCpuName: ds.l 1 - -.align 4 - -_crt0_init_stack: - ds.l 500 -_crt0_init_stktop: - -/* -- Initialization code -- */ -BEGIN_CODE - -.align 4 - dc.l _crt0_init_stktop /* reset SP */ - dc.l _crt0_cold_start /* reset PC */ - dc.l _crt0_warm_start - - .ascii "BOOT XHM68K/Spectra for ASTECC 68349 and 68340 boards" - dc.w 0 -.align 4 - -.globl start -start: - -_crt0_cold_start: - moveq.l #0,crt0_boot_type | signal cold reset - bra.s _crt0_common_start - -_crt0_warm_start: - moveq.l #1,crt0_boot_type | signal warm reset - -_crt0_common_start: - move.w #0x2700,sr | disable interrupts and switch to interrupt mode - movea.l #_crt0_init_stktop,sp | set up initialization stack - - move.l #Entry,crt0_temp | VBR initialization - movec.l crt0_temp,vbr | - moveq.l #0x07,crt0_temp - movec.l crt0_temp,dfc | prepare access in CPU space - move.l #(BASE_SIM+0x111),crt0_temp | mask CPU, RESERVED USER SPACES - moves.l crt0_temp,BASE_REG | base initialization (must be MOVES, PCC-130795) - - movea.l #BASE_SIM,crt0_sim_base - - /* -- disable Bus Monitor -- */ - move.b #0,SIM_SYPCR(crt0_sim_base) | system protection control register - - /* -- enable A31-A24 -- */ - clr.b SIM_PPRA1(crt0_sim_base) - - /* -- show cycles, user acces to SIM, 4 /CS & 4 /IT -- */ - move.w #0x427F,SIM_MCR(crt0_sim_base) - - /* -- enable /IRQ3, 5, 6, 7 -- */ - move.b #0xE8,SIM_PPRB(crt0_sim_base) - - /* -- enable autovector on /IRQ7 -- */ - move.b #0x80,SIM_AVR(crt0_sim_base) - - /* -- test CPU type -- */ - cmp.b #_CPU349,SIM_IDR(crt0_sim_base) - bne cpu_is_68340 - -/*-------------------------------------------------------------------------------------------*/ -cpu_is_68349: - - /* -- set cpu clock -- */ - move.w #_SPEED349,SIM_SYNCR(crt0_sim_base) | clock - -sync_wait349: - btst.b #3,(SIM_SYNCR+1)(crt0_sim_base) - beq sync_wait349 - - /* to allow access to the EPLD internal registers, it is necessary - to disable the global chip-select /CS0 (which decodes every external - cycles). To do that, we initialize the 68349 internal RAM, - copy a part of the initialization code in it, and jump there. - from that moment, /CS0 is not used, therefore it can be initialized - with its default value. Its width may be incorrect, but it will be - adjusted later. The goal is to avoid any conflict with - the accesses to the EPLD registers. - When this is done, we read the RESET parameters (boot prom width - and chip-select switch) and proceed with the initialization - when all is done, we jump back to the boot prom now - decoded with a properly configured /CS0 */ - - /*-------------------------------------*/ - /* -- configure internal SRAM banks -- */ - - move.l #0x00000000,QDMM_MCR(crt0_sim_base) - move.l #_FastRam_Start+0x0005,QDMM_QBAR0(crt0_sim_base) - move.l #_FastRam_Start+0x0405,QDMM_QBAR1(crt0_sim_base) - move.l #_FastRam_Start+0x0805,QDMM_QBAR2(crt0_sim_base) - move.l #_FastRam_Start+0x0c05,QDMM_QBAR3(crt0_sim_base) - - /*--------------------------------------------------------*/ - /* -- copy to address of the 68349 initialization code -- */ - - lea.l _copy_start(%pc),crt0_ptr3 - lea.l _copy_end(%pc),crt0_ptr4 - move.l crt0_ptr4,crt0_temp - sub.l crt0_ptr3,crt0_temp - add.l #3,crt0_temp | adjust to next long word - lsr.l #2,crt0_temp - - move.l #_FastRam_Start,crt0_ptr4 -_copy_loop: - move.l (crt0_ptr3)+,(crt0_ptr4)+ - subq.l #1,crt0_temp - bne.s _copy_loop - bra.l _FastRam_Start | jump to code in internal RAM - - /*------------------------------------*/ - /* -- start of initialization code -- */ - -_copy_start: - bra.l _begin_68349_init - - /*----------------------------------------------------------*/ - /* Astecc 68349 board : chip-select initialization values */ - -_table_csepld: - dc.b (_EPLD_CS_BASE&0x0F)+0x80 | 16 bits, 0ws - dc.b 0x80 | 16 bits, 0 ws - dc.b 0x90 | 16 bits, ext /dsack - dc.b 0x90 | 16 bits, ext /dsack - -_table_cs349: - dc.l 0x003FFFF4 | Mask CS0 (4Mbytes PROM, 32bits, 1WS) - dc.l (_PROM_Start&0xFFFFFF00)+0x00000003 | Base CS0 - dc.l 0x003FFFF1 | MASK CS1 (4Mbytes RAM, 16bits, 0WS) - dc.l (_BCCram_Start&0xFFFFFF00)+0x00000003 | Base CS1 - dc.l 0x000000FF | MASK CS2 (FLEX, ext DTACK, 256 bytes) - dc.l (_FLEX_Start&0xFFFFFF00)+0x00000003 | Base CS2 - dc.l 0x000000FF | Mask CS3 (I2C, ext DTACK, 256 bytes) - dc.l (_I2C_Start&0xFFFFFF00)+0x00000003 | Base CS3 - - /*-------------------------------------------------*/ -_begin_68349_init: - - /*-------------------------------------------------*/ - /* 68349 chip select initialization - - at this stage, the width of /CS0 may be incorrect - it will be corrected later - */ - -_cs68349_init: - lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 - lea.l _table_cs349(%pc),crt0_ptr3 - - moveq.l #0x07,crt0_temp -_cs349_init2: - move.l (crt0_ptr3)+,(crt0_ptr4)+ - dbra crt0_temp,_cs349_init2 - - /*-----------------------------------------------*/ - /* -- prepare access to the internal registers --*/ - moveq.l #EPLD_SPACE,crt0_temp - movec.l crt0_temp,dfc - movec.l crt0_temp,sfc - move.l #GLUE_EPLD,crt0_glue - move.l #DRAM_EPLD,crt0_dram - - /*-------------------------------------------*/ - /* EPLD generated /CS[3..0] must be disabled */ - -_csepld_clear: - move.l crt0_glue,crt0_ptr4 - move.w #3,crt0_spare6 - clr.b crt0_temp - -_csepld_clear1: - moves.b crt0_temp,(crt0_ptr4)+ - dbra crt0_spare6,_csepld_clear1 - - /*---------------------------------------------------------*/ - /* -- get width of boot PROM, and active chip-select set --*/ - moves.b REG_BUSWIDTH(crt0_dram),crt0_csswitch - move.b crt0_csswitch,crt0_buswidth - - /* state of CS_SWITCH : sel == 0 => CPU chip_selects (/CS[3..0]) - : sel == 1 => EPLD chip_selects (/CS[3..0]) */ - and.b #1,crt0_csswitch - - /* bus width of /CS0 during reset bw[1..0] : 0 1 2 3 - bus width : 32 16 8 ext./dsackx */ - rol.b #2,crt0_buswidth - and.b #3,crt0_buswidth - - /*----------------------------------------------------*/ - /* -- configure chip select 0 with boot prom width -- */ - lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 - lea.l _table_cs349(%pc),crt0_ptr3 - move.l (crt0_ptr3)+,crt0_temp - and.b #0xFC,crt0_temp | clear PS0 & PS1 - or.b crt0_buswidth,crt0_temp | set boot PROM bus width - move.l crt0_temp,(crt0_ptr4)+ - - /*------------------------*/ - /* -- read PDCS buffer -- */ - moves.b REG_PDCS(crt0_glue),crt0_pdcs -/* move.b #0x3F,crt0_pdcs pour test */ - - - /*---------------------------------------*/ - /* -- EPLD chip-select initialization -- */ - /*---------------------------------------*/ - btst.b #0,crt0_csswitch - beq _cs_init_end - - /*--------------------------------------------*/ - /* 68349 generated /CS[3..0] must be disabled */ - lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 - lea.l _table_cs349(%pc),crt0_ptr3 - moveq.l #0x03,crt0_temp -_cs349_clear: - move.l (crt0_ptr3)+,(crt0_ptr4)+ - move.l (crt0_ptr3)+,crt0_spare6 - and.b #0xFE,crt0_spare6 | disable chip-select - move.l crt0_spare6,(crt0_ptr4)+ - dbra crt0_temp,_cs349_clear - - /*---------------------------------------------*/ - /* EPLD generated /CS[3..0] must be configured */ -_csepld_init: - move.l crt0_glue,crt0_ptr4 - lea.l _table_csepld(%pc),crt0_ptr3 - - move.b (crt0_ptr3)+,crt0_temp - or.b #0x20,crt0_temp | default width is 32 bits - tst.b crt0_buswidth | is boot PROM bus width 32 bits ? - beq _csepld1 | if not - and.b #0xDF,crt0_temp | set width to 16 bits -_csepld1: - moves.b crt0_temp,(crt0_ptr4)+ - - moveq.l #0x02,crt0_spare6 -_csepld2: - move.b (crt0_ptr3)+,crt0_temp - moves.b crt0_temp,(crt0_ptr4)+ - dbra crt0_spare6,_csepld2 - -_cs_init_end: - - /*--------------------------------------*/ - /* -- DRAM controller initialization -- */ -_dram_init: - move.w #15,crt0_temp - move.l #_ExtRam_Start,crt0_ptr3 - -_dram_init1: - clr.l (crt0_ptr3)+ | must access DRAM - dbra crt0_temp,_dram_init1 | prior to init refresh - -_dram_init2: - move.b #3,crt0_temp - moves.b crt0_temp,REG_WS(crt0_dram) | set 3 wait-states - - move.b #0x81,crt0_temp - moves.b crt0_temp,REG_REFRESH(crt0_dram) | refresh every 10µs - - move.b #0,crt0_temp - moves.b crt0_temp,REG_CONFIG(crt0_dram) | default size = 4Mbytes - - /*-----------------------*/ - /* -- configure cache -- */ -_init_cache: - move.l #0x000001E0,CACHE_MCR(crt0_sim_base) - btst.b #bit_cache,crt0_pdcs - bne _init_cache_end - or.l #0x00000001,CACHE_MCR(crt0_sim_base) - -_init_cache_end: - - /*-----------------------------*/ - /* -- timers initialization -- */ - - clr.b crt0_temp - moves.b crt0_temp,REG_TIMER1(crt0_glue) | disable timer 1 - moves.b crt0_temp,REG_TIMER2(crt0_glue) | disable timer 2 - - /*--------------------------*/ - /* -- I2C initialization -- */ - move.b #3,crt0_temp - moves.b crt0_temp,REG_I2C(crt0_glue) | tri-states I2C ports - - /*-----------------------------------------*/ - /* -- baudrate generator initialization -- */ - move.b #2,crt0_temp - moves.b crt0_temp,REG_BAUDRATE(crt0_glue) | baudrate = 38400 - - /*-------------------------------*/ - /* -- IO port initialization -- */ - clr.b crt0_temp - moves.b crt0_temp,REG_IO(crt0_glue) | set port as input - - /* -- */ - - move.l #68349,crt0_cpu_type - - - /* -- jump back to PROM -- */ - - jmp.l (_fill_test) | must be absolute long - -_copy_end: - -/*------------------------------------------------- - initialization code for the 68340 board - -------------------------------------------------*/ - - /* Astecc 68340 board : chip-select initialization values */ -_table_cs340: - dc.l 0x003FFFF0 /* Mask CS0 (4Mbytes PROM, 32bits, 0WS) */ - dc.l ((_PROM_Start&0xFFFFFF00)+0x00000003) /* Base CS0 */ - dc.l 0x0000FFFD /* MASK CS1 (RAMBCC340, 0WS, FTE) */ - dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000003) /* Base CS1 */ - dc.l 0x000000FF /* MASK CS2 (FLEX, ext DTACK, 256 bytes) */ - dc.l ((_FLEX_Start&0xFFFFFF00)+0x00000003) /* Base CS2 */ - dc.l 0x000000FF /* Mask CS3 (I2C, ext DTACK, 256 bytes) */ - dc.l ((_I2C_Start&0xFFFFFF00)+0x00000003) /* Base CS3 */ - -cpu_is_68340: - - /* -- set cpu clock -- */ - move.w #_SPEED340,SIM_SYNCR(crt0_sim_base) | clock -sync_wait340: - btst.b #3,(SIM_SYNCR+1)(crt0_sim_base) - beq sync_wait340 - - /* -- chip select initialization -- */ - lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 - lea.l _table_cs340(%pc),crt0_ptr3 - moveq.l #0x07,crt0_temp -_b_cs340: - move.l (crt0_ptr3)+,crt0_ptr5 - move.l crt0_ptr5,(crt0_ptr4)+ | pour test - dbra crt0_temp,_b_cs340 - - move.l #68340,crt0_cpu_type - move.b #0,crt0_csswitch | CPU - move.b #1,crt0_buswidth | 16 bits - - - /*------------------------------------------------- - fill RAM if COLDSTART - -------------------------------------------------*/ -_fill_test: - - tst.l crt0_boot_type - bne _dont_fill - - cmp.b #_CPU349,SIM_IDR(crt0_sim_base) - bne _fill - btst.b #bit_meminit,crt0_pdcs - bne _dont_fill - - /* fill main memory */ -_fill: - move.l #_crt0_init_stack,crt0_ptr3 | skip Astecc vars - move.l #_ExtRam_Start,crt0_temp - sub.l #_crt0_init_stack,crt0_temp - add.l #_ExtRam_Size,crt0_temp | get size - lsr.l #2,crt0_temp | ajust for long word -_fill_loop: - clr.l (crt0_ptr3)+ - subq.l #1,crt0_temp - bne _fill_loop - - cmp.b #_CPU349,SIM_IDR(crt0_sim_base) - bne _fill_bccram - - /* fill QDMM memory */ - movea.l #_FastRam_Start,crt0_ptr3 | get start - move.l #_FastRam_Size,crt0_temp | get size - lsr.l #2,crt0_temp | ajust for long word - -_QDMMfill_loop: - clr.l (crt0_ptr3)+ - subq.l #1,crt0_temp - bne _QDMMfill_loop - bra _dont_fill - - /* fill BCC memory */ -_fill_bccram: - movea.l #_BCCram_Start,crt0_ptr3 | get start - move.l #_BCCram_Size,crt0_temp | get size - lsr.l #2,crt0_temp | ajust for long word -_BCCfill_loop: - clr.l (crt0_ptr3)+ - subq.l #1,crt0_temp - bne _BCCfill_loop - - *-------------------------------------------------*/ -_dont_fill: - move.b crt0_csswitch,_AsteccCsSwitch - move.b crt0_buswidth,_AsteccBusWidth - move.l crt0_cpu_type,_AsteccCpuName - - jmp SYM(_Init68340) | Start C code (which never returns) - -/* - * Copy DATA segment, clear BSS segment, set up real stack, - * initialize heap, start C program. - * Assume that DATA and BSS sizes are multiples of 4. - */ - PUBLIC (_CopyDataClearBSSAndStart) -SYM(_CopyDataClearBSSAndStart): - lea copy_start,a0 | Get start of DATA in RAM - lea SYM(etext),a2 | Get start of DATA in ROM - cmpl a0,a2 | Are they the same? - beq.s NOCOPY | Yes, no copy necessary - lea copy_end,a1 | Get end of DATA in RAM - bra.s COPYLOOPTEST | Branch into copy loop -COPYLOOP: - movel a2@+,a0@+ | Copy word from ROM to RAM -COPYLOOPTEST: - cmpl a1,a0 | Done? - bcs.s COPYLOOP | No, skip -NOCOPY: - - lea clear_start,a0 | Get start of BSS - lea clear_end,a1 | Get end of BSS - clrl d0 | Value to set - bra.s ZEROLOOPTEST | Branch into clear loop -ZEROLOOP: - movel d0,a0@+ | Clear a word -ZEROLOOPTEST: - cmpl a1,a0 | Done? - bcs.s ZEROLOOP | No, skip - - movel #stack_init,a7 | set master stack pointer - movel d0,a7@- | environp - movel d0,a7@- | argv - movel d0,a7@- | argc - jsr SYM(boot_card) | Call C main - - PUBLIC (_mainDone) -SYM(_mainDone): - nop | Leave spot for breakpoint - movew #1,a7 | Force a double bus error - movel d0,a7@- | This should cause a RESET -/* stop #0x2700 | Stop with interrupts disabled */ - move.w #0x2700,sr - bra.s SYM(_mainDone) | Stuck forever - - .align 2 - PUBLIC (_HeapSize) -SYM (_HeapSize): - .long HeapSize - PUBLIC (_StackSize) -SYM (_StackSize): - .long StackSize -END_CODE - -BEGIN_DATA_DCL - .align 2 - PUBLIC (environ) -SYM (environ): - .long 0 - PUBLIC (_M68kSpuriousInterruptCount) -SYM (_M68kSpuriousInterruptCount): - .long 0 -END_DATA_DCL - -END - diff --git a/c/src/lib/libbsp/m68k/gen68340/start/startfor340only.S b/c/src/lib/libbsp/m68k/gen68340/start/startfor340only.S new file mode 100644 index 0000000000..930694f02e --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68340/start/startfor340only.S @@ -0,0 +1,499 @@ +/* + * This file contains the entry point for the application. + * The name of this entry point is compiler dependent. + * It jumps to the BSP which is responsible for performing + * all initialization. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * Based on the `gen68360' board support package, and covered by the + * original distribution terms. + * + * Geoffroy Montel + * France Telecom - CNET/DSM/TAM/CAT + * 4, rue du Clos Courtel + * 35512 CESSON-SEVIGNE + * FRANCE + * + * e-mail: g_montel@yahoo.com + * + * $Id$ + */ + +#include "asm.h" +#include + +BEGIN_CODE + /* + * Step 1: Decide on Reset Stack Pointer and Initial Program Counter + */ +Entry: + .long SYM(m340)+1024 | 0: Initial SSP + .long start | 1: Initial PC + .long SYM(_uhoh) | 2: Bus error + .long SYM(_uhoh) | 3: Address error + .long SYM(_uhoh) | 4: Illegal instruction + .long SYM(_uhoh) | 5: Zero division + .long SYM(_uhoh) | 6: CHK, CHK2 instruction + .long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions + .long SYM(_uhoh) | 8: Privilege violation + .long SYM(_uhoh) | 9: Trace + .long SYM(_uhoh) | 10: Line 1010 emulator + .long SYM(_uhoh) | 11: Line 1111 emulator + .long SYM(_uhoh) | 12: Hardware breakpoint + .long SYM(_uhoh) | 13: Reserved for coprocessor violation + .long SYM(_uhoh) | 14: Format error + .long SYM(_uhoh) | 15: Uninitialized interrupt + .long SYM(_uhoh) | 16: Unassigned, reserved + .long SYM(_uhoh) | 17: + .long SYM(_uhoh) | 18: + .long SYM(_uhoh) | 19: + .long SYM(_uhoh) | 20: + .long SYM(_uhoh) | 21: + .long SYM(_uhoh) | 22: + .long SYM(_uhoh) | 23: + .long SYM(_spuriousInterrupt) | 24: Spurious interrupt + .long SYM(_uhoh) | 25: Level 1 interrupt autovector + .long SYM(_uhoh) | 26: Level 2 interrupt autovector + .long SYM(_uhoh) | 27: Level 3 interrupt autovector + .long SYM(_uhoh) | 28: Level 4 interrupt autovector + .long SYM(_uhoh) | 29: Level 5 interrupt autovector + .long SYM(_uhoh) | 30: Level 6 interrupt autovector + .long SYM(_uhoh) | 31: Level 7 interrupt autovector + .long SYM(_uhoh) | 32: Trap instruction (0-15) + .long SYM(_uhoh) | 33: + .long SYM(_uhoh) | 34: + .long SYM(_uhoh) | 35: + .long SYM(_uhoh) | 36: + .long SYM(_uhoh) | 37: + .long SYM(_uhoh) | 38: + .long SYM(_uhoh) | 39: + .long SYM(_uhoh) | 40: + .long SYM(_uhoh) | 41: + .long SYM(_uhoh) | 42: + .long SYM(_uhoh) | 43: + .long SYM(_uhoh) | 44: + .long SYM(_uhoh) | 45: + .long SYM(_uhoh) | 46: + .long SYM(_uhoh) | 47: + .long SYM(_uhoh) | 48: Reserved for coprocessor + .long SYM(_uhoh) | 49: + .long SYM(_uhoh) | 50: + .long SYM(_uhoh) | 51: + .long SYM(_uhoh) | 52: + .long SYM(_uhoh) | 53: + .long SYM(_uhoh) | 54: + .long SYM(_uhoh) | 55: + .long SYM(_uhoh) | 56: + .long SYM(_uhoh) | 57: + .long SYM(_uhoh) | 58: + .long SYM(_uhoh) | 59: Unassigned, reserved + .long SYM(_uhoh) | 60: + .long SYM(_uhoh) | 61: + .long SYM(_uhoh) | 62: + .long SYM(_uhoh) | 63: + .long SYM(_uhoh) | 64: User defined vectors (192) + .long SYM(_uhoh) | 65: + .long SYM(_uhoh) | 66: + .long SYM(_uhoh) | 67: + .long SYM(_uhoh) | 68: + .long SYM(_uhoh) | 69: + .long SYM(_uhoh) | 70: + .long SYM(_uhoh) | 71: + .long SYM(_uhoh) | 72: + .long SYM(_uhoh) | 73: + .long SYM(_uhoh) | 74: + .long SYM(_uhoh) | 75: + .long SYM(_uhoh) | 76: + .long SYM(_uhoh) | 77: + .long SYM(_uhoh) | 78: + .long SYM(_uhoh) | 79: + .long SYM(_uhoh) | 80: + .long SYM(_uhoh) | 81: + .long SYM(_uhoh) | 82: + .long SYM(_uhoh) | 83: + .long SYM(_uhoh) | 84: + .long SYM(_uhoh) | 85: + .long SYM(_uhoh) | 86: + .long SYM(_uhoh) | 87: + .long SYM(_uhoh) | 88: + .long SYM(_uhoh) | 89: + .long SYM(_uhoh) | 90: + .long SYM(_uhoh) | 91: + .long SYM(_uhoh) | 92: + .long SYM(_uhoh) | 93: + .long SYM(_uhoh) | 94: + .long SYM(_uhoh) | 95: + .long SYM(_uhoh) | 96: + .long SYM(_uhoh) | 97: + .long SYM(_uhoh) | 98: + .long SYM(_uhoh) | 99: + .long SYM(_uhoh) | 100: + .long SYM(_uhoh) | 101: + .long SYM(_uhoh) | 102: + .long SYM(_uhoh) | 103: + .long SYM(_uhoh) | 104: + .long SYM(_uhoh) | 105: + .long SYM(_uhoh) | 106: + .long SYM(_uhoh) | 107: + .long SYM(_uhoh) | 108: + .long SYM(_uhoh) | 109: + .long SYM(_uhoh) | 110: + .long SYM(_uhoh) | 111: + .long SYM(_uhoh) | 112: + .long SYM(_uhoh) | 113: + .long SYM(_uhoh) | 114: + .long SYM(_uhoh) | 115: + .long SYM(_uhoh) | 116: + .long SYM(_uhoh) | 117: + .long SYM(_uhoh) | 118: + .long SYM(_uhoh) | 119: + .long SYM(_uhoh) | 120: + .long SYM(_uhoh) | 121: + .long SYM(_uhoh) | 122: + .long SYM(_uhoh) | 123: + .long SYM(_uhoh) | 124: + .long SYM(_uhoh) | 125: + .long SYM(_uhoh) | 126: + .long SYM(_uhoh) | 127: + .long SYM(_uhoh) | 128: + .long SYM(_uhoh) | 129: + .long SYM(_uhoh) | 130: + .long SYM(_uhoh) | 131: + .long SYM(_uhoh) | 132: + .long SYM(_uhoh) | 133: + .long SYM(_uhoh) | 134: + .long SYM(_uhoh) | 135: + .long SYM(_uhoh) | 136: + .long SYM(_uhoh) | 137: + .long SYM(_uhoh) | 138: + .long SYM(_uhoh) | 139: + .long SYM(_uhoh) | 140: + .long SYM(_uhoh) | 141: + .long SYM(_uhoh) | 142: + .long SYM(_uhoh) | 143: + .long SYM(_uhoh) | 144: + .long SYM(_uhoh) | 145: + .long SYM(_uhoh) | 146: + .long SYM(_uhoh) | 147: + .long SYM(_uhoh) | 148: + .long SYM(_uhoh) | 149: + .long SYM(_uhoh) | 150: + .long SYM(_uhoh) | 151: + .long SYM(_uhoh) | 152: + .long SYM(_uhoh) | 153: + .long SYM(_uhoh) | 154: + .long SYM(_uhoh) | 155: + .long SYM(_uhoh) | 156: + .long SYM(_uhoh) | 157: + .long SYM(_uhoh) | 158: + .long SYM(_uhoh) | 159: + .long SYM(_uhoh) | 160: + .long SYM(_uhoh) | 161: + .long SYM(_uhoh) | 162: + .long SYM(_uhoh) | 163: + .long SYM(_uhoh) | 164: + .long SYM(_uhoh) | 165: + .long SYM(_uhoh) | 166: + .long SYM(_uhoh) | 167: + .long SYM(_uhoh) | 168: + .long SYM(_uhoh) | 169: + .long SYM(_uhoh) | 170: + .long SYM(_uhoh) | 171: + .long SYM(_uhoh) | 172: + .long SYM(_uhoh) | 173: + .long SYM(_uhoh) | 174: + .long SYM(_uhoh) | 175: + .long SYM(_uhoh) | 176: + .long SYM(_uhoh) | 177: + .long SYM(_uhoh) | 178: + .long SYM(_uhoh) | 179: + .long SYM(_uhoh) | 180: + .long SYM(_uhoh) | 181: + .long SYM(_uhoh) | 182: + .long SYM(_uhoh) | 183: + .long SYM(_uhoh) | 184: + .long SYM(_uhoh) | 185: + .long SYM(_uhoh) | 186: + .long SYM(_uhoh) | 187: + .long SYM(_uhoh) | 188: + .long SYM(_uhoh) | 189: + .long SYM(_uhoh) | 190: + .long SYM(_uhoh) | 191: + .long SYM(_uhoh) | 192: + .long SYM(_uhoh) | 193: + .long SYM(_uhoh) | 194: + .long SYM(_uhoh) | 195: + .long SYM(_uhoh) | 196: + .long SYM(_uhoh) | 197: + .long SYM(_uhoh) | 198: + .long SYM(_uhoh) | 199: + .long SYM(_uhoh) | 200: + .long SYM(_uhoh) | 201: + .long SYM(_uhoh) | 202: + .long SYM(_uhoh) | 203: + .long SYM(_uhoh) | 204: + .long SYM(_uhoh) | 205: + .long SYM(_uhoh) | 206: + .long SYM(_uhoh) | 207: + .long SYM(_uhoh) | 208: + .long SYM(_uhoh) | 209: + .long SYM(_uhoh) | 210: + .long SYM(_uhoh) | 211: + .long SYM(_uhoh) | 212: + .long SYM(_uhoh) | 213: + .long SYM(_uhoh) | 214: + .long SYM(_uhoh) | 215: + .long SYM(_uhoh) | 216: + .long SYM(_uhoh) | 217: + .long SYM(_uhoh) | 218: + .long SYM(_uhoh) | 219: + .long SYM(_uhoh) | 220: + .long SYM(_uhoh) | 221: + .long SYM(_uhoh) | 222: + .long SYM(_uhoh) | 223: + .long SYM(_uhoh) | 224: + .long SYM(_uhoh) | 225: + .long SYM(_uhoh) | 226: + .long SYM(_uhoh) | 227: + .long SYM(_uhoh) | 228: + .long SYM(_uhoh) | 229: + .long SYM(_uhoh) | 230: + .long SYM(_uhoh) | 231: + .long SYM(_uhoh) | 232: + .long SYM(_uhoh) | 233: + .long SYM(_uhoh) | 234: + .long SYM(_uhoh) | 235: + .long SYM(_uhoh) | 236: + .long SYM(_uhoh) | 237: + .long SYM(_uhoh) | 238: + .long SYM(_uhoh) | 239: + .long SYM(_uhoh) | 240: + .long SYM(_uhoh) | 241: + .long SYM(_uhoh) | 242: + .long SYM(_uhoh) | 243: + .long SYM(_uhoh) | 244: + .long SYM(_uhoh) | 245: + .long SYM(_uhoh) | 246: + .long SYM(_uhoh) | 247: + .long SYM(_uhoh) | 248: + .long SYM(_uhoh) | 249: + .long SYM(_uhoh) | 250: + .long SYM(_uhoh) | 251: + .long SYM(_uhoh) | 252: + .long SYM(_uhoh) | 253: + .long SYM(_uhoh) | 254: + .long SYM(_uhoh) | 255: + +/* + * Default trap handler + * With an oscilloscope you can see AS* stop + */ + PUBLIC (_uhoh) +SYM(_uhoh): nop | Leave spot for breakpoint + stop #0x2700 | Stop with interrupts disabled + bra.s SYM(_uhoh) | Stuck forever + +/* + * Log, but otherwise ignore, spurious interrupts + */ + PUBLIC (_spuriousInterrupt) +SYM(_spuriousInterrupt): + addql #1,SYM(_M68kSpuriousInterruptCount) + rte + +/* + * Place the low-order 3 octets of the board's ethernet address at + * a `well-known' fixed location relative to the startup location. + */ + .align 2 + .word 0 | Padding +ethernet_address_buffer: + .word 0x08F3 | Default address + .word 0xDEAD + .word 0xCAFE + +/* -- equates -- */ +.equ _PROM_Start, 0x01000000 /* CS0 */ +.equ _BCCram_Start, 0x00000000 /* CS1 */ +.equ _FLEX_Start, 0x08000000 /* CS2 */ +.equ _I2C_Start, 0x02000000 /* CS3 */ +.equ _EXTram_Start, 0x10000000 /* CS4 */ +.equ _EXTram_Size, 0x000400000 /* 4 Mbytes */ +.equ _SPEED, 0xD780 /* 25 Mhz CPU349 */ +/* .equ _SPEED, 0xD700 25 Mhz */ +/* .equ _SPEED, 0xCE00 16 Mhz */ + +BEGIN_DATA + +_crt0_init_stack: + ds.l 0x1000 +_crt0_init_stktop: + + +BEGIN_CODE + dc.l _crt0_init_stktop /* reset SP */ + dc.l _crt0_cold_start /* reset PC */ + dc.l _crt0_warm_start + + .ascii "RTEMS" + dc.w 0 + +.align 2 + +_table_cs: + /* carte Astecc - 68340 */ + dc.l 0x003FFFF0 /* Mask CS0 (4Mbytes PROM, 32bits, 0WS) */ +/* dc.l 0x003FFFFD Mask CS0 (4Mbytes PROM, 16bits, 3WS) */ + dc.l ((_PROM_Start&0xFFFFFF00)+0x00000003) /* Base CS0 */ +/* dc.l 0x0000FFF1 MASK CS1 (RAMBCC340, 0WS, FTE) */ + dc.l 0x0000FFFD /* MASK CS1 (RAMBCC340, 0WS, FTE) */ +/* dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000007) Base CS1 */ + dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000003) /* Base CS1 */ + dc.l 0x000000FF /* MASK CS2 (FLEX, ext DTACK, 256 bytes) */ + dc.l ((_FLEX_Start&0xFFFFFF00)+0x00000003) /* Base CS2 */ + dc.l 0x000000FF /* Mask CS3 (I2C, ext DTACK, 256 bytes) */ + dc.l ((_I2C_Start&0xFFFFFF00)+0x00000003) /* Base CS3 */ + +/* + * Initial PC + */ +.globl start +start: + +_crt0_cold_start: + moveq.l #0,d0 /* signal cold reset */ + bra.s _crt0_common_start + +_crt0_warm_start: + moveq.l #1,d0 /* signal warm reset */ + +_crt0_common_start: + move.w #0x2700,sr /* disable interrupts and switch to interrupt mode */ + movea.l #_crt0_init_stktop,sp /* set up initialization stack */ + + lea Entry,a0 /* Get base of vector table */ + movec a0,vbr /* Set up the VBR */ + + moveq.l #0x07,d1 + movec.l d1,dfc /* prepare access in CPU space */ + move.l #(BASE_SIM+1),d1 + moves.l d1,BASE_REG /* base initialization (must be MOVES, PCC-130795) */ + moveq.l #0x05,d1 + movec.l d1,dfc + + movea.l #BASE_SIM,a0 + + /* -- disable Bus Monitor -- */ + move.b #0,SIM_SYPCR(a0) /* system protection control register */ + + /* -- set frequency to 25.16 Mhz -- */ + move.w #_SPEED,SIM_SYNCR(a0) /* clock */ + +sync_wait: + btst.b #3,(SIM_SYNCR+1)(a0) + beq sync_wait + + /* -- enable A31-A24 -- */ + clr.b SIM_PPRA1(a0) + + /* -- show cycles, user acces to SIM, 4 /CS & 4 /IT -- */ + move.w #0x427F,SIM_MCR(a0) + + /* -- chip select initialization -- */ + lea.l SIM_MASKH0(a0),a2 + lea.l _table_cs(%pc),a1 + + moveq.l #0x07,d1 + +_b_cs: + move.l (a1)+, (a2)+ + dbra d1,_b_cs + + /* fill RAM if COLDSTART */ + tst.l d0 + bne _dont_fill + + movea.l #_EXTram_Start,a0 /* get start */ + move.l #_EXTram_Size,d1 /* get size */ + lsr.l #2,d1 /* ajust for long word */ + +_fill_loop: + clr.l (a0)+ + subq.l #1,d1 + bne _fill_loop + +_dont_fill: + jmp SYM(_Init68340) | Start C code (which never returns) + +/* + * Copy DATA segment, clear BSS segment, set up real stack, + * initialize heap, start C program. + * Assume that DATA and BSS sizes are multiples of 4. + */ + PUBLIC (_CopyDataClearBSSAndStart) +SYM(_CopyDataClearBSSAndStart): + lea copy_start,a0 | Get start of DATA in RAM + lea SYM(etext),a2 | Get start of DATA in ROM + cmpl a0,a2 | Are they the same? + beq.s NOCOPY | Yes, no copy necessary + lea copy_end,a1 | Get end of DATA in RAM + bra.s COPYLOOPTEST | Branch into copy loop +COPYLOOP: + movel a2@+,a0@+ | Copy word from ROM to RAM +COPYLOOPTEST: + cmpl a1,a0 | Done? + bcs.s COPYLOOP | No, skip +NOCOPY: + + lea clear_start,a0 | Get start of BSS + lea clear_end,a1 | Get end of BSS + clrl d0 | Value to set + bra.s ZEROLOOPTEST | Branch into clear loop +ZEROLOOP: + movel d0,a0@+ | Clear a word +ZEROLOOPTEST: + cmpl a1,a0 | Done? + bcs.s ZEROLOOP | No, skip + + movel #stack_init,a7 | set master stack pointer + movel d0,a7@- | environp + movel d0,a7@- | argv + movel d0,a7@- | argc + jsr SYM(boot_card) | Call C main + + PUBLIC (_mainDone) +SYM(_mainDone): + nop | Leave spot for breakpoint + movew #1,a7 | Force a double bus error + movel d0,a7@- | This should cause a RESET + stop #0x2700 | Stop with interrupts disabled + bra.s SYM(_mainDone) | Stuck forever + + .align 2 + PUBLIC (_HeapSize) +SYM (_HeapSize): + .long HeapSize + PUBLIC (_StackSize) +SYM (_StackSize): + .long StackSize +END_CODE + +BEGIN_DATA_DCL + .align 2 + PUBLIC (environ) +SYM (environ): + .long 0 + PUBLIC (_M68kSpuriousInterruptCount) +SYM (_M68kSpuriousInterruptCount): + .long 0 +END_DATA_DCL + +END + diff --git a/c/src/lib/libbsp/m68k/gen68340/start/startfor340only.s b/c/src/lib/libbsp/m68k/gen68340/start/startfor340only.s deleted file mode 100644 index 930694f02e..0000000000 --- a/c/src/lib/libbsp/m68k/gen68340/start/startfor340only.s +++ /dev/null @@ -1,499 +0,0 @@ -/* - * This file contains the entry point for the application. - * The name of this entry point is compiler dependent. - * It jumps to the BSP which is responsible for performing - * all initialization. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may in - * the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * Based on the `gen68360' board support package, and covered by the - * original distribution terms. - * - * Geoffroy Montel - * France Telecom - CNET/DSM/TAM/CAT - * 4, rue du Clos Courtel - * 35512 CESSON-SEVIGNE - * FRANCE - * - * e-mail: g_montel@yahoo.com - * - * $Id$ - */ - -#include "asm.h" -#include - -BEGIN_CODE - /* - * Step 1: Decide on Reset Stack Pointer and Initial Program Counter - */ -Entry: - .long SYM(m340)+1024 | 0: Initial SSP - .long start | 1: Initial PC - .long SYM(_uhoh) | 2: Bus error - .long SYM(_uhoh) | 3: Address error - .long SYM(_uhoh) | 4: Illegal instruction - .long SYM(_uhoh) | 5: Zero division - .long SYM(_uhoh) | 6: CHK, CHK2 instruction - .long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions - .long SYM(_uhoh) | 8: Privilege violation - .long SYM(_uhoh) | 9: Trace - .long SYM(_uhoh) | 10: Line 1010 emulator - .long SYM(_uhoh) | 11: Line 1111 emulator - .long SYM(_uhoh) | 12: Hardware breakpoint - .long SYM(_uhoh) | 13: Reserved for coprocessor violation - .long SYM(_uhoh) | 14: Format error - .long SYM(_uhoh) | 15: Uninitialized interrupt - .long SYM(_uhoh) | 16: Unassigned, reserved - .long SYM(_uhoh) | 17: - .long SYM(_uhoh) | 18: - .long SYM(_uhoh) | 19: - .long SYM(_uhoh) | 20: - .long SYM(_uhoh) | 21: - .long SYM(_uhoh) | 22: - .long SYM(_uhoh) | 23: - .long SYM(_spuriousInterrupt) | 24: Spurious interrupt - .long SYM(_uhoh) | 25: Level 1 interrupt autovector - .long SYM(_uhoh) | 26: Level 2 interrupt autovector - .long SYM(_uhoh) | 27: Level 3 interrupt autovector - .long SYM(_uhoh) | 28: Level 4 interrupt autovector - .long SYM(_uhoh) | 29: Level 5 interrupt autovector - .long SYM(_uhoh) | 30: Level 6 interrupt autovector - .long SYM(_uhoh) | 31: Level 7 interrupt autovector - .long SYM(_uhoh) | 32: Trap instruction (0-15) - .long SYM(_uhoh) | 33: - .long SYM(_uhoh) | 34: - .long SYM(_uhoh) | 35: - .long SYM(_uhoh) | 36: - .long SYM(_uhoh) | 37: - .long SYM(_uhoh) | 38: - .long SYM(_uhoh) | 39: - .long SYM(_uhoh) | 40: - .long SYM(_uhoh) | 41: - .long SYM(_uhoh) | 42: - .long SYM(_uhoh) | 43: - .long SYM(_uhoh) | 44: - .long SYM(_uhoh) | 45: - .long SYM(_uhoh) | 46: - .long SYM(_uhoh) | 47: - .long SYM(_uhoh) | 48: Reserved for coprocessor - .long SYM(_uhoh) | 49: - .long SYM(_uhoh) | 50: - .long SYM(_uhoh) | 51: - .long SYM(_uhoh) | 52: - .long SYM(_uhoh) | 53: - .long SYM(_uhoh) | 54: - .long SYM(_uhoh) | 55: - .long SYM(_uhoh) | 56: - .long SYM(_uhoh) | 57: - .long SYM(_uhoh) | 58: - .long SYM(_uhoh) | 59: Unassigned, reserved - .long SYM(_uhoh) | 60: - .long SYM(_uhoh) | 61: - .long SYM(_uhoh) | 62: - .long SYM(_uhoh) | 63: - .long SYM(_uhoh) | 64: User defined vectors (192) - .long SYM(_uhoh) | 65: - .long SYM(_uhoh) | 66: - .long SYM(_uhoh) | 67: - .long SYM(_uhoh) | 68: - .long SYM(_uhoh) | 69: - .long SYM(_uhoh) | 70: - .long SYM(_uhoh) | 71: - .long SYM(_uhoh) | 72: - .long SYM(_uhoh) | 73: - .long SYM(_uhoh) | 74: - .long SYM(_uhoh) | 75: - .long SYM(_uhoh) | 76: - .long SYM(_uhoh) | 77: - .long SYM(_uhoh) | 78: - .long SYM(_uhoh) | 79: - .long SYM(_uhoh) | 80: - .long SYM(_uhoh) | 81: - .long SYM(_uhoh) | 82: - .long SYM(_uhoh) | 83: - .long SYM(_uhoh) | 84: - .long SYM(_uhoh) | 85: - .long SYM(_uhoh) | 86: - .long SYM(_uhoh) | 87: - .long SYM(_uhoh) | 88: - .long SYM(_uhoh) | 89: - .long SYM(_uhoh) | 90: - .long SYM(_uhoh) | 91: - .long SYM(_uhoh) | 92: - .long SYM(_uhoh) | 93: - .long SYM(_uhoh) | 94: - .long SYM(_uhoh) | 95: - .long SYM(_uhoh) | 96: - .long SYM(_uhoh) | 97: - .long SYM(_uhoh) | 98: - .long SYM(_uhoh) | 99: - .long SYM(_uhoh) | 100: - .long SYM(_uhoh) | 101: - .long SYM(_uhoh) | 102: - .long SYM(_uhoh) | 103: - .long SYM(_uhoh) | 104: - .long SYM(_uhoh) | 105: - .long SYM(_uhoh) | 106: - .long SYM(_uhoh) | 107: - .long SYM(_uhoh) | 108: - .long SYM(_uhoh) | 109: - .long SYM(_uhoh) | 110: - .long SYM(_uhoh) | 111: - .long SYM(_uhoh) | 112: - .long SYM(_uhoh) | 113: - .long SYM(_uhoh) | 114: - .long SYM(_uhoh) | 115: - .long SYM(_uhoh) | 116: - .long SYM(_uhoh) | 117: - .long SYM(_uhoh) | 118: - .long SYM(_uhoh) | 119: - .long SYM(_uhoh) | 120: - .long SYM(_uhoh) | 121: - .long SYM(_uhoh) | 122: - .long SYM(_uhoh) | 123: - .long SYM(_uhoh) | 124: - .long SYM(_uhoh) | 125: - .long SYM(_uhoh) | 126: - .long SYM(_uhoh) | 127: - .long SYM(_uhoh) | 128: - .long SYM(_uhoh) | 129: - .long SYM(_uhoh) | 130: - .long SYM(_uhoh) | 131: - .long SYM(_uhoh) | 132: - .long SYM(_uhoh) | 133: - .long SYM(_uhoh) | 134: - .long SYM(_uhoh) | 135: - .long SYM(_uhoh) | 136: - .long SYM(_uhoh) | 137: - .long SYM(_uhoh) | 138: - .long SYM(_uhoh) | 139: - .long SYM(_uhoh) | 140: - .long SYM(_uhoh) | 141: - .long SYM(_uhoh) | 142: - .long SYM(_uhoh) | 143: - .long SYM(_uhoh) | 144: - .long SYM(_uhoh) | 145: - .long SYM(_uhoh) | 146: - .long SYM(_uhoh) | 147: - .long SYM(_uhoh) | 148: - .long SYM(_uhoh) | 149: - .long SYM(_uhoh) | 150: - .long SYM(_uhoh) | 151: - .long SYM(_uhoh) | 152: - .long SYM(_uhoh) | 153: - .long SYM(_uhoh) | 154: - .long SYM(_uhoh) | 155: - .long SYM(_uhoh) | 156: - .long SYM(_uhoh) | 157: - .long SYM(_uhoh) | 158: - .long SYM(_uhoh) | 159: - .long SYM(_uhoh) | 160: - .long SYM(_uhoh) | 161: - .long SYM(_uhoh) | 162: - .long SYM(_uhoh) | 163: - .long SYM(_uhoh) | 164: - .long SYM(_uhoh) | 165: - .long SYM(_uhoh) | 166: - .long SYM(_uhoh) | 167: - .long SYM(_uhoh) | 168: - .long SYM(_uhoh) | 169: - .long SYM(_uhoh) | 170: - .long SYM(_uhoh) | 171: - .long SYM(_uhoh) | 172: - .long SYM(_uhoh) | 173: - .long SYM(_uhoh) | 174: - .long SYM(_uhoh) | 175: - .long SYM(_uhoh) | 176: - .long SYM(_uhoh) | 177: - .long SYM(_uhoh) | 178: - .long SYM(_uhoh) | 179: - .long SYM(_uhoh) | 180: - .long SYM(_uhoh) | 181: - .long SYM(_uhoh) | 182: - .long SYM(_uhoh) | 183: - .long SYM(_uhoh) | 184: - .long SYM(_uhoh) | 185: - .long SYM(_uhoh) | 186: - .long SYM(_uhoh) | 187: - .long SYM(_uhoh) | 188: - .long SYM(_uhoh) | 189: - .long SYM(_uhoh) | 190: - .long SYM(_uhoh) | 191: - .long SYM(_uhoh) | 192: - .long SYM(_uhoh) | 193: - .long SYM(_uhoh) | 194: - .long SYM(_uhoh) | 195: - .long SYM(_uhoh) | 196: - .long SYM(_uhoh) | 197: - .long SYM(_uhoh) | 198: - .long SYM(_uhoh) | 199: - .long SYM(_uhoh) | 200: - .long SYM(_uhoh) | 201: - .long SYM(_uhoh) | 202: - .long SYM(_uhoh) | 203: - .long SYM(_uhoh) | 204: - .long SYM(_uhoh) | 205: - .long SYM(_uhoh) | 206: - .long SYM(_uhoh) | 207: - .long SYM(_uhoh) | 208: - .long SYM(_uhoh) | 209: - .long SYM(_uhoh) | 210: - .long SYM(_uhoh) | 211: - .long SYM(_uhoh) | 212: - .long SYM(_uhoh) | 213: - .long SYM(_uhoh) | 214: - .long SYM(_uhoh) | 215: - .long SYM(_uhoh) | 216: - .long SYM(_uhoh) | 217: - .long SYM(_uhoh) | 218: - .long SYM(_uhoh) | 219: - .long SYM(_uhoh) | 220: - .long SYM(_uhoh) | 221: - .long SYM(_uhoh) | 222: - .long SYM(_uhoh) | 223: - .long SYM(_uhoh) | 224: - .long SYM(_uhoh) | 225: - .long SYM(_uhoh) | 226: - .long SYM(_uhoh) | 227: - .long SYM(_uhoh) | 228: - .long SYM(_uhoh) | 229: - .long SYM(_uhoh) | 230: - .long SYM(_uhoh) | 231: - .long SYM(_uhoh) | 232: - .long SYM(_uhoh) | 233: - .long SYM(_uhoh) | 234: - .long SYM(_uhoh) | 235: - .long SYM(_uhoh) | 236: - .long SYM(_uhoh) | 237: - .long SYM(_uhoh) | 238: - .long SYM(_uhoh) | 239: - .long SYM(_uhoh) | 240: - .long SYM(_uhoh) | 241: - .long SYM(_uhoh) | 242: - .long SYM(_uhoh) | 243: - .long SYM(_uhoh) | 244: - .long SYM(_uhoh) | 245: - .long SYM(_uhoh) | 246: - .long SYM(_uhoh) | 247: - .long SYM(_uhoh) | 248: - .long SYM(_uhoh) | 249: - .long SYM(_uhoh) | 250: - .long SYM(_uhoh) | 251: - .long SYM(_uhoh) | 252: - .long SYM(_uhoh) | 253: - .long SYM(_uhoh) | 254: - .long SYM(_uhoh) | 255: - -/* - * Default trap handler - * With an oscilloscope you can see AS* stop - */ - PUBLIC (_uhoh) -SYM(_uhoh): nop | Leave spot for breakpoint - stop #0x2700 | Stop with interrupts disabled - bra.s SYM(_uhoh) | Stuck forever - -/* - * Log, but otherwise ignore, spurious interrupts - */ - PUBLIC (_spuriousInterrupt) -SYM(_spuriousInterrupt): - addql #1,SYM(_M68kSpuriousInterruptCount) - rte - -/* - * Place the low-order 3 octets of the board's ethernet address at - * a `well-known' fixed location relative to the startup location. - */ - .align 2 - .word 0 | Padding -ethernet_address_buffer: - .word 0x08F3 | Default address - .word 0xDEAD - .word 0xCAFE - -/* -- equates -- */ -.equ _PROM_Start, 0x01000000 /* CS0 */ -.equ _BCCram_Start, 0x00000000 /* CS1 */ -.equ _FLEX_Start, 0x08000000 /* CS2 */ -.equ _I2C_Start, 0x02000000 /* CS3 */ -.equ _EXTram_Start, 0x10000000 /* CS4 */ -.equ _EXTram_Size, 0x000400000 /* 4 Mbytes */ -.equ _SPEED, 0xD780 /* 25 Mhz CPU349 */ -/* .equ _SPEED, 0xD700 25 Mhz */ -/* .equ _SPEED, 0xCE00 16 Mhz */ - -BEGIN_DATA - -_crt0_init_stack: - ds.l 0x1000 -_crt0_init_stktop: - - -BEGIN_CODE - dc.l _crt0_init_stktop /* reset SP */ - dc.l _crt0_cold_start /* reset PC */ - dc.l _crt0_warm_start - - .ascii "RTEMS" - dc.w 0 - -.align 2 - -_table_cs: - /* carte Astecc - 68340 */ - dc.l 0x003FFFF0 /* Mask CS0 (4Mbytes PROM, 32bits, 0WS) */ -/* dc.l 0x003FFFFD Mask CS0 (4Mbytes PROM, 16bits, 3WS) */ - dc.l ((_PROM_Start&0xFFFFFF00)+0x00000003) /* Base CS0 */ -/* dc.l 0x0000FFF1 MASK CS1 (RAMBCC340, 0WS, FTE) */ - dc.l 0x0000FFFD /* MASK CS1 (RAMBCC340, 0WS, FTE) */ -/* dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000007) Base CS1 */ - dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000003) /* Base CS1 */ - dc.l 0x000000FF /* MASK CS2 (FLEX, ext DTACK, 256 bytes) */ - dc.l ((_FLEX_Start&0xFFFFFF00)+0x00000003) /* Base CS2 */ - dc.l 0x000000FF /* Mask CS3 (I2C, ext DTACK, 256 bytes) */ - dc.l ((_I2C_Start&0xFFFFFF00)+0x00000003) /* Base CS3 */ - -/* - * Initial PC - */ -.globl start -start: - -_crt0_cold_start: - moveq.l #0,d0 /* signal cold reset */ - bra.s _crt0_common_start - -_crt0_warm_start: - moveq.l #1,d0 /* signal warm reset */ - -_crt0_common_start: - move.w #0x2700,sr /* disable interrupts and switch to interrupt mode */ - movea.l #_crt0_init_stktop,sp /* set up initialization stack */ - - lea Entry,a0 /* Get base of vector table */ - movec a0,vbr /* Set up the VBR */ - - moveq.l #0x07,d1 - movec.l d1,dfc /* prepare access in CPU space */ - move.l #(BASE_SIM+1),d1 - moves.l d1,BASE_REG /* base initialization (must be MOVES, PCC-130795) */ - moveq.l #0x05,d1 - movec.l d1,dfc - - movea.l #BASE_SIM,a0 - - /* -- disable Bus Monitor -- */ - move.b #0,SIM_SYPCR(a0) /* system protection control register */ - - /* -- set frequency to 25.16 Mhz -- */ - move.w #_SPEED,SIM_SYNCR(a0) /* clock */ - -sync_wait: - btst.b #3,(SIM_SYNCR+1)(a0) - beq sync_wait - - /* -- enable A31-A24 -- */ - clr.b SIM_PPRA1(a0) - - /* -- show cycles, user acces to SIM, 4 /CS & 4 /IT -- */ - move.w #0x427F,SIM_MCR(a0) - - /* -- chip select initialization -- */ - lea.l SIM_MASKH0(a0),a2 - lea.l _table_cs(%pc),a1 - - moveq.l #0x07,d1 - -_b_cs: - move.l (a1)+, (a2)+ - dbra d1,_b_cs - - /* fill RAM if COLDSTART */ - tst.l d0 - bne _dont_fill - - movea.l #_EXTram_Start,a0 /* get start */ - move.l #_EXTram_Size,d1 /* get size */ - lsr.l #2,d1 /* ajust for long word */ - -_fill_loop: - clr.l (a0)+ - subq.l #1,d1 - bne _fill_loop - -_dont_fill: - jmp SYM(_Init68340) | Start C code (which never returns) - -/* - * Copy DATA segment, clear BSS segment, set up real stack, - * initialize heap, start C program. - * Assume that DATA and BSS sizes are multiples of 4. - */ - PUBLIC (_CopyDataClearBSSAndStart) -SYM(_CopyDataClearBSSAndStart): - lea copy_start,a0 | Get start of DATA in RAM - lea SYM(etext),a2 | Get start of DATA in ROM - cmpl a0,a2 | Are they the same? - beq.s NOCOPY | Yes, no copy necessary - lea copy_end,a1 | Get end of DATA in RAM - bra.s COPYLOOPTEST | Branch into copy loop -COPYLOOP: - movel a2@+,a0@+ | Copy word from ROM to RAM -COPYLOOPTEST: - cmpl a1,a0 | Done? - bcs.s COPYLOOP | No, skip -NOCOPY: - - lea clear_start,a0 | Get start of BSS - lea clear_end,a1 | Get end of BSS - clrl d0 | Value to set - bra.s ZEROLOOPTEST | Branch into clear loop -ZEROLOOP: - movel d0,a0@+ | Clear a word -ZEROLOOPTEST: - cmpl a1,a0 | Done? - bcs.s ZEROLOOP | No, skip - - movel #stack_init,a7 | set master stack pointer - movel d0,a7@- | environp - movel d0,a7@- | argv - movel d0,a7@- | argc - jsr SYM(boot_card) | Call C main - - PUBLIC (_mainDone) -SYM(_mainDone): - nop | Leave spot for breakpoint - movew #1,a7 | Force a double bus error - movel d0,a7@- | This should cause a RESET - stop #0x2700 | Stop with interrupts disabled - bra.s SYM(_mainDone) | Stuck forever - - .align 2 - PUBLIC (_HeapSize) -SYM (_HeapSize): - .long HeapSize - PUBLIC (_StackSize) -SYM (_StackSize): - .long StackSize -END_CODE - -BEGIN_DATA_DCL - .align 2 - PUBLIC (environ) -SYM (environ): - .long 0 - PUBLIC (_M68kSpuriousInterruptCount) -SYM (_M68kSpuriousInterruptCount): - .long 0 -END_DATA_DCL - -END - diff --git a/c/src/lib/libbsp/m68k/gen68340/start340/Makefile.in b/c/src/lib/libbsp/m68k/gen68340/start340/Makefile.in index ce91b95e3b..4dfebd249f 100644 --- a/c/src/lib/libbsp/m68k/gen68340/start340/Makefile.in +++ b/c/src/lib/libbsp/m68k/gen68340/start340/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=start340 -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/m68k/gen68340/start340/start340.S b/c/src/lib/libbsp/m68k/gen68340/start340/start340.S new file mode 100644 index 0000000000..58ea0c92d0 --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68340/start340/start340.S @@ -0,0 +1,874 @@ +/* + * This file contains the entry point for the application. + * The name of this entry point is compiler dependent. + * It jumps to the BSP which is responsible for performing + * all initialization. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * Based on the `gen68360' board support package, and covered by the + * original distribution terms. + * + * Geoffroy Montel + * France Telecom - CNET/DSM/TAM/CAT + * 4, rue du Clos Courtel + * 35512 CESSON-SEVIGNE + * FRANCE + * + * e-mail: g_montel@yahoo.com + * + * $Id$ + */ + +#include "asm.h" +#include + +#define _OLD_ASTECC 1 /* old addresses for AST68340 only, undefine for AST68349 */ + +BEGIN_CODE + /* + * Step 1: Decide on Reset Stack Pointer and Initial Program Counter + */ +Entry: + .long SYM(m340)+1024 | 0: Initial SSP + .long start | 1: Initial PC + .long SYM(_uhoh) | 2: Bus error + .long SYM(_uhoh) | 3: Address error + .long SYM(_uhoh) | 4: Illegal instruction + .long SYM(_uhoh) | 5: Zero division + .long SYM(_uhoh) | 6: CHK, CHK2 instruction + .long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions + .long SYM(_uhoh) | 8: Privilege violation + .long SYM(_uhoh) | 9: Trace + .long SYM(_uhoh) | 10: Line 1010 emulator + .long SYM(_uhoh) | 11: Line 1111 emulator + .long SYM(_uhoh) | 12: Hardware breakpoint + .long SYM(_uhoh) | 13: Reserved for coprocessor violation + .long SYM(_uhoh) | 14: Format error + .long SYM(_uhoh) | 15: Uninitialized interrupt + .long SYM(_uhoh) | 16: Unassigned, reserved + .long SYM(_uhoh) | 17: + .long SYM(_uhoh) | 18: + .long SYM(_uhoh) | 19: + .long SYM(_uhoh) | 20: + .long SYM(_uhoh) | 21: + .long SYM(_uhoh) | 22: + .long SYM(_uhoh) | 23: + .long SYM(_spuriousInterrupt) | 24: Spurious interrupt + .long SYM(_uhoh) | 25: Level 1 interrupt autovector + .long SYM(_uhoh) | 26: Level 2 interrupt autovector + .long SYM(_uhoh) | 27: Level 3 interrupt autovector + .long SYM(_uhoh) | 28: Level 4 interrupt autovector + .long SYM(_uhoh) | 29: Level 5 interrupt autovector + .long SYM(_uhoh) | 30: Level 6 interrupt autovector + .long SYM(_uhoh) | 31: Level 7 interrupt autovector + .long SYM(_uhoh) | 32: Trap instruction (0-15) + .long SYM(_uhoh) | 33: + .long SYM(_uhoh) | 34: + .long SYM(_uhoh) | 35: + .long SYM(_uhoh) | 36: + .long SYM(_uhoh) | 37: + .long SYM(_uhoh) | 38: + .long SYM(_uhoh) | 39: + .long SYM(_uhoh) | 40: + .long SYM(_uhoh) | 41: + .long SYM(_uhoh) | 42: + .long SYM(_uhoh) | 43: + .long SYM(_uhoh) | 44: + .long SYM(_uhoh) | 45: + .long SYM(_uhoh) | 46: + .long SYM(_uhoh) | 47: + .long SYM(_uhoh) | 48: Reserved for coprocessor + .long SYM(_uhoh) | 49: + .long SYM(_uhoh) | 50: + .long SYM(_uhoh) | 51: + .long SYM(_uhoh) | 52: + .long SYM(_uhoh) | 53: + .long SYM(_uhoh) | 54: + .long SYM(_uhoh) | 55: + .long SYM(_uhoh) | 56: + .long SYM(_uhoh) | 57: + .long SYM(_uhoh) | 58: + .long SYM(_uhoh) | 59: Unassigned, reserved + .long SYM(_uhoh) | 60: + .long SYM(_uhoh) | 61: + .long SYM(_uhoh) | 62: + .long SYM(_uhoh) | 63: + .long SYM(_uhoh) | 64: User defined vectors (192) + .long SYM(_uhoh) | 65: + .long SYM(_uhoh) | 66: + .long SYM(_uhoh) | 67: + .long SYM(_uhoh) | 68: + .long SYM(_uhoh) | 69: + .long SYM(_uhoh) | 70: + .long SYM(_uhoh) | 71: + .long SYM(_uhoh) | 72: + .long SYM(_uhoh) | 73: + .long SYM(_uhoh) | 74: + .long SYM(_uhoh) | 75: + .long SYM(_uhoh) | 76: + .long SYM(_uhoh) | 77: + .long SYM(_uhoh) | 78: + .long SYM(_uhoh) | 79: + .long SYM(_uhoh) | 80: + .long SYM(_uhoh) | 81: + .long SYM(_uhoh) | 82: + .long SYM(_uhoh) | 83: + .long SYM(_uhoh) | 84: + .long SYM(_uhoh) | 85: + .long SYM(_uhoh) | 86: + .long SYM(_uhoh) | 87: + .long SYM(_uhoh) | 88: + .long SYM(_uhoh) | 89: + .long SYM(_uhoh) | 90: + .long SYM(_uhoh) | 91: + .long SYM(_uhoh) | 92: + .long SYM(_uhoh) | 93: + .long SYM(_uhoh) | 94: + .long SYM(_uhoh) | 95: + .long SYM(_uhoh) | 96: + .long SYM(_uhoh) | 97: + .long SYM(_uhoh) | 98: + .long SYM(_uhoh) | 99: + .long SYM(_uhoh) | 100: + .long SYM(_uhoh) | 101: + .long SYM(_uhoh) | 102: + .long SYM(_uhoh) | 103: + .long SYM(_uhoh) | 104: + .long SYM(_uhoh) | 105: + .long SYM(_uhoh) | 106: + .long SYM(_uhoh) | 107: + .long SYM(_uhoh) | 108: + .long SYM(_uhoh) | 109: + .long SYM(_uhoh) | 110: + .long SYM(_uhoh) | 111: + .long SYM(_uhoh) | 112: + .long SYM(_uhoh) | 113: + .long SYM(_uhoh) | 114: + .long SYM(_uhoh) | 115: + .long SYM(_uhoh) | 116: + .long SYM(_uhoh) | 117: + .long SYM(_uhoh) | 118: + .long SYM(_uhoh) | 119: + .long SYM(_uhoh) | 120: + .long SYM(_uhoh) | 121: + .long SYM(_uhoh) | 122: + .long SYM(_uhoh) | 123: + .long SYM(_uhoh) | 124: + .long SYM(_uhoh) | 125: + .long SYM(_uhoh) | 126: + .long SYM(_uhoh) | 127: + .long SYM(_uhoh) | 128: + .long SYM(_uhoh) | 129: + .long SYM(_uhoh) | 130: + .long SYM(_uhoh) | 131: + .long SYM(_uhoh) | 132: + .long SYM(_uhoh) | 133: + .long SYM(_uhoh) | 134: + .long SYM(_uhoh) | 135: + .long SYM(_uhoh) | 136: + .long SYM(_uhoh) | 137: + .long SYM(_uhoh) | 138: + .long SYM(_uhoh) | 139: + .long SYM(_uhoh) | 140: + .long SYM(_uhoh) | 141: + .long SYM(_uhoh) | 142: + .long SYM(_uhoh) | 143: + .long SYM(_uhoh) | 144: + .long SYM(_uhoh) | 145: + .long SYM(_uhoh) | 146: + .long SYM(_uhoh) | 147: + .long SYM(_uhoh) | 148: + .long SYM(_uhoh) | 149: + .long SYM(_uhoh) | 150: + .long SYM(_uhoh) | 151: + .long SYM(_uhoh) | 152: + .long SYM(_uhoh) | 153: + .long SYM(_uhoh) | 154: + .long SYM(_uhoh) | 155: + .long SYM(_uhoh) | 156: + .long SYM(_uhoh) | 157: + .long SYM(_uhoh) | 158: + .long SYM(_uhoh) | 159: + .long SYM(_uhoh) | 160: + .long SYM(_uhoh) | 161: + .long SYM(_uhoh) | 162: + .long SYM(_uhoh) | 163: + .long SYM(_uhoh) | 164: + .long SYM(_uhoh) | 165: + .long SYM(_uhoh) | 166: + .long SYM(_uhoh) | 167: + .long SYM(_uhoh) | 168: + .long SYM(_uhoh) | 169: + .long SYM(_uhoh) | 170: + .long SYM(_uhoh) | 171: + .long SYM(_uhoh) | 172: + .long SYM(_uhoh) | 173: + .long SYM(_uhoh) | 174: + .long SYM(_uhoh) | 175: + .long SYM(_uhoh) | 176: + .long SYM(_uhoh) | 177: + .long SYM(_uhoh) | 178: + .long SYM(_uhoh) | 179: + .long SYM(_uhoh) | 180: + .long SYM(_uhoh) | 181: + .long SYM(_uhoh) | 182: + .long SYM(_uhoh) | 183: + .long SYM(_uhoh) | 184: + .long SYM(_uhoh) | 185: + .long SYM(_uhoh) | 186: + .long SYM(_uhoh) | 187: + .long SYM(_uhoh) | 188: + .long SYM(_uhoh) | 189: + .long SYM(_uhoh) | 190: + .long SYM(_uhoh) | 191: + .long SYM(_uhoh) | 192: + .long SYM(_uhoh) | 193: + .long SYM(_uhoh) | 194: + .long SYM(_uhoh) | 195: + .long SYM(_uhoh) | 196: + .long SYM(_uhoh) | 197: + .long SYM(_uhoh) | 198: + .long SYM(_uhoh) | 199: + .long SYM(_uhoh) | 200: + .long SYM(_uhoh) | 201: + .long SYM(_uhoh) | 202: + .long SYM(_uhoh) | 203: + .long SYM(_uhoh) | 204: + .long SYM(_uhoh) | 205: + .long SYM(_uhoh) | 206: + .long SYM(_uhoh) | 207: + .long SYM(_uhoh) | 208: + .long SYM(_uhoh) | 209: + .long SYM(_uhoh) | 210: + .long SYM(_uhoh) | 211: + .long SYM(_uhoh) | 212: + .long SYM(_uhoh) | 213: + .long SYM(_uhoh) | 214: + .long SYM(_uhoh) | 215: + .long SYM(_uhoh) | 216: + .long SYM(_uhoh) | 217: + .long SYM(_uhoh) | 218: + .long SYM(_uhoh) | 219: + .long SYM(_uhoh) | 220: + .long SYM(_uhoh) | 221: + .long SYM(_uhoh) | 222: + .long SYM(_uhoh) | 223: + .long SYM(_uhoh) | 224: + .long SYM(_uhoh) | 225: + .long SYM(_uhoh) | 226: + .long SYM(_uhoh) | 227: + .long SYM(_uhoh) | 228: + .long SYM(_uhoh) | 229: + .long SYM(_uhoh) | 230: + .long SYM(_uhoh) | 231: + .long SYM(_uhoh) | 232: + .long SYM(_uhoh) | 233: + .long SYM(_uhoh) | 234: + .long SYM(_uhoh) | 235: + .long SYM(_uhoh) | 236: + .long SYM(_uhoh) | 237: + .long SYM(_uhoh) | 238: + .long SYM(_uhoh) | 239: + .long SYM(_uhoh) | 240: + .long SYM(_uhoh) | 241: + .long SYM(_uhoh) | 242: + .long SYM(_uhoh) | 243: + .long SYM(_uhoh) | 244: + .long SYM(_uhoh) | 245: + .long SYM(_uhoh) | 246: + .long SYM(_uhoh) | 247: + .long SYM(_uhoh) | 248: + .long SYM(_uhoh) | 249: + .long SYM(_uhoh) | 250: + .long SYM(_uhoh) | 251: + .long SYM(_uhoh) | 252: + .long SYM(_uhoh) | 253: + .long SYM(_uhoh) | 254: + .long SYM(_uhoh) | 255: + +/* + * Default trap handler + * With an oscilloscope you can see AS* stop + */ + PUBLIC (_uhoh) +SYM(_uhoh): nop | Leave spot for breakpoint +/* stop #0x2700 | Stop with interrupts disabled */ + move.w #0x2700,sr + move.w (a7),_boot_panic_registers+4 | SR + move.l 2(a7),_boot_panic_registers | PC + move.w 6(a7),_boot_panic_registers+6 | format & vector + movem.l d0-d7/a0-a7, _boot_panic_registers+8 + movec sfc, d0 + movem.l d0, _boot_panic_registers+72 + movec dfc, d0 + movem.l d0, _boot_panic_registers+76 + movec vbr, d0 + movem.l d0, _boot_panic_registers+80 + jmp SYM(_dbug_dumpanic) + bra.s _crt0_cold_start + +/* + * Log, but otherwise ignore, spurious interrupts + */ + PUBLIC (_spuriousInterrupt) +SYM(_spuriousInterrupt): + addql #1,SYM(_M68kSpuriousInterruptCount) + rte + +/* + * Place the low-order 3 octets of the board's ethernet address at + * a `well-known' fixed location relative to the startup location. + */ + .align 2 + .word 0 | Padding +ethernet_address_buffer: + .word 0x08F3 | Default address + .word 0xDEAD + .word 0xCAFE + +BEGIN_DATA + +/* equates */ + +.equ _CPU340, 0x0 +.equ _CPU349, 0x31 + +#ifdef _OLD_ASTECC /* old addresses for AST68340 only */ +.equ _EPLD_CS_BASE, 0x1 +.equ _PROM_Start, 0x01000000 /* CS0 */ +.equ _FLEX_Start, 0x08000000 /* CS2 */ +.equ _I2C_Start, 0x0c000000 /* CS3 */ + +.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */ +.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */ + +.equ _ExtRam_Start, 0x10000000 /* SRAM */ +.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */ + +.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */ +.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */ + +#else /* new addresses for AST68349 and 68340 */ + +.equ _EPLD_CS_BASE, 0x5 +.equ _PROM_Start, 0x50000000 /* CS0 */ +.equ _FLEX_Start, 0x08000000 /* CS2 */ +.equ _I2C_Start, 0x0c000000 /* CS3 */ + +.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */ +.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */ + +.equ _ExtRam_Start, 0x80000000 /* DRAM */ +.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */ + +.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */ +.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */ +#endif + +.equ _SPEED349, 0xD680 /* 24 Mhz */ +.equ _SPEED340, 0xD700 /* 25 Mhz */ +/* .equ _SPEED340, 0xCE00 16 Mhz */ + +#define crt0_boot_type d0 /* cold/warm start (must be D0) */ +#define crt0_temp d1 +#define crt0_cpu_type d2 +#define crt0_csswitch d3 +#define crt0_buswidth d4 +#define crt0_pdcs d5 +#define crt0_spare6 d6 +#define crt0_spare7 d7 +#define crt0_sim_base a0 +#define crt0_glue a1 +#define crt0_dram a2 +#define crt0_ptr3 a3 +#define crt0_ptr4 a4 +#define crt0_ptr5 a5 +#define crt0_ptr6 a6 + +/* -- PDCS buffer equates -- */ +.equ pdcs_mask, 0x1F /* DRAM configuration */ +.equ pdcs_sw12, 7 /* switch 12 */ +.equ pdcs_sw11, 6 /* switch 11 */ +.equ pdcs_sw14, 5 /* switch 14 */ + +.equ bit_cache, pdcs_sw12 /* enable cache if on */ +.equ bit_meminit, pdcs_sw11 /* init memory if on */ + +/* -- Initialization stack and vars -- */ + +_AsteccBusWidth: ds.b 1 +_AsteccCsSwitch: ds.b 1 +_AsteccCpuName: ds.l 1 + +.align 4 + +_crt0_init_stack: + ds.l 500 +_crt0_init_stktop: + +/* -- Initialization code -- */ +BEGIN_CODE + +.align 4 + dc.l _crt0_init_stktop /* reset SP */ + dc.l _crt0_cold_start /* reset PC */ + dc.l _crt0_warm_start + + .ascii "BOOT XHM68K/Spectra for ASTECC 68349 and 68340 boards" + dc.w 0 +.align 4 + +.globl start +start: + +_crt0_cold_start: + moveq.l #0,crt0_boot_type | signal cold reset + bra.s _crt0_common_start + +_crt0_warm_start: + moveq.l #1,crt0_boot_type | signal warm reset + +_crt0_common_start: + move.w #0x2700,sr | disable interrupts and switch to interrupt mode + movea.l #_crt0_init_stktop,sp | set up initialization stack + + move.l #Entry,crt0_temp | VBR initialization + movec.l crt0_temp,vbr | + moveq.l #0x07,crt0_temp + movec.l crt0_temp,dfc | prepare access in CPU space + move.l #(BASE_SIM+0x111),crt0_temp | mask CPU, RESERVED USER SPACES + moves.l crt0_temp,BASE_REG | base initialization (must be MOVES, PCC-130795) + + movea.l #BASE_SIM,crt0_sim_base + + /* -- disable Bus Monitor -- */ + move.b #0,SIM_SYPCR(crt0_sim_base) | system protection control register + + /* -- enable A31-A24 -- */ + clr.b SIM_PPRA1(crt0_sim_base) + + /* -- show cycles, user acces to SIM, 4 /CS & 4 /IT -- */ + move.w #0x427F,SIM_MCR(crt0_sim_base) + + /* -- enable /IRQ3, 5, 6, 7 -- */ + move.b #0xE8,SIM_PPRB(crt0_sim_base) + + /* -- enable autovector on /IRQ7 -- */ + move.b #0x80,SIM_AVR(crt0_sim_base) + + /* -- test CPU type -- */ + cmp.b #_CPU349,SIM_IDR(crt0_sim_base) + bne cpu_is_68340 + +/*-------------------------------------------------------------------------------------------*/ +cpu_is_68349: + + /* -- set cpu clock -- */ + move.w #_SPEED349,SIM_SYNCR(crt0_sim_base) | clock + +sync_wait349: + btst.b #3,(SIM_SYNCR+1)(crt0_sim_base) + beq sync_wait349 + + /* to allow access to the EPLD internal registers, it is necessary + to disable the global chip-select /CS0 (which decodes every external + cycles). To do that, we initialize the 68349 internal RAM, + copy a part of the initialization code in it, and jump there. + from that moment, /CS0 is not used, therefore it can be initialized + with its default value. Its width may be incorrect, but it will be + adjusted later. The goal is to avoid any conflict with + the accesses to the EPLD registers. + When this is done, we read the RESET parameters (boot prom width + and chip-select switch) and proceed with the initialization + when all is done, we jump back to the boot prom now + decoded with a properly configured /CS0 */ + + /*-------------------------------------*/ + /* -- configure internal SRAM banks -- */ + + move.l #0x00000000,QDMM_MCR(crt0_sim_base) + move.l #_FastRam_Start+0x0005,QDMM_QBAR0(crt0_sim_base) + move.l #_FastRam_Start+0x0405,QDMM_QBAR1(crt0_sim_base) + move.l #_FastRam_Start+0x0805,QDMM_QBAR2(crt0_sim_base) + move.l #_FastRam_Start+0x0c05,QDMM_QBAR3(crt0_sim_base) + + /*--------------------------------------------------------*/ + /* -- copy to address of the 68349 initialization code -- */ + + lea.l _copy_start(%pc),crt0_ptr3 + lea.l _copy_end(%pc),crt0_ptr4 + move.l crt0_ptr4,crt0_temp + sub.l crt0_ptr3,crt0_temp + add.l #3,crt0_temp | adjust to next long word + lsr.l #2,crt0_temp + + move.l #_FastRam_Start,crt0_ptr4 +_copy_loop: + move.l (crt0_ptr3)+,(crt0_ptr4)+ + subq.l #1,crt0_temp + bne.s _copy_loop + bra.l _FastRam_Start | jump to code in internal RAM + + /*------------------------------------*/ + /* -- start of initialization code -- */ + +_copy_start: + bra.l _begin_68349_init + + /*----------------------------------------------------------*/ + /* Astecc 68349 board : chip-select initialization values */ + +_table_csepld: + dc.b (_EPLD_CS_BASE&0x0F)+0x80 | 16 bits, 0ws + dc.b 0x80 | 16 bits, 0 ws + dc.b 0x90 | 16 bits, ext /dsack + dc.b 0x90 | 16 bits, ext /dsack + +_table_cs349: + dc.l 0x003FFFF4 | Mask CS0 (4Mbytes PROM, 32bits, 1WS) + dc.l (_PROM_Start&0xFFFFFF00)+0x00000003 | Base CS0 + dc.l 0x003FFFF1 | MASK CS1 (4Mbytes RAM, 16bits, 0WS) + dc.l (_BCCram_Start&0xFFFFFF00)+0x00000003 | Base CS1 + dc.l 0x000000FF | MASK CS2 (FLEX, ext DTACK, 256 bytes) + dc.l (_FLEX_Start&0xFFFFFF00)+0x00000003 | Base CS2 + dc.l 0x000000FF | Mask CS3 (I2C, ext DTACK, 256 bytes) + dc.l (_I2C_Start&0xFFFFFF00)+0x00000003 | Base CS3 + + /*-------------------------------------------------*/ +_begin_68349_init: + + /*-------------------------------------------------*/ + /* 68349 chip select initialization + + at this stage, the width of /CS0 may be incorrect + it will be corrected later + */ + +_cs68349_init: + lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 + lea.l _table_cs349(%pc),crt0_ptr3 + + moveq.l #0x07,crt0_temp +_cs349_init2: + move.l (crt0_ptr3)+,(crt0_ptr4)+ + dbra crt0_temp,_cs349_init2 + + /*-----------------------------------------------*/ + /* -- prepare access to the internal registers --*/ + moveq.l #EPLD_SPACE,crt0_temp + movec.l crt0_temp,dfc + movec.l crt0_temp,sfc + move.l #GLUE_EPLD,crt0_glue + move.l #DRAM_EPLD,crt0_dram + + /*-------------------------------------------*/ + /* EPLD generated /CS[3..0] must be disabled */ + +_csepld_clear: + move.l crt0_glue,crt0_ptr4 + move.w #3,crt0_spare6 + clr.b crt0_temp + +_csepld_clear1: + moves.b crt0_temp,(crt0_ptr4)+ + dbra crt0_spare6,_csepld_clear1 + + /*---------------------------------------------------------*/ + /* -- get width of boot PROM, and active chip-select set --*/ + moves.b REG_BUSWIDTH(crt0_dram),crt0_csswitch + move.b crt0_csswitch,crt0_buswidth + + /* state of CS_SWITCH : sel == 0 => CPU chip_selects (/CS[3..0]) + : sel == 1 => EPLD chip_selects (/CS[3..0]) */ + and.b #1,crt0_csswitch + + /* bus width of /CS0 during reset bw[1..0] : 0 1 2 3 + bus width : 32 16 8 ext./dsackx */ + rol.b #2,crt0_buswidth + and.b #3,crt0_buswidth + + /*----------------------------------------------------*/ + /* -- configure chip select 0 with boot prom width -- */ + lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 + lea.l _table_cs349(%pc),crt0_ptr3 + move.l (crt0_ptr3)+,crt0_temp + and.b #0xFC,crt0_temp | clear PS0 & PS1 + or.b crt0_buswidth,crt0_temp | set boot PROM bus width + move.l crt0_temp,(crt0_ptr4)+ + + /*------------------------*/ + /* -- read PDCS buffer -- */ + moves.b REG_PDCS(crt0_glue),crt0_pdcs +/* move.b #0x3F,crt0_pdcs pour test */ + + + /*---------------------------------------*/ + /* -- EPLD chip-select initialization -- */ + /*---------------------------------------*/ + btst.b #0,crt0_csswitch + beq _cs_init_end + + /*--------------------------------------------*/ + /* 68349 generated /CS[3..0] must be disabled */ + lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 + lea.l _table_cs349(%pc),crt0_ptr3 + moveq.l #0x03,crt0_temp +_cs349_clear: + move.l (crt0_ptr3)+,(crt0_ptr4)+ + move.l (crt0_ptr3)+,crt0_spare6 + and.b #0xFE,crt0_spare6 | disable chip-select + move.l crt0_spare6,(crt0_ptr4)+ + dbra crt0_temp,_cs349_clear + + /*---------------------------------------------*/ + /* EPLD generated /CS[3..0] must be configured */ +_csepld_init: + move.l crt0_glue,crt0_ptr4 + lea.l _table_csepld(%pc),crt0_ptr3 + + move.b (crt0_ptr3)+,crt0_temp + or.b #0x20,crt0_temp | default width is 32 bits + tst.b crt0_buswidth | is boot PROM bus width 32 bits ? + beq _csepld1 | if not + and.b #0xDF,crt0_temp | set width to 16 bits +_csepld1: + moves.b crt0_temp,(crt0_ptr4)+ + + moveq.l #0x02,crt0_spare6 +_csepld2: + move.b (crt0_ptr3)+,crt0_temp + moves.b crt0_temp,(crt0_ptr4)+ + dbra crt0_spare6,_csepld2 + +_cs_init_end: + + /*--------------------------------------*/ + /* -- DRAM controller initialization -- */ +_dram_init: + move.w #15,crt0_temp + move.l #_ExtRam_Start,crt0_ptr3 + +_dram_init1: + clr.l (crt0_ptr3)+ | must access DRAM + dbra crt0_temp,_dram_init1 | prior to init refresh + +_dram_init2: + move.b #3,crt0_temp + moves.b crt0_temp,REG_WS(crt0_dram) | set 3 wait-states + + move.b #0x81,crt0_temp + moves.b crt0_temp,REG_REFRESH(crt0_dram) | refresh every 10µs + + move.b #0,crt0_temp + moves.b crt0_temp,REG_CONFIG(crt0_dram) | default size = 4Mbytes + + /*-----------------------*/ + /* -- configure cache -- */ +_init_cache: + move.l #0x000001E0,CACHE_MCR(crt0_sim_base) + btst.b #bit_cache,crt0_pdcs + bne _init_cache_end + or.l #0x00000001,CACHE_MCR(crt0_sim_base) + +_init_cache_end: + + /*-----------------------------*/ + /* -- timers initialization -- */ + + clr.b crt0_temp + moves.b crt0_temp,REG_TIMER1(crt0_glue) | disable timer 1 + moves.b crt0_temp,REG_TIMER2(crt0_glue) | disable timer 2 + + /*--------------------------*/ + /* -- I2C initialization -- */ + move.b #3,crt0_temp + moves.b crt0_temp,REG_I2C(crt0_glue) | tri-states I2C ports + + /*-----------------------------------------*/ + /* -- baudrate generator initialization -- */ + move.b #2,crt0_temp + moves.b crt0_temp,REG_BAUDRATE(crt0_glue) | baudrate = 38400 + + /*-------------------------------*/ + /* -- IO port initialization -- */ + clr.b crt0_temp + moves.b crt0_temp,REG_IO(crt0_glue) | set port as input + + /* -- */ + + move.l #68349,crt0_cpu_type + + + /* -- jump back to PROM -- */ + + jmp.l (_fill_test) | must be absolute long + +_copy_end: + +/*------------------------------------------------- + initialization code for the 68340 board + -------------------------------------------------*/ + + /* Astecc 68340 board : chip-select initialization values */ +_table_cs340: + dc.l 0x003FFFF0 /* Mask CS0 (4Mbytes PROM, 32bits, 0WS) */ + dc.l ((_PROM_Start&0xFFFFFF00)+0x00000003) /* Base CS0 */ + dc.l 0x0000FFFD /* MASK CS1 (RAMBCC340, 0WS, FTE) */ + dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000003) /* Base CS1 */ + dc.l 0x000000FF /* MASK CS2 (FLEX, ext DTACK, 256 bytes) */ + dc.l ((_FLEX_Start&0xFFFFFF00)+0x00000003) /* Base CS2 */ + dc.l 0x000000FF /* Mask CS3 (I2C, ext DTACK, 256 bytes) */ + dc.l ((_I2C_Start&0xFFFFFF00)+0x00000003) /* Base CS3 */ + +cpu_is_68340: + + /* -- set cpu clock -- */ + move.w #_SPEED340,SIM_SYNCR(crt0_sim_base) | clock +sync_wait340: + btst.b #3,(SIM_SYNCR+1)(crt0_sim_base) + beq sync_wait340 + + /* -- chip select initialization -- */ + lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 + lea.l _table_cs340(%pc),crt0_ptr3 + moveq.l #0x07,crt0_temp +_b_cs340: + move.l (crt0_ptr3)+,crt0_ptr5 + move.l crt0_ptr5,(crt0_ptr4)+ | pour test + dbra crt0_temp,_b_cs340 + + move.l #68340,crt0_cpu_type + move.b #0,crt0_csswitch | CPU + move.b #1,crt0_buswidth | 16 bits + + + /*------------------------------------------------- + fill RAM if COLDSTART + -------------------------------------------------*/ +_fill_test: + + tst.l crt0_boot_type + bne _dont_fill + + cmp.b #_CPU349,SIM_IDR(crt0_sim_base) + bne _fill + btst.b #bit_meminit,crt0_pdcs + bne _dont_fill + + /* fill main memory */ +_fill: + move.l #_crt0_init_stack,crt0_ptr3 | skip Astecc vars + move.l #_ExtRam_Start,crt0_temp + sub.l #_crt0_init_stack,crt0_temp + add.l #_ExtRam_Size,crt0_temp | get size + lsr.l #2,crt0_temp | ajust for long word +_fill_loop: + clr.l (crt0_ptr3)+ + subq.l #1,crt0_temp + bne _fill_loop + + cmp.b #_CPU349,SIM_IDR(crt0_sim_base) + bne _fill_bccram + + /* fill QDMM memory */ + movea.l #_FastRam_Start,crt0_ptr3 | get start + move.l #_FastRam_Size,crt0_temp | get size + lsr.l #2,crt0_temp | ajust for long word + +_QDMMfill_loop: + clr.l (crt0_ptr3)+ + subq.l #1,crt0_temp + bne _QDMMfill_loop + bra _dont_fill + + /* fill BCC memory */ +_fill_bccram: + movea.l #_BCCram_Start,crt0_ptr3 | get start + move.l #_BCCram_Size,crt0_temp | get size + lsr.l #2,crt0_temp | ajust for long word +_BCCfill_loop: + clr.l (crt0_ptr3)+ + subq.l #1,crt0_temp + bne _BCCfill_loop + + *-------------------------------------------------*/ +_dont_fill: + move.b crt0_csswitch,_AsteccCsSwitch + move.b crt0_buswidth,_AsteccBusWidth + move.l crt0_cpu_type,_AsteccCpuName + + jmp SYM(_Init68340) | Start C code (which never returns) + +/* + * Copy DATA segment, clear BSS segment, set up real stack, + * initialize heap, start C program. + * Assume that DATA and BSS sizes are multiples of 4. + */ + PUBLIC (_CopyDataClearBSSAndStart) +SYM(_CopyDataClearBSSAndStart): + lea copy_start,a0 | Get start of DATA in RAM + lea SYM(etext),a2 | Get start of DATA in ROM + cmpl a0,a2 | Are they the same? + beq.s NOCOPY | Yes, no copy necessary + lea copy_end,a1 | Get end of DATA in RAM + bra.s COPYLOOPTEST | Branch into copy loop +COPYLOOP: + movel a2@+,a0@+ | Copy word from ROM to RAM +COPYLOOPTEST: + cmpl a1,a0 | Done? + bcs.s COPYLOOP | No, skip +NOCOPY: + + lea clear_start,a0 | Get start of BSS + lea clear_end,a1 | Get end of BSS + clrl d0 | Value to set + bra.s ZEROLOOPTEST | Branch into clear loop +ZEROLOOP: + movel d0,a0@+ | Clear a word +ZEROLOOPTEST: + cmpl a1,a0 | Done? + bcs.s ZEROLOOP | No, skip + + movel #stack_init,a7 | set master stack pointer + movel d0,a7@- | environp + movel d0,a7@- | argv + movel d0,a7@- | argc + jsr SYM(boot_card) | Call C main + + PUBLIC (_mainDone) +SYM(_mainDone): + nop | Leave spot for breakpoint + movew #1,a7 | Force a double bus error + movel d0,a7@- | This should cause a RESET +/* stop #0x2700 | Stop with interrupts disabled */ + move.w #0x2700,sr + bra.s SYM(_mainDone) | Stuck forever + + .align 2 + PUBLIC (_HeapSize) +SYM (_HeapSize): + .long HeapSize + PUBLIC (_StackSize) +SYM (_StackSize): + .long StackSize +END_CODE + +BEGIN_DATA_DCL + .align 2 + PUBLIC (environ) +SYM (environ): + .long 0 + PUBLIC (_M68kSpuriousInterruptCount) +SYM (_M68kSpuriousInterruptCount): + .long 0 +END_DATA_DCL + +END + diff --git a/c/src/lib/libbsp/m68k/gen68340/start340/start340.s b/c/src/lib/libbsp/m68k/gen68340/start340/start340.s deleted file mode 100644 index 58ea0c92d0..0000000000 --- a/c/src/lib/libbsp/m68k/gen68340/start340/start340.s +++ /dev/null @@ -1,874 +0,0 @@ -/* - * This file contains the entry point for the application. - * The name of this entry point is compiler dependent. - * It jumps to the BSP which is responsible for performing - * all initialization. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may in - * the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * Based on the `gen68360' board support package, and covered by the - * original distribution terms. - * - * Geoffroy Montel - * France Telecom - CNET/DSM/TAM/CAT - * 4, rue du Clos Courtel - * 35512 CESSON-SEVIGNE - * FRANCE - * - * e-mail: g_montel@yahoo.com - * - * $Id$ - */ - -#include "asm.h" -#include - -#define _OLD_ASTECC 1 /* old addresses for AST68340 only, undefine for AST68349 */ - -BEGIN_CODE - /* - * Step 1: Decide on Reset Stack Pointer and Initial Program Counter - */ -Entry: - .long SYM(m340)+1024 | 0: Initial SSP - .long start | 1: Initial PC - .long SYM(_uhoh) | 2: Bus error - .long SYM(_uhoh) | 3: Address error - .long SYM(_uhoh) | 4: Illegal instruction - .long SYM(_uhoh) | 5: Zero division - .long SYM(_uhoh) | 6: CHK, CHK2 instruction - .long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions - .long SYM(_uhoh) | 8: Privilege violation - .long SYM(_uhoh) | 9: Trace - .long SYM(_uhoh) | 10: Line 1010 emulator - .long SYM(_uhoh) | 11: Line 1111 emulator - .long SYM(_uhoh) | 12: Hardware breakpoint - .long SYM(_uhoh) | 13: Reserved for coprocessor violation - .long SYM(_uhoh) | 14: Format error - .long SYM(_uhoh) | 15: Uninitialized interrupt - .long SYM(_uhoh) | 16: Unassigned, reserved - .long SYM(_uhoh) | 17: - .long SYM(_uhoh) | 18: - .long SYM(_uhoh) | 19: - .long SYM(_uhoh) | 20: - .long SYM(_uhoh) | 21: - .long SYM(_uhoh) | 22: - .long SYM(_uhoh) | 23: - .long SYM(_spuriousInterrupt) | 24: Spurious interrupt - .long SYM(_uhoh) | 25: Level 1 interrupt autovector - .long SYM(_uhoh) | 26: Level 2 interrupt autovector - .long SYM(_uhoh) | 27: Level 3 interrupt autovector - .long SYM(_uhoh) | 28: Level 4 interrupt autovector - .long SYM(_uhoh) | 29: Level 5 interrupt autovector - .long SYM(_uhoh) | 30: Level 6 interrupt autovector - .long SYM(_uhoh) | 31: Level 7 interrupt autovector - .long SYM(_uhoh) | 32: Trap instruction (0-15) - .long SYM(_uhoh) | 33: - .long SYM(_uhoh) | 34: - .long SYM(_uhoh) | 35: - .long SYM(_uhoh) | 36: - .long SYM(_uhoh) | 37: - .long SYM(_uhoh) | 38: - .long SYM(_uhoh) | 39: - .long SYM(_uhoh) | 40: - .long SYM(_uhoh) | 41: - .long SYM(_uhoh) | 42: - .long SYM(_uhoh) | 43: - .long SYM(_uhoh) | 44: - .long SYM(_uhoh) | 45: - .long SYM(_uhoh) | 46: - .long SYM(_uhoh) | 47: - .long SYM(_uhoh) | 48: Reserved for coprocessor - .long SYM(_uhoh) | 49: - .long SYM(_uhoh) | 50: - .long SYM(_uhoh) | 51: - .long SYM(_uhoh) | 52: - .long SYM(_uhoh) | 53: - .long SYM(_uhoh) | 54: - .long SYM(_uhoh) | 55: - .long SYM(_uhoh) | 56: - .long SYM(_uhoh) | 57: - .long SYM(_uhoh) | 58: - .long SYM(_uhoh) | 59: Unassigned, reserved - .long SYM(_uhoh) | 60: - .long SYM(_uhoh) | 61: - .long SYM(_uhoh) | 62: - .long SYM(_uhoh) | 63: - .long SYM(_uhoh) | 64: User defined vectors (192) - .long SYM(_uhoh) | 65: - .long SYM(_uhoh) | 66: - .long SYM(_uhoh) | 67: - .long SYM(_uhoh) | 68: - .long SYM(_uhoh) | 69: - .long SYM(_uhoh) | 70: - .long SYM(_uhoh) | 71: - .long SYM(_uhoh) | 72: - .long SYM(_uhoh) | 73: - .long SYM(_uhoh) | 74: - .long SYM(_uhoh) | 75: - .long SYM(_uhoh) | 76: - .long SYM(_uhoh) | 77: - .long SYM(_uhoh) | 78: - .long SYM(_uhoh) | 79: - .long SYM(_uhoh) | 80: - .long SYM(_uhoh) | 81: - .long SYM(_uhoh) | 82: - .long SYM(_uhoh) | 83: - .long SYM(_uhoh) | 84: - .long SYM(_uhoh) | 85: - .long SYM(_uhoh) | 86: - .long SYM(_uhoh) | 87: - .long SYM(_uhoh) | 88: - .long SYM(_uhoh) | 89: - .long SYM(_uhoh) | 90: - .long SYM(_uhoh) | 91: - .long SYM(_uhoh) | 92: - .long SYM(_uhoh) | 93: - .long SYM(_uhoh) | 94: - .long SYM(_uhoh) | 95: - .long SYM(_uhoh) | 96: - .long SYM(_uhoh) | 97: - .long SYM(_uhoh) | 98: - .long SYM(_uhoh) | 99: - .long SYM(_uhoh) | 100: - .long SYM(_uhoh) | 101: - .long SYM(_uhoh) | 102: - .long SYM(_uhoh) | 103: - .long SYM(_uhoh) | 104: - .long SYM(_uhoh) | 105: - .long SYM(_uhoh) | 106: - .long SYM(_uhoh) | 107: - .long SYM(_uhoh) | 108: - .long SYM(_uhoh) | 109: - .long SYM(_uhoh) | 110: - .long SYM(_uhoh) | 111: - .long SYM(_uhoh) | 112: - .long SYM(_uhoh) | 113: - .long SYM(_uhoh) | 114: - .long SYM(_uhoh) | 115: - .long SYM(_uhoh) | 116: - .long SYM(_uhoh) | 117: - .long SYM(_uhoh) | 118: - .long SYM(_uhoh) | 119: - .long SYM(_uhoh) | 120: - .long SYM(_uhoh) | 121: - .long SYM(_uhoh) | 122: - .long SYM(_uhoh) | 123: - .long SYM(_uhoh) | 124: - .long SYM(_uhoh) | 125: - .long SYM(_uhoh) | 126: - .long SYM(_uhoh) | 127: - .long SYM(_uhoh) | 128: - .long SYM(_uhoh) | 129: - .long SYM(_uhoh) | 130: - .long SYM(_uhoh) | 131: - .long SYM(_uhoh) | 132: - .long SYM(_uhoh) | 133: - .long SYM(_uhoh) | 134: - .long SYM(_uhoh) | 135: - .long SYM(_uhoh) | 136: - .long SYM(_uhoh) | 137: - .long SYM(_uhoh) | 138: - .long SYM(_uhoh) | 139: - .long SYM(_uhoh) | 140: - .long SYM(_uhoh) | 141: - .long SYM(_uhoh) | 142: - .long SYM(_uhoh) | 143: - .long SYM(_uhoh) | 144: - .long SYM(_uhoh) | 145: - .long SYM(_uhoh) | 146: - .long SYM(_uhoh) | 147: - .long SYM(_uhoh) | 148: - .long SYM(_uhoh) | 149: - .long SYM(_uhoh) | 150: - .long SYM(_uhoh) | 151: - .long SYM(_uhoh) | 152: - .long SYM(_uhoh) | 153: - .long SYM(_uhoh) | 154: - .long SYM(_uhoh) | 155: - .long SYM(_uhoh) | 156: - .long SYM(_uhoh) | 157: - .long SYM(_uhoh) | 158: - .long SYM(_uhoh) | 159: - .long SYM(_uhoh) | 160: - .long SYM(_uhoh) | 161: - .long SYM(_uhoh) | 162: - .long SYM(_uhoh) | 163: - .long SYM(_uhoh) | 164: - .long SYM(_uhoh) | 165: - .long SYM(_uhoh) | 166: - .long SYM(_uhoh) | 167: - .long SYM(_uhoh) | 168: - .long SYM(_uhoh) | 169: - .long SYM(_uhoh) | 170: - .long SYM(_uhoh) | 171: - .long SYM(_uhoh) | 172: - .long SYM(_uhoh) | 173: - .long SYM(_uhoh) | 174: - .long SYM(_uhoh) | 175: - .long SYM(_uhoh) | 176: - .long SYM(_uhoh) | 177: - .long SYM(_uhoh) | 178: - .long SYM(_uhoh) | 179: - .long SYM(_uhoh) | 180: - .long SYM(_uhoh) | 181: - .long SYM(_uhoh) | 182: - .long SYM(_uhoh) | 183: - .long SYM(_uhoh) | 184: - .long SYM(_uhoh) | 185: - .long SYM(_uhoh) | 186: - .long SYM(_uhoh) | 187: - .long SYM(_uhoh) | 188: - .long SYM(_uhoh) | 189: - .long SYM(_uhoh) | 190: - .long SYM(_uhoh) | 191: - .long SYM(_uhoh) | 192: - .long SYM(_uhoh) | 193: - .long SYM(_uhoh) | 194: - .long SYM(_uhoh) | 195: - .long SYM(_uhoh) | 196: - .long SYM(_uhoh) | 197: - .long SYM(_uhoh) | 198: - .long SYM(_uhoh) | 199: - .long SYM(_uhoh) | 200: - .long SYM(_uhoh) | 201: - .long SYM(_uhoh) | 202: - .long SYM(_uhoh) | 203: - .long SYM(_uhoh) | 204: - .long SYM(_uhoh) | 205: - .long SYM(_uhoh) | 206: - .long SYM(_uhoh) | 207: - .long SYM(_uhoh) | 208: - .long SYM(_uhoh) | 209: - .long SYM(_uhoh) | 210: - .long SYM(_uhoh) | 211: - .long SYM(_uhoh) | 212: - .long SYM(_uhoh) | 213: - .long SYM(_uhoh) | 214: - .long SYM(_uhoh) | 215: - .long SYM(_uhoh) | 216: - .long SYM(_uhoh) | 217: - .long SYM(_uhoh) | 218: - .long SYM(_uhoh) | 219: - .long SYM(_uhoh) | 220: - .long SYM(_uhoh) | 221: - .long SYM(_uhoh) | 222: - .long SYM(_uhoh) | 223: - .long SYM(_uhoh) | 224: - .long SYM(_uhoh) | 225: - .long SYM(_uhoh) | 226: - .long SYM(_uhoh) | 227: - .long SYM(_uhoh) | 228: - .long SYM(_uhoh) | 229: - .long SYM(_uhoh) | 230: - .long SYM(_uhoh) | 231: - .long SYM(_uhoh) | 232: - .long SYM(_uhoh) | 233: - .long SYM(_uhoh) | 234: - .long SYM(_uhoh) | 235: - .long SYM(_uhoh) | 236: - .long SYM(_uhoh) | 237: - .long SYM(_uhoh) | 238: - .long SYM(_uhoh) | 239: - .long SYM(_uhoh) | 240: - .long SYM(_uhoh) | 241: - .long SYM(_uhoh) | 242: - .long SYM(_uhoh) | 243: - .long SYM(_uhoh) | 244: - .long SYM(_uhoh) | 245: - .long SYM(_uhoh) | 246: - .long SYM(_uhoh) | 247: - .long SYM(_uhoh) | 248: - .long SYM(_uhoh) | 249: - .long SYM(_uhoh) | 250: - .long SYM(_uhoh) | 251: - .long SYM(_uhoh) | 252: - .long SYM(_uhoh) | 253: - .long SYM(_uhoh) | 254: - .long SYM(_uhoh) | 255: - -/* - * Default trap handler - * With an oscilloscope you can see AS* stop - */ - PUBLIC (_uhoh) -SYM(_uhoh): nop | Leave spot for breakpoint -/* stop #0x2700 | Stop with interrupts disabled */ - move.w #0x2700,sr - move.w (a7),_boot_panic_registers+4 | SR - move.l 2(a7),_boot_panic_registers | PC - move.w 6(a7),_boot_panic_registers+6 | format & vector - movem.l d0-d7/a0-a7, _boot_panic_registers+8 - movec sfc, d0 - movem.l d0, _boot_panic_registers+72 - movec dfc, d0 - movem.l d0, _boot_panic_registers+76 - movec vbr, d0 - movem.l d0, _boot_panic_registers+80 - jmp SYM(_dbug_dumpanic) - bra.s _crt0_cold_start - -/* - * Log, but otherwise ignore, spurious interrupts - */ - PUBLIC (_spuriousInterrupt) -SYM(_spuriousInterrupt): - addql #1,SYM(_M68kSpuriousInterruptCount) - rte - -/* - * Place the low-order 3 octets of the board's ethernet address at - * a `well-known' fixed location relative to the startup location. - */ - .align 2 - .word 0 | Padding -ethernet_address_buffer: - .word 0x08F3 | Default address - .word 0xDEAD - .word 0xCAFE - -BEGIN_DATA - -/* equates */ - -.equ _CPU340, 0x0 -.equ _CPU349, 0x31 - -#ifdef _OLD_ASTECC /* old addresses for AST68340 only */ -.equ _EPLD_CS_BASE, 0x1 -.equ _PROM_Start, 0x01000000 /* CS0 */ -.equ _FLEX_Start, 0x08000000 /* CS2 */ -.equ _I2C_Start, 0x0c000000 /* CS3 */ - -.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */ -.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */ - -.equ _ExtRam_Start, 0x10000000 /* SRAM */ -.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */ - -.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */ -.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */ - -#else /* new addresses for AST68349 and 68340 */ - -.equ _EPLD_CS_BASE, 0x5 -.equ _PROM_Start, 0x50000000 /* CS0 */ -.equ _FLEX_Start, 0x08000000 /* CS2 */ -.equ _I2C_Start, 0x0c000000 /* CS3 */ - -.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */ -.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */ - -.equ _ExtRam_Start, 0x80000000 /* DRAM */ -.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */ - -.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */ -.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */ -#endif - -.equ _SPEED349, 0xD680 /* 24 Mhz */ -.equ _SPEED340, 0xD700 /* 25 Mhz */ -/* .equ _SPEED340, 0xCE00 16 Mhz */ - -#define crt0_boot_type d0 /* cold/warm start (must be D0) */ -#define crt0_temp d1 -#define crt0_cpu_type d2 -#define crt0_csswitch d3 -#define crt0_buswidth d4 -#define crt0_pdcs d5 -#define crt0_spare6 d6 -#define crt0_spare7 d7 -#define crt0_sim_base a0 -#define crt0_glue a1 -#define crt0_dram a2 -#define crt0_ptr3 a3 -#define crt0_ptr4 a4 -#define crt0_ptr5 a5 -#define crt0_ptr6 a6 - -/* -- PDCS buffer equates -- */ -.equ pdcs_mask, 0x1F /* DRAM configuration */ -.equ pdcs_sw12, 7 /* switch 12 */ -.equ pdcs_sw11, 6 /* switch 11 */ -.equ pdcs_sw14, 5 /* switch 14 */ - -.equ bit_cache, pdcs_sw12 /* enable cache if on */ -.equ bit_meminit, pdcs_sw11 /* init memory if on */ - -/* -- Initialization stack and vars -- */ - -_AsteccBusWidth: ds.b 1 -_AsteccCsSwitch: ds.b 1 -_AsteccCpuName: ds.l 1 - -.align 4 - -_crt0_init_stack: - ds.l 500 -_crt0_init_stktop: - -/* -- Initialization code -- */ -BEGIN_CODE - -.align 4 - dc.l _crt0_init_stktop /* reset SP */ - dc.l _crt0_cold_start /* reset PC */ - dc.l _crt0_warm_start - - .ascii "BOOT XHM68K/Spectra for ASTECC 68349 and 68340 boards" - dc.w 0 -.align 4 - -.globl start -start: - -_crt0_cold_start: - moveq.l #0,crt0_boot_type | signal cold reset - bra.s _crt0_common_start - -_crt0_warm_start: - moveq.l #1,crt0_boot_type | signal warm reset - -_crt0_common_start: - move.w #0x2700,sr | disable interrupts and switch to interrupt mode - movea.l #_crt0_init_stktop,sp | set up initialization stack - - move.l #Entry,crt0_temp | VBR initialization - movec.l crt0_temp,vbr | - moveq.l #0x07,crt0_temp - movec.l crt0_temp,dfc | prepare access in CPU space - move.l #(BASE_SIM+0x111),crt0_temp | mask CPU, RESERVED USER SPACES - moves.l crt0_temp,BASE_REG | base initialization (must be MOVES, PCC-130795) - - movea.l #BASE_SIM,crt0_sim_base - - /* -- disable Bus Monitor -- */ - move.b #0,SIM_SYPCR(crt0_sim_base) | system protection control register - - /* -- enable A31-A24 -- */ - clr.b SIM_PPRA1(crt0_sim_base) - - /* -- show cycles, user acces to SIM, 4 /CS & 4 /IT -- */ - move.w #0x427F,SIM_MCR(crt0_sim_base) - - /* -- enable /IRQ3, 5, 6, 7 -- */ - move.b #0xE8,SIM_PPRB(crt0_sim_base) - - /* -- enable autovector on /IRQ7 -- */ - move.b #0x80,SIM_AVR(crt0_sim_base) - - /* -- test CPU type -- */ - cmp.b #_CPU349,SIM_IDR(crt0_sim_base) - bne cpu_is_68340 - -/*-------------------------------------------------------------------------------------------*/ -cpu_is_68349: - - /* -- set cpu clock -- */ - move.w #_SPEED349,SIM_SYNCR(crt0_sim_base) | clock - -sync_wait349: - btst.b #3,(SIM_SYNCR+1)(crt0_sim_base) - beq sync_wait349 - - /* to allow access to the EPLD internal registers, it is necessary - to disable the global chip-select /CS0 (which decodes every external - cycles). To do that, we initialize the 68349 internal RAM, - copy a part of the initialization code in it, and jump there. - from that moment, /CS0 is not used, therefore it can be initialized - with its default value. Its width may be incorrect, but it will be - adjusted later. The goal is to avoid any conflict with - the accesses to the EPLD registers. - When this is done, we read the RESET parameters (boot prom width - and chip-select switch) and proceed with the initialization - when all is done, we jump back to the boot prom now - decoded with a properly configured /CS0 */ - - /*-------------------------------------*/ - /* -- configure internal SRAM banks -- */ - - move.l #0x00000000,QDMM_MCR(crt0_sim_base) - move.l #_FastRam_Start+0x0005,QDMM_QBAR0(crt0_sim_base) - move.l #_FastRam_Start+0x0405,QDMM_QBAR1(crt0_sim_base) - move.l #_FastRam_Start+0x0805,QDMM_QBAR2(crt0_sim_base) - move.l #_FastRam_Start+0x0c05,QDMM_QBAR3(crt0_sim_base) - - /*--------------------------------------------------------*/ - /* -- copy to address of the 68349 initialization code -- */ - - lea.l _copy_start(%pc),crt0_ptr3 - lea.l _copy_end(%pc),crt0_ptr4 - move.l crt0_ptr4,crt0_temp - sub.l crt0_ptr3,crt0_temp - add.l #3,crt0_temp | adjust to next long word - lsr.l #2,crt0_temp - - move.l #_FastRam_Start,crt0_ptr4 -_copy_loop: - move.l (crt0_ptr3)+,(crt0_ptr4)+ - subq.l #1,crt0_temp - bne.s _copy_loop - bra.l _FastRam_Start | jump to code in internal RAM - - /*------------------------------------*/ - /* -- start of initialization code -- */ - -_copy_start: - bra.l _begin_68349_init - - /*----------------------------------------------------------*/ - /* Astecc 68349 board : chip-select initialization values */ - -_table_csepld: - dc.b (_EPLD_CS_BASE&0x0F)+0x80 | 16 bits, 0ws - dc.b 0x80 | 16 bits, 0 ws - dc.b 0x90 | 16 bits, ext /dsack - dc.b 0x90 | 16 bits, ext /dsack - -_table_cs349: - dc.l 0x003FFFF4 | Mask CS0 (4Mbytes PROM, 32bits, 1WS) - dc.l (_PROM_Start&0xFFFFFF00)+0x00000003 | Base CS0 - dc.l 0x003FFFF1 | MASK CS1 (4Mbytes RAM, 16bits, 0WS) - dc.l (_BCCram_Start&0xFFFFFF00)+0x00000003 | Base CS1 - dc.l 0x000000FF | MASK CS2 (FLEX, ext DTACK, 256 bytes) - dc.l (_FLEX_Start&0xFFFFFF00)+0x00000003 | Base CS2 - dc.l 0x000000FF | Mask CS3 (I2C, ext DTACK, 256 bytes) - dc.l (_I2C_Start&0xFFFFFF00)+0x00000003 | Base CS3 - - /*-------------------------------------------------*/ -_begin_68349_init: - - /*-------------------------------------------------*/ - /* 68349 chip select initialization - - at this stage, the width of /CS0 may be incorrect - it will be corrected later - */ - -_cs68349_init: - lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 - lea.l _table_cs349(%pc),crt0_ptr3 - - moveq.l #0x07,crt0_temp -_cs349_init2: - move.l (crt0_ptr3)+,(crt0_ptr4)+ - dbra crt0_temp,_cs349_init2 - - /*-----------------------------------------------*/ - /* -- prepare access to the internal registers --*/ - moveq.l #EPLD_SPACE,crt0_temp - movec.l crt0_temp,dfc - movec.l crt0_temp,sfc - move.l #GLUE_EPLD,crt0_glue - move.l #DRAM_EPLD,crt0_dram - - /*-------------------------------------------*/ - /* EPLD generated /CS[3..0] must be disabled */ - -_csepld_clear: - move.l crt0_glue,crt0_ptr4 - move.w #3,crt0_spare6 - clr.b crt0_temp - -_csepld_clear1: - moves.b crt0_temp,(crt0_ptr4)+ - dbra crt0_spare6,_csepld_clear1 - - /*---------------------------------------------------------*/ - /* -- get width of boot PROM, and active chip-select set --*/ - moves.b REG_BUSWIDTH(crt0_dram),crt0_csswitch - move.b crt0_csswitch,crt0_buswidth - - /* state of CS_SWITCH : sel == 0 => CPU chip_selects (/CS[3..0]) - : sel == 1 => EPLD chip_selects (/CS[3..0]) */ - and.b #1,crt0_csswitch - - /* bus width of /CS0 during reset bw[1..0] : 0 1 2 3 - bus width : 32 16 8 ext./dsackx */ - rol.b #2,crt0_buswidth - and.b #3,crt0_buswidth - - /*----------------------------------------------------*/ - /* -- configure chip select 0 with boot prom width -- */ - lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 - lea.l _table_cs349(%pc),crt0_ptr3 - move.l (crt0_ptr3)+,crt0_temp - and.b #0xFC,crt0_temp | clear PS0 & PS1 - or.b crt0_buswidth,crt0_temp | set boot PROM bus width - move.l crt0_temp,(crt0_ptr4)+ - - /*------------------------*/ - /* -- read PDCS buffer -- */ - moves.b REG_PDCS(crt0_glue),crt0_pdcs -/* move.b #0x3F,crt0_pdcs pour test */ - - - /*---------------------------------------*/ - /* -- EPLD chip-select initialization -- */ - /*---------------------------------------*/ - btst.b #0,crt0_csswitch - beq _cs_init_end - - /*--------------------------------------------*/ - /* 68349 generated /CS[3..0] must be disabled */ - lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 - lea.l _table_cs349(%pc),crt0_ptr3 - moveq.l #0x03,crt0_temp -_cs349_clear: - move.l (crt0_ptr3)+,(crt0_ptr4)+ - move.l (crt0_ptr3)+,crt0_spare6 - and.b #0xFE,crt0_spare6 | disable chip-select - move.l crt0_spare6,(crt0_ptr4)+ - dbra crt0_temp,_cs349_clear - - /*---------------------------------------------*/ - /* EPLD generated /CS[3..0] must be configured */ -_csepld_init: - move.l crt0_glue,crt0_ptr4 - lea.l _table_csepld(%pc),crt0_ptr3 - - move.b (crt0_ptr3)+,crt0_temp - or.b #0x20,crt0_temp | default width is 32 bits - tst.b crt0_buswidth | is boot PROM bus width 32 bits ? - beq _csepld1 | if not - and.b #0xDF,crt0_temp | set width to 16 bits -_csepld1: - moves.b crt0_temp,(crt0_ptr4)+ - - moveq.l #0x02,crt0_spare6 -_csepld2: - move.b (crt0_ptr3)+,crt0_temp - moves.b crt0_temp,(crt0_ptr4)+ - dbra crt0_spare6,_csepld2 - -_cs_init_end: - - /*--------------------------------------*/ - /* -- DRAM controller initialization -- */ -_dram_init: - move.w #15,crt0_temp - move.l #_ExtRam_Start,crt0_ptr3 - -_dram_init1: - clr.l (crt0_ptr3)+ | must access DRAM - dbra crt0_temp,_dram_init1 | prior to init refresh - -_dram_init2: - move.b #3,crt0_temp - moves.b crt0_temp,REG_WS(crt0_dram) | set 3 wait-states - - move.b #0x81,crt0_temp - moves.b crt0_temp,REG_REFRESH(crt0_dram) | refresh every 10µs - - move.b #0,crt0_temp - moves.b crt0_temp,REG_CONFIG(crt0_dram) | default size = 4Mbytes - - /*-----------------------*/ - /* -- configure cache -- */ -_init_cache: - move.l #0x000001E0,CACHE_MCR(crt0_sim_base) - btst.b #bit_cache,crt0_pdcs - bne _init_cache_end - or.l #0x00000001,CACHE_MCR(crt0_sim_base) - -_init_cache_end: - - /*-----------------------------*/ - /* -- timers initialization -- */ - - clr.b crt0_temp - moves.b crt0_temp,REG_TIMER1(crt0_glue) | disable timer 1 - moves.b crt0_temp,REG_TIMER2(crt0_glue) | disable timer 2 - - /*--------------------------*/ - /* -- I2C initialization -- */ - move.b #3,crt0_temp - moves.b crt0_temp,REG_I2C(crt0_glue) | tri-states I2C ports - - /*-----------------------------------------*/ - /* -- baudrate generator initialization -- */ - move.b #2,crt0_temp - moves.b crt0_temp,REG_BAUDRATE(crt0_glue) | baudrate = 38400 - - /*-------------------------------*/ - /* -- IO port initialization -- */ - clr.b crt0_temp - moves.b crt0_temp,REG_IO(crt0_glue) | set port as input - - /* -- */ - - move.l #68349,crt0_cpu_type - - - /* -- jump back to PROM -- */ - - jmp.l (_fill_test) | must be absolute long - -_copy_end: - -/*------------------------------------------------- - initialization code for the 68340 board - -------------------------------------------------*/ - - /* Astecc 68340 board : chip-select initialization values */ -_table_cs340: - dc.l 0x003FFFF0 /* Mask CS0 (4Mbytes PROM, 32bits, 0WS) */ - dc.l ((_PROM_Start&0xFFFFFF00)+0x00000003) /* Base CS0 */ - dc.l 0x0000FFFD /* MASK CS1 (RAMBCC340, 0WS, FTE) */ - dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000003) /* Base CS1 */ - dc.l 0x000000FF /* MASK CS2 (FLEX, ext DTACK, 256 bytes) */ - dc.l ((_FLEX_Start&0xFFFFFF00)+0x00000003) /* Base CS2 */ - dc.l 0x000000FF /* Mask CS3 (I2C, ext DTACK, 256 bytes) */ - dc.l ((_I2C_Start&0xFFFFFF00)+0x00000003) /* Base CS3 */ - -cpu_is_68340: - - /* -- set cpu clock -- */ - move.w #_SPEED340,SIM_SYNCR(crt0_sim_base) | clock -sync_wait340: - btst.b #3,(SIM_SYNCR+1)(crt0_sim_base) - beq sync_wait340 - - /* -- chip select initialization -- */ - lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4 - lea.l _table_cs340(%pc),crt0_ptr3 - moveq.l #0x07,crt0_temp -_b_cs340: - move.l (crt0_ptr3)+,crt0_ptr5 - move.l crt0_ptr5,(crt0_ptr4)+ | pour test - dbra crt0_temp,_b_cs340 - - move.l #68340,crt0_cpu_type - move.b #0,crt0_csswitch | CPU - move.b #1,crt0_buswidth | 16 bits - - - /*------------------------------------------------- - fill RAM if COLDSTART - -------------------------------------------------*/ -_fill_test: - - tst.l crt0_boot_type - bne _dont_fill - - cmp.b #_CPU349,SIM_IDR(crt0_sim_base) - bne _fill - btst.b #bit_meminit,crt0_pdcs - bne _dont_fill - - /* fill main memory */ -_fill: - move.l #_crt0_init_stack,crt0_ptr3 | skip Astecc vars - move.l #_ExtRam_Start,crt0_temp - sub.l #_crt0_init_stack,crt0_temp - add.l #_ExtRam_Size,crt0_temp | get size - lsr.l #2,crt0_temp | ajust for long word -_fill_loop: - clr.l (crt0_ptr3)+ - subq.l #1,crt0_temp - bne _fill_loop - - cmp.b #_CPU349,SIM_IDR(crt0_sim_base) - bne _fill_bccram - - /* fill QDMM memory */ - movea.l #_FastRam_Start,crt0_ptr3 | get start - move.l #_FastRam_Size,crt0_temp | get size - lsr.l #2,crt0_temp | ajust for long word - -_QDMMfill_loop: - clr.l (crt0_ptr3)+ - subq.l #1,crt0_temp - bne _QDMMfill_loop - bra _dont_fill - - /* fill BCC memory */ -_fill_bccram: - movea.l #_BCCram_Start,crt0_ptr3 | get start - move.l #_BCCram_Size,crt0_temp | get size - lsr.l #2,crt0_temp | ajust for long word -_BCCfill_loop: - clr.l (crt0_ptr3)+ - subq.l #1,crt0_temp - bne _BCCfill_loop - - *-------------------------------------------------*/ -_dont_fill: - move.b crt0_csswitch,_AsteccCsSwitch - move.b crt0_buswidth,_AsteccBusWidth - move.l crt0_cpu_type,_AsteccCpuName - - jmp SYM(_Init68340) | Start C code (which never returns) - -/* - * Copy DATA segment, clear BSS segment, set up real stack, - * initialize heap, start C program. - * Assume that DATA and BSS sizes are multiples of 4. - */ - PUBLIC (_CopyDataClearBSSAndStart) -SYM(_CopyDataClearBSSAndStart): - lea copy_start,a0 | Get start of DATA in RAM - lea SYM(etext),a2 | Get start of DATA in ROM - cmpl a0,a2 | Are they the same? - beq.s NOCOPY | Yes, no copy necessary - lea copy_end,a1 | Get end of DATA in RAM - bra.s COPYLOOPTEST | Branch into copy loop -COPYLOOP: - movel a2@+,a0@+ | Copy word from ROM to RAM -COPYLOOPTEST: - cmpl a1,a0 | Done? - bcs.s COPYLOOP | No, skip -NOCOPY: - - lea clear_start,a0 | Get start of BSS - lea clear_end,a1 | Get end of BSS - clrl d0 | Value to set - bra.s ZEROLOOPTEST | Branch into clear loop -ZEROLOOP: - movel d0,a0@+ | Clear a word -ZEROLOOPTEST: - cmpl a1,a0 | Done? - bcs.s ZEROLOOP | No, skip - - movel #stack_init,a7 | set master stack pointer - movel d0,a7@- | environp - movel d0,a7@- | argv - movel d0,a7@- | argc - jsr SYM(boot_card) | Call C main - - PUBLIC (_mainDone) -SYM(_mainDone): - nop | Leave spot for breakpoint - movew #1,a7 | Force a double bus error - movel d0,a7@- | This should cause a RESET -/* stop #0x2700 | Stop with interrupts disabled */ - move.w #0x2700,sr - bra.s SYM(_mainDone) | Stuck forever - - .align 2 - PUBLIC (_HeapSize) -SYM (_HeapSize): - .long HeapSize - PUBLIC (_StackSize) -SYM (_StackSize): - .long StackSize -END_CODE - -BEGIN_DATA_DCL - .align 2 - PUBLIC (environ) -SYM (environ): - .long 0 - PUBLIC (_M68kSpuriousInterruptCount) -SYM (_M68kSpuriousInterruptCount): - .long 0 -END_DATA_DCL - -END - diff --git a/c/src/lib/libbsp/m68k/gen68340/start340/startfor340only.S b/c/src/lib/libbsp/m68k/gen68340/start340/startfor340only.S new file mode 100644 index 0000000000..930694f02e --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68340/start340/startfor340only.S @@ -0,0 +1,499 @@ +/* + * This file contains the entry point for the application. + * The name of this entry point is compiler dependent. + * It jumps to the BSP which is responsible for performing + * all initialization. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * Based on the `gen68360' board support package, and covered by the + * original distribution terms. + * + * Geoffroy Montel + * France Telecom - CNET/DSM/TAM/CAT + * 4, rue du Clos Courtel + * 35512 CESSON-SEVIGNE + * FRANCE + * + * e-mail: g_montel@yahoo.com + * + * $Id$ + */ + +#include "asm.h" +#include + +BEGIN_CODE + /* + * Step 1: Decide on Reset Stack Pointer and Initial Program Counter + */ +Entry: + .long SYM(m340)+1024 | 0: Initial SSP + .long start | 1: Initial PC + .long SYM(_uhoh) | 2: Bus error + .long SYM(_uhoh) | 3: Address error + .long SYM(_uhoh) | 4: Illegal instruction + .long SYM(_uhoh) | 5: Zero division + .long SYM(_uhoh) | 6: CHK, CHK2 instruction + .long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions + .long SYM(_uhoh) | 8: Privilege violation + .long SYM(_uhoh) | 9: Trace + .long SYM(_uhoh) | 10: Line 1010 emulator + .long SYM(_uhoh) | 11: Line 1111 emulator + .long SYM(_uhoh) | 12: Hardware breakpoint + .long SYM(_uhoh) | 13: Reserved for coprocessor violation + .long SYM(_uhoh) | 14: Format error + .long SYM(_uhoh) | 15: Uninitialized interrupt + .long SYM(_uhoh) | 16: Unassigned, reserved + .long SYM(_uhoh) | 17: + .long SYM(_uhoh) | 18: + .long SYM(_uhoh) | 19: + .long SYM(_uhoh) | 20: + .long SYM(_uhoh) | 21: + .long SYM(_uhoh) | 22: + .long SYM(_uhoh) | 23: + .long SYM(_spuriousInterrupt) | 24: Spurious interrupt + .long SYM(_uhoh) | 25: Level 1 interrupt autovector + .long SYM(_uhoh) | 26: Level 2 interrupt autovector + .long SYM(_uhoh) | 27: Level 3 interrupt autovector + .long SYM(_uhoh) | 28: Level 4 interrupt autovector + .long SYM(_uhoh) | 29: Level 5 interrupt autovector + .long SYM(_uhoh) | 30: Level 6 interrupt autovector + .long SYM(_uhoh) | 31: Level 7 interrupt autovector + .long SYM(_uhoh) | 32: Trap instruction (0-15) + .long SYM(_uhoh) | 33: + .long SYM(_uhoh) | 34: + .long SYM(_uhoh) | 35: + .long SYM(_uhoh) | 36: + .long SYM(_uhoh) | 37: + .long SYM(_uhoh) | 38: + .long SYM(_uhoh) | 39: + .long SYM(_uhoh) | 40: + .long SYM(_uhoh) | 41: + .long SYM(_uhoh) | 42: + .long SYM(_uhoh) | 43: + .long SYM(_uhoh) | 44: + .long SYM(_uhoh) | 45: + .long SYM(_uhoh) | 46: + .long SYM(_uhoh) | 47: + .long SYM(_uhoh) | 48: Reserved for coprocessor + .long SYM(_uhoh) | 49: + .long SYM(_uhoh) | 50: + .long SYM(_uhoh) | 51: + .long SYM(_uhoh) | 52: + .long SYM(_uhoh) | 53: + .long SYM(_uhoh) | 54: + .long SYM(_uhoh) | 55: + .long SYM(_uhoh) | 56: + .long SYM(_uhoh) | 57: + .long SYM(_uhoh) | 58: + .long SYM(_uhoh) | 59: Unassigned, reserved + .long SYM(_uhoh) | 60: + .long SYM(_uhoh) | 61: + .long SYM(_uhoh) | 62: + .long SYM(_uhoh) | 63: + .long SYM(_uhoh) | 64: User defined vectors (192) + .long SYM(_uhoh) | 65: + .long SYM(_uhoh) | 66: + .long SYM(_uhoh) | 67: + .long SYM(_uhoh) | 68: + .long SYM(_uhoh) | 69: + .long SYM(_uhoh) | 70: + .long SYM(_uhoh) | 71: + .long SYM(_uhoh) | 72: + .long SYM(_uhoh) | 73: + .long SYM(_uhoh) | 74: + .long SYM(_uhoh) | 75: + .long SYM(_uhoh) | 76: + .long SYM(_uhoh) | 77: + .long SYM(_uhoh) | 78: + .long SYM(_uhoh) | 79: + .long SYM(_uhoh) | 80: + .long SYM(_uhoh) | 81: + .long SYM(_uhoh) | 82: + .long SYM(_uhoh) | 83: + .long SYM(_uhoh) | 84: + .long SYM(_uhoh) | 85: + .long SYM(_uhoh) | 86: + .long SYM(_uhoh) | 87: + .long SYM(_uhoh) | 88: + .long SYM(_uhoh) | 89: + .long SYM(_uhoh) | 90: + .long SYM(_uhoh) | 91: + .long SYM(_uhoh) | 92: + .long SYM(_uhoh) | 93: + .long SYM(_uhoh) | 94: + .long SYM(_uhoh) | 95: + .long SYM(_uhoh) | 96: + .long SYM(_uhoh) | 97: + .long SYM(_uhoh) | 98: + .long SYM(_uhoh) | 99: + .long SYM(_uhoh) | 100: + .long SYM(_uhoh) | 101: + .long SYM(_uhoh) | 102: + .long SYM(_uhoh) | 103: + .long SYM(_uhoh) | 104: + .long SYM(_uhoh) | 105: + .long SYM(_uhoh) | 106: + .long SYM(_uhoh) | 107: + .long SYM(_uhoh) | 108: + .long SYM(_uhoh) | 109: + .long SYM(_uhoh) | 110: + .long SYM(_uhoh) | 111: + .long SYM(_uhoh) | 112: + .long SYM(_uhoh) | 113: + .long SYM(_uhoh) | 114: + .long SYM(_uhoh) | 115: + .long SYM(_uhoh) | 116: + .long SYM(_uhoh) | 117: + .long SYM(_uhoh) | 118: + .long SYM(_uhoh) | 119: + .long SYM(_uhoh) | 120: + .long SYM(_uhoh) | 121: + .long SYM(_uhoh) | 122: + .long SYM(_uhoh) | 123: + .long SYM(_uhoh) | 124: + .long SYM(_uhoh) | 125: + .long SYM(_uhoh) | 126: + .long SYM(_uhoh) | 127: + .long SYM(_uhoh) | 128: + .long SYM(_uhoh) | 129: + .long SYM(_uhoh) | 130: + .long SYM(_uhoh) | 131: + .long SYM(_uhoh) | 132: + .long SYM(_uhoh) | 133: + .long SYM(_uhoh) | 134: + .long SYM(_uhoh) | 135: + .long SYM(_uhoh) | 136: + .long SYM(_uhoh) | 137: + .long SYM(_uhoh) | 138: + .long SYM(_uhoh) | 139: + .long SYM(_uhoh) | 140: + .long SYM(_uhoh) | 141: + .long SYM(_uhoh) | 142: + .long SYM(_uhoh) | 143: + .long SYM(_uhoh) | 144: + .long SYM(_uhoh) | 145: + .long SYM(_uhoh) | 146: + .long SYM(_uhoh) | 147: + .long SYM(_uhoh) | 148: + .long SYM(_uhoh) | 149: + .long SYM(_uhoh) | 150: + .long SYM(_uhoh) | 151: + .long SYM(_uhoh) | 152: + .long SYM(_uhoh) | 153: + .long SYM(_uhoh) | 154: + .long SYM(_uhoh) | 155: + .long SYM(_uhoh) | 156: + .long SYM(_uhoh) | 157: + .long SYM(_uhoh) | 158: + .long SYM(_uhoh) | 159: + .long SYM(_uhoh) | 160: + .long SYM(_uhoh) | 161: + .long SYM(_uhoh) | 162: + .long SYM(_uhoh) | 163: + .long SYM(_uhoh) | 164: + .long SYM(_uhoh) | 165: + .long SYM(_uhoh) | 166: + .long SYM(_uhoh) | 167: + .long SYM(_uhoh) | 168: + .long SYM(_uhoh) | 169: + .long SYM(_uhoh) | 170: + .long SYM(_uhoh) | 171: + .long SYM(_uhoh) | 172: + .long SYM(_uhoh) | 173: + .long SYM(_uhoh) | 174: + .long SYM(_uhoh) | 175: + .long SYM(_uhoh) | 176: + .long SYM(_uhoh) | 177: + .long SYM(_uhoh) | 178: + .long SYM(_uhoh) | 179: + .long SYM(_uhoh) | 180: + .long SYM(_uhoh) | 181: + .long SYM(_uhoh) | 182: + .long SYM(_uhoh) | 183: + .long SYM(_uhoh) | 184: + .long SYM(_uhoh) | 185: + .long SYM(_uhoh) | 186: + .long SYM(_uhoh) | 187: + .long SYM(_uhoh) | 188: + .long SYM(_uhoh) | 189: + .long SYM(_uhoh) | 190: + .long SYM(_uhoh) | 191: + .long SYM(_uhoh) | 192: + .long SYM(_uhoh) | 193: + .long SYM(_uhoh) | 194: + .long SYM(_uhoh) | 195: + .long SYM(_uhoh) | 196: + .long SYM(_uhoh) | 197: + .long SYM(_uhoh) | 198: + .long SYM(_uhoh) | 199: + .long SYM(_uhoh) | 200: + .long SYM(_uhoh) | 201: + .long SYM(_uhoh) | 202: + .long SYM(_uhoh) | 203: + .long SYM(_uhoh) | 204: + .long SYM(_uhoh) | 205: + .long SYM(_uhoh) | 206: + .long SYM(_uhoh) | 207: + .long SYM(_uhoh) | 208: + .long SYM(_uhoh) | 209: + .long SYM(_uhoh) | 210: + .long SYM(_uhoh) | 211: + .long SYM(_uhoh) | 212: + .long SYM(_uhoh) | 213: + .long SYM(_uhoh) | 214: + .long SYM(_uhoh) | 215: + .long SYM(_uhoh) | 216: + .long SYM(_uhoh) | 217: + .long SYM(_uhoh) | 218: + .long SYM(_uhoh) | 219: + .long SYM(_uhoh) | 220: + .long SYM(_uhoh) | 221: + .long SYM(_uhoh) | 222: + .long SYM(_uhoh) | 223: + .long SYM(_uhoh) | 224: + .long SYM(_uhoh) | 225: + .long SYM(_uhoh) | 226: + .long SYM(_uhoh) | 227: + .long SYM(_uhoh) | 228: + .long SYM(_uhoh) | 229: + .long SYM(_uhoh) | 230: + .long SYM(_uhoh) | 231: + .long SYM(_uhoh) | 232: + .long SYM(_uhoh) | 233: + .long SYM(_uhoh) | 234: + .long SYM(_uhoh) | 235: + .long SYM(_uhoh) | 236: + .long SYM(_uhoh) | 237: + .long SYM(_uhoh) | 238: + .long SYM(_uhoh) | 239: + .long SYM(_uhoh) | 240: + .long SYM(_uhoh) | 241: + .long SYM(_uhoh) | 242: + .long SYM(_uhoh) | 243: + .long SYM(_uhoh) | 244: + .long SYM(_uhoh) | 245: + .long SYM(_uhoh) | 246: + .long SYM(_uhoh) | 247: + .long SYM(_uhoh) | 248: + .long SYM(_uhoh) | 249: + .long SYM(_uhoh) | 250: + .long SYM(_uhoh) | 251: + .long SYM(_uhoh) | 252: + .long SYM(_uhoh) | 253: + .long SYM(_uhoh) | 254: + .long SYM(_uhoh) | 255: + +/* + * Default trap handler + * With an oscilloscope you can see AS* stop + */ + PUBLIC (_uhoh) +SYM(_uhoh): nop | Leave spot for breakpoint + stop #0x2700 | Stop with interrupts disabled + bra.s SYM(_uhoh) | Stuck forever + +/* + * Log, but otherwise ignore, spurious interrupts + */ + PUBLIC (_spuriousInterrupt) +SYM(_spuriousInterrupt): + addql #1,SYM(_M68kSpuriousInterruptCount) + rte + +/* + * Place the low-order 3 octets of the board's ethernet address at + * a `well-known' fixed location relative to the startup location. + */ + .align 2 + .word 0 | Padding +ethernet_address_buffer: + .word 0x08F3 | Default address + .word 0xDEAD + .word 0xCAFE + +/* -- equates -- */ +.equ _PROM_Start, 0x01000000 /* CS0 */ +.equ _BCCram_Start, 0x00000000 /* CS1 */ +.equ _FLEX_Start, 0x08000000 /* CS2 */ +.equ _I2C_Start, 0x02000000 /* CS3 */ +.equ _EXTram_Start, 0x10000000 /* CS4 */ +.equ _EXTram_Size, 0x000400000 /* 4 Mbytes */ +.equ _SPEED, 0xD780 /* 25 Mhz CPU349 */ +/* .equ _SPEED, 0xD700 25 Mhz */ +/* .equ _SPEED, 0xCE00 16 Mhz */ + +BEGIN_DATA + +_crt0_init_stack: + ds.l 0x1000 +_crt0_init_stktop: + + +BEGIN_CODE + dc.l _crt0_init_stktop /* reset SP */ + dc.l _crt0_cold_start /* reset PC */ + dc.l _crt0_warm_start + + .ascii "RTEMS" + dc.w 0 + +.align 2 + +_table_cs: + /* carte Astecc - 68340 */ + dc.l 0x003FFFF0 /* Mask CS0 (4Mbytes PROM, 32bits, 0WS) */ +/* dc.l 0x003FFFFD Mask CS0 (4Mbytes PROM, 16bits, 3WS) */ + dc.l ((_PROM_Start&0xFFFFFF00)+0x00000003) /* Base CS0 */ +/* dc.l 0x0000FFF1 MASK CS1 (RAMBCC340, 0WS, FTE) */ + dc.l 0x0000FFFD /* MASK CS1 (RAMBCC340, 0WS, FTE) */ +/* dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000007) Base CS1 */ + dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000003) /* Base CS1 */ + dc.l 0x000000FF /* MASK CS2 (FLEX, ext DTACK, 256 bytes) */ + dc.l ((_FLEX_Start&0xFFFFFF00)+0x00000003) /* Base CS2 */ + dc.l 0x000000FF /* Mask CS3 (I2C, ext DTACK, 256 bytes) */ + dc.l ((_I2C_Start&0xFFFFFF00)+0x00000003) /* Base CS3 */ + +/* + * Initial PC + */ +.globl start +start: + +_crt0_cold_start: + moveq.l #0,d0 /* signal cold reset */ + bra.s _crt0_common_start + +_crt0_warm_start: + moveq.l #1,d0 /* signal warm reset */ + +_crt0_common_start: + move.w #0x2700,sr /* disable interrupts and switch to interrupt mode */ + movea.l #_crt0_init_stktop,sp /* set up initialization stack */ + + lea Entry,a0 /* Get base of vector table */ + movec a0,vbr /* Set up the VBR */ + + moveq.l #0x07,d1 + movec.l d1,dfc /* prepare access in CPU space */ + move.l #(BASE_SIM+1),d1 + moves.l d1,BASE_REG /* base initialization (must be MOVES, PCC-130795) */ + moveq.l #0x05,d1 + movec.l d1,dfc + + movea.l #BASE_SIM,a0 + + /* -- disable Bus Monitor -- */ + move.b #0,SIM_SYPCR(a0) /* system protection control register */ + + /* -- set frequency to 25.16 Mhz -- */ + move.w #_SPEED,SIM_SYNCR(a0) /* clock */ + +sync_wait: + btst.b #3,(SIM_SYNCR+1)(a0) + beq sync_wait + + /* -- enable A31-A24 -- */ + clr.b SIM_PPRA1(a0) + + /* -- show cycles, user acces to SIM, 4 /CS & 4 /IT -- */ + move.w #0x427F,SIM_MCR(a0) + + /* -- chip select initialization -- */ + lea.l SIM_MASKH0(a0),a2 + lea.l _table_cs(%pc),a1 + + moveq.l #0x07,d1 + +_b_cs: + move.l (a1)+, (a2)+ + dbra d1,_b_cs + + /* fill RAM if COLDSTART */ + tst.l d0 + bne _dont_fill + + movea.l #_EXTram_Start,a0 /* get start */ + move.l #_EXTram_Size,d1 /* get size */ + lsr.l #2,d1 /* ajust for long word */ + +_fill_loop: + clr.l (a0)+ + subq.l #1,d1 + bne _fill_loop + +_dont_fill: + jmp SYM(_Init68340) | Start C code (which never returns) + +/* + * Copy DATA segment, clear BSS segment, set up real stack, + * initialize heap, start C program. + * Assume that DATA and BSS sizes are multiples of 4. + */ + PUBLIC (_CopyDataClearBSSAndStart) +SYM(_CopyDataClearBSSAndStart): + lea copy_start,a0 | Get start of DATA in RAM + lea SYM(etext),a2 | Get start of DATA in ROM + cmpl a0,a2 | Are they the same? + beq.s NOCOPY | Yes, no copy necessary + lea copy_end,a1 | Get end of DATA in RAM + bra.s COPYLOOPTEST | Branch into copy loop +COPYLOOP: + movel a2@+,a0@+ | Copy word from ROM to RAM +COPYLOOPTEST: + cmpl a1,a0 | Done? + bcs.s COPYLOOP | No, skip +NOCOPY: + + lea clear_start,a0 | Get start of BSS + lea clear_end,a1 | Get end of BSS + clrl d0 | Value to set + bra.s ZEROLOOPTEST | Branch into clear loop +ZEROLOOP: + movel d0,a0@+ | Clear a word +ZEROLOOPTEST: + cmpl a1,a0 | Done? + bcs.s ZEROLOOP | No, skip + + movel #stack_init,a7 | set master stack pointer + movel d0,a7@- | environp + movel d0,a7@- | argv + movel d0,a7@- | argc + jsr SYM(boot_card) | Call C main + + PUBLIC (_mainDone) +SYM(_mainDone): + nop | Leave spot for breakpoint + movew #1,a7 | Force a double bus error + movel d0,a7@- | This should cause a RESET + stop #0x2700 | Stop with interrupts disabled + bra.s SYM(_mainDone) | Stuck forever + + .align 2 + PUBLIC (_HeapSize) +SYM (_HeapSize): + .long HeapSize + PUBLIC (_StackSize) +SYM (_StackSize): + .long StackSize +END_CODE + +BEGIN_DATA_DCL + .align 2 + PUBLIC (environ) +SYM (environ): + .long 0 + PUBLIC (_M68kSpuriousInterruptCount) +SYM (_M68kSpuriousInterruptCount): + .long 0 +END_DATA_DCL + +END + diff --git a/c/src/lib/libbsp/m68k/gen68340/start340/startfor340only.s b/c/src/lib/libbsp/m68k/gen68340/start340/startfor340only.s deleted file mode 100644 index 930694f02e..0000000000 --- a/c/src/lib/libbsp/m68k/gen68340/start340/startfor340only.s +++ /dev/null @@ -1,499 +0,0 @@ -/* - * This file contains the entry point for the application. - * The name of this entry point is compiler dependent. - * It jumps to the BSP which is responsible for performing - * all initialization. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may in - * the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * Based on the `gen68360' board support package, and covered by the - * original distribution terms. - * - * Geoffroy Montel - * France Telecom - CNET/DSM/TAM/CAT - * 4, rue du Clos Courtel - * 35512 CESSON-SEVIGNE - * FRANCE - * - * e-mail: g_montel@yahoo.com - * - * $Id$ - */ - -#include "asm.h" -#include - -BEGIN_CODE - /* - * Step 1: Decide on Reset Stack Pointer and Initial Program Counter - */ -Entry: - .long SYM(m340)+1024 | 0: Initial SSP - .long start | 1: Initial PC - .long SYM(_uhoh) | 2: Bus error - .long SYM(_uhoh) | 3: Address error - .long SYM(_uhoh) | 4: Illegal instruction - .long SYM(_uhoh) | 5: Zero division - .long SYM(_uhoh) | 6: CHK, CHK2 instruction - .long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions - .long SYM(_uhoh) | 8: Privilege violation - .long SYM(_uhoh) | 9: Trace - .long SYM(_uhoh) | 10: Line 1010 emulator - .long SYM(_uhoh) | 11: Line 1111 emulator - .long SYM(_uhoh) | 12: Hardware breakpoint - .long SYM(_uhoh) | 13: Reserved for coprocessor violation - .long SYM(_uhoh) | 14: Format error - .long SYM(_uhoh) | 15: Uninitialized interrupt - .long SYM(_uhoh) | 16: Unassigned, reserved - .long SYM(_uhoh) | 17: - .long SYM(_uhoh) | 18: - .long SYM(_uhoh) | 19: - .long SYM(_uhoh) | 20: - .long SYM(_uhoh) | 21: - .long SYM(_uhoh) | 22: - .long SYM(_uhoh) | 23: - .long SYM(_spuriousInterrupt) | 24: Spurious interrupt - .long SYM(_uhoh) | 25: Level 1 interrupt autovector - .long SYM(_uhoh) | 26: Level 2 interrupt autovector - .long SYM(_uhoh) | 27: Level 3 interrupt autovector - .long SYM(_uhoh) | 28: Level 4 interrupt autovector - .long SYM(_uhoh) | 29: Level 5 interrupt autovector - .long SYM(_uhoh) | 30: Level 6 interrupt autovector - .long SYM(_uhoh) | 31: Level 7 interrupt autovector - .long SYM(_uhoh) | 32: Trap instruction (0-15) - .long SYM(_uhoh) | 33: - .long SYM(_uhoh) | 34: - .long SYM(_uhoh) | 35: - .long SYM(_uhoh) | 36: - .long SYM(_uhoh) | 37: - .long SYM(_uhoh) | 38: - .long SYM(_uhoh) | 39: - .long SYM(_uhoh) | 40: - .long SYM(_uhoh) | 41: - .long SYM(_uhoh) | 42: - .long SYM(_uhoh) | 43: - .long SYM(_uhoh) | 44: - .long SYM(_uhoh) | 45: - .long SYM(_uhoh) | 46: - .long SYM(_uhoh) | 47: - .long SYM(_uhoh) | 48: Reserved for coprocessor - .long SYM(_uhoh) | 49: - .long SYM(_uhoh) | 50: - .long SYM(_uhoh) | 51: - .long SYM(_uhoh) | 52: - .long SYM(_uhoh) | 53: - .long SYM(_uhoh) | 54: - .long SYM(_uhoh) | 55: - .long SYM(_uhoh) | 56: - .long SYM(_uhoh) | 57: - .long SYM(_uhoh) | 58: - .long SYM(_uhoh) | 59: Unassigned, reserved - .long SYM(_uhoh) | 60: - .long SYM(_uhoh) | 61: - .long SYM(_uhoh) | 62: - .long SYM(_uhoh) | 63: - .long SYM(_uhoh) | 64: User defined vectors (192) - .long SYM(_uhoh) | 65: - .long SYM(_uhoh) | 66: - .long SYM(_uhoh) | 67: - .long SYM(_uhoh) | 68: - .long SYM(_uhoh) | 69: - .long SYM(_uhoh) | 70: - .long SYM(_uhoh) | 71: - .long SYM(_uhoh) | 72: - .long SYM(_uhoh) | 73: - .long SYM(_uhoh) | 74: - .long SYM(_uhoh) | 75: - .long SYM(_uhoh) | 76: - .long SYM(_uhoh) | 77: - .long SYM(_uhoh) | 78: - .long SYM(_uhoh) | 79: - .long SYM(_uhoh) | 80: - .long SYM(_uhoh) | 81: - .long SYM(_uhoh) | 82: - .long SYM(_uhoh) | 83: - .long SYM(_uhoh) | 84: - .long SYM(_uhoh) | 85: - .long SYM(_uhoh) | 86: - .long SYM(_uhoh) | 87: - .long SYM(_uhoh) | 88: - .long SYM(_uhoh) | 89: - .long SYM(_uhoh) | 90: - .long SYM(_uhoh) | 91: - .long SYM(_uhoh) | 92: - .long SYM(_uhoh) | 93: - .long SYM(_uhoh) | 94: - .long SYM(_uhoh) | 95: - .long SYM(_uhoh) | 96: - .long SYM(_uhoh) | 97: - .long SYM(_uhoh) | 98: - .long SYM(_uhoh) | 99: - .long SYM(_uhoh) | 100: - .long SYM(_uhoh) | 101: - .long SYM(_uhoh) | 102: - .long SYM(_uhoh) | 103: - .long SYM(_uhoh) | 104: - .long SYM(_uhoh) | 105: - .long SYM(_uhoh) | 106: - .long SYM(_uhoh) | 107: - .long SYM(_uhoh) | 108: - .long SYM(_uhoh) | 109: - .long SYM(_uhoh) | 110: - .long SYM(_uhoh) | 111: - .long SYM(_uhoh) | 112: - .long SYM(_uhoh) | 113: - .long SYM(_uhoh) | 114: - .long SYM(_uhoh) | 115: - .long SYM(_uhoh) | 116: - .long SYM(_uhoh) | 117: - .long SYM(_uhoh) | 118: - .long SYM(_uhoh) | 119: - .long SYM(_uhoh) | 120: - .long SYM(_uhoh) | 121: - .long SYM(_uhoh) | 122: - .long SYM(_uhoh) | 123: - .long SYM(_uhoh) | 124: - .long SYM(_uhoh) | 125: - .long SYM(_uhoh) | 126: - .long SYM(_uhoh) | 127: - .long SYM(_uhoh) | 128: - .long SYM(_uhoh) | 129: - .long SYM(_uhoh) | 130: - .long SYM(_uhoh) | 131: - .long SYM(_uhoh) | 132: - .long SYM(_uhoh) | 133: - .long SYM(_uhoh) | 134: - .long SYM(_uhoh) | 135: - .long SYM(_uhoh) | 136: - .long SYM(_uhoh) | 137: - .long SYM(_uhoh) | 138: - .long SYM(_uhoh) | 139: - .long SYM(_uhoh) | 140: - .long SYM(_uhoh) | 141: - .long SYM(_uhoh) | 142: - .long SYM(_uhoh) | 143: - .long SYM(_uhoh) | 144: - .long SYM(_uhoh) | 145: - .long SYM(_uhoh) | 146: - .long SYM(_uhoh) | 147: - .long SYM(_uhoh) | 148: - .long SYM(_uhoh) | 149: - .long SYM(_uhoh) | 150: - .long SYM(_uhoh) | 151: - .long SYM(_uhoh) | 152: - .long SYM(_uhoh) | 153: - .long SYM(_uhoh) | 154: - .long SYM(_uhoh) | 155: - .long SYM(_uhoh) | 156: - .long SYM(_uhoh) | 157: - .long SYM(_uhoh) | 158: - .long SYM(_uhoh) | 159: - .long SYM(_uhoh) | 160: - .long SYM(_uhoh) | 161: - .long SYM(_uhoh) | 162: - .long SYM(_uhoh) | 163: - .long SYM(_uhoh) | 164: - .long SYM(_uhoh) | 165: - .long SYM(_uhoh) | 166: - .long SYM(_uhoh) | 167: - .long SYM(_uhoh) | 168: - .long SYM(_uhoh) | 169: - .long SYM(_uhoh) | 170: - .long SYM(_uhoh) | 171: - .long SYM(_uhoh) | 172: - .long SYM(_uhoh) | 173: - .long SYM(_uhoh) | 174: - .long SYM(_uhoh) | 175: - .long SYM(_uhoh) | 176: - .long SYM(_uhoh) | 177: - .long SYM(_uhoh) | 178: - .long SYM(_uhoh) | 179: - .long SYM(_uhoh) | 180: - .long SYM(_uhoh) | 181: - .long SYM(_uhoh) | 182: - .long SYM(_uhoh) | 183: - .long SYM(_uhoh) | 184: - .long SYM(_uhoh) | 185: - .long SYM(_uhoh) | 186: - .long SYM(_uhoh) | 187: - .long SYM(_uhoh) | 188: - .long SYM(_uhoh) | 189: - .long SYM(_uhoh) | 190: - .long SYM(_uhoh) | 191: - .long SYM(_uhoh) | 192: - .long SYM(_uhoh) | 193: - .long SYM(_uhoh) | 194: - .long SYM(_uhoh) | 195: - .long SYM(_uhoh) | 196: - .long SYM(_uhoh) | 197: - .long SYM(_uhoh) | 198: - .long SYM(_uhoh) | 199: - .long SYM(_uhoh) | 200: - .long SYM(_uhoh) | 201: - .long SYM(_uhoh) | 202: - .long SYM(_uhoh) | 203: - .long SYM(_uhoh) | 204: - .long SYM(_uhoh) | 205: - .long SYM(_uhoh) | 206: - .long SYM(_uhoh) | 207: - .long SYM(_uhoh) | 208: - .long SYM(_uhoh) | 209: - .long SYM(_uhoh) | 210: - .long SYM(_uhoh) | 211: - .long SYM(_uhoh) | 212: - .long SYM(_uhoh) | 213: - .long SYM(_uhoh) | 214: - .long SYM(_uhoh) | 215: - .long SYM(_uhoh) | 216: - .long SYM(_uhoh) | 217: - .long SYM(_uhoh) | 218: - .long SYM(_uhoh) | 219: - .long SYM(_uhoh) | 220: - .long SYM(_uhoh) | 221: - .long SYM(_uhoh) | 222: - .long SYM(_uhoh) | 223: - .long SYM(_uhoh) | 224: - .long SYM(_uhoh) | 225: - .long SYM(_uhoh) | 226: - .long SYM(_uhoh) | 227: - .long SYM(_uhoh) | 228: - .long SYM(_uhoh) | 229: - .long SYM(_uhoh) | 230: - .long SYM(_uhoh) | 231: - .long SYM(_uhoh) | 232: - .long SYM(_uhoh) | 233: - .long SYM(_uhoh) | 234: - .long SYM(_uhoh) | 235: - .long SYM(_uhoh) | 236: - .long SYM(_uhoh) | 237: - .long SYM(_uhoh) | 238: - .long SYM(_uhoh) | 239: - .long SYM(_uhoh) | 240: - .long SYM(_uhoh) | 241: - .long SYM(_uhoh) | 242: - .long SYM(_uhoh) | 243: - .long SYM(_uhoh) | 244: - .long SYM(_uhoh) | 245: - .long SYM(_uhoh) | 246: - .long SYM(_uhoh) | 247: - .long SYM(_uhoh) | 248: - .long SYM(_uhoh) | 249: - .long SYM(_uhoh) | 250: - .long SYM(_uhoh) | 251: - .long SYM(_uhoh) | 252: - .long SYM(_uhoh) | 253: - .long SYM(_uhoh) | 254: - .long SYM(_uhoh) | 255: - -/* - * Default trap handler - * With an oscilloscope you can see AS* stop - */ - PUBLIC (_uhoh) -SYM(_uhoh): nop | Leave spot for breakpoint - stop #0x2700 | Stop with interrupts disabled - bra.s SYM(_uhoh) | Stuck forever - -/* - * Log, but otherwise ignore, spurious interrupts - */ - PUBLIC (_spuriousInterrupt) -SYM(_spuriousInterrupt): - addql #1,SYM(_M68kSpuriousInterruptCount) - rte - -/* - * Place the low-order 3 octets of the board's ethernet address at - * a `well-known' fixed location relative to the startup location. - */ - .align 2 - .word 0 | Padding -ethernet_address_buffer: - .word 0x08F3 | Default address - .word 0xDEAD - .word 0xCAFE - -/* -- equates -- */ -.equ _PROM_Start, 0x01000000 /* CS0 */ -.equ _BCCram_Start, 0x00000000 /* CS1 */ -.equ _FLEX_Start, 0x08000000 /* CS2 */ -.equ _I2C_Start, 0x02000000 /* CS3 */ -.equ _EXTram_Start, 0x10000000 /* CS4 */ -.equ _EXTram_Size, 0x000400000 /* 4 Mbytes */ -.equ _SPEED, 0xD780 /* 25 Mhz CPU349 */ -/* .equ _SPEED, 0xD700 25 Mhz */ -/* .equ _SPEED, 0xCE00 16 Mhz */ - -BEGIN_DATA - -_crt0_init_stack: - ds.l 0x1000 -_crt0_init_stktop: - - -BEGIN_CODE - dc.l _crt0_init_stktop /* reset SP */ - dc.l _crt0_cold_start /* reset PC */ - dc.l _crt0_warm_start - - .ascii "RTEMS" - dc.w 0 - -.align 2 - -_table_cs: - /* carte Astecc - 68340 */ - dc.l 0x003FFFF0 /* Mask CS0 (4Mbytes PROM, 32bits, 0WS) */ -/* dc.l 0x003FFFFD Mask CS0 (4Mbytes PROM, 16bits, 3WS) */ - dc.l ((_PROM_Start&0xFFFFFF00)+0x00000003) /* Base CS0 */ -/* dc.l 0x0000FFF1 MASK CS1 (RAMBCC340, 0WS, FTE) */ - dc.l 0x0000FFFD /* MASK CS1 (RAMBCC340, 0WS, FTE) */ -/* dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000007) Base CS1 */ - dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000003) /* Base CS1 */ - dc.l 0x000000FF /* MASK CS2 (FLEX, ext DTACK, 256 bytes) */ - dc.l ((_FLEX_Start&0xFFFFFF00)+0x00000003) /* Base CS2 */ - dc.l 0x000000FF /* Mask CS3 (I2C, ext DTACK, 256 bytes) */ - dc.l ((_I2C_Start&0xFFFFFF00)+0x00000003) /* Base CS3 */ - -/* - * Initial PC - */ -.globl start -start: - -_crt0_cold_start: - moveq.l #0,d0 /* signal cold reset */ - bra.s _crt0_common_start - -_crt0_warm_start: - moveq.l #1,d0 /* signal warm reset */ - -_crt0_common_start: - move.w #0x2700,sr /* disable interrupts and switch to interrupt mode */ - movea.l #_crt0_init_stktop,sp /* set up initialization stack */ - - lea Entry,a0 /* Get base of vector table */ - movec a0,vbr /* Set up the VBR */ - - moveq.l #0x07,d1 - movec.l d1,dfc /* prepare access in CPU space */ - move.l #(BASE_SIM+1),d1 - moves.l d1,BASE_REG /* base initialization (must be MOVES, PCC-130795) */ - moveq.l #0x05,d1 - movec.l d1,dfc - - movea.l #BASE_SIM,a0 - - /* -- disable Bus Monitor -- */ - move.b #0,SIM_SYPCR(a0) /* system protection control register */ - - /* -- set frequency to 25.16 Mhz -- */ - move.w #_SPEED,SIM_SYNCR(a0) /* clock */ - -sync_wait: - btst.b #3,(SIM_SYNCR+1)(a0) - beq sync_wait - - /* -- enable A31-A24 -- */ - clr.b SIM_PPRA1(a0) - - /* -- show cycles, user acces to SIM, 4 /CS & 4 /IT -- */ - move.w #0x427F,SIM_MCR(a0) - - /* -- chip select initialization -- */ - lea.l SIM_MASKH0(a0),a2 - lea.l _table_cs(%pc),a1 - - moveq.l #0x07,d1 - -_b_cs: - move.l (a1)+, (a2)+ - dbra d1,_b_cs - - /* fill RAM if COLDSTART */ - tst.l d0 - bne _dont_fill - - movea.l #_EXTram_Start,a0 /* get start */ - move.l #_EXTram_Size,d1 /* get size */ - lsr.l #2,d1 /* ajust for long word */ - -_fill_loop: - clr.l (a0)+ - subq.l #1,d1 - bne _fill_loop - -_dont_fill: - jmp SYM(_Init68340) | Start C code (which never returns) - -/* - * Copy DATA segment, clear BSS segment, set up real stack, - * initialize heap, start C program. - * Assume that DATA and BSS sizes are multiples of 4. - */ - PUBLIC (_CopyDataClearBSSAndStart) -SYM(_CopyDataClearBSSAndStart): - lea copy_start,a0 | Get start of DATA in RAM - lea SYM(etext),a2 | Get start of DATA in ROM - cmpl a0,a2 | Are they the same? - beq.s NOCOPY | Yes, no copy necessary - lea copy_end,a1 | Get end of DATA in RAM - bra.s COPYLOOPTEST | Branch into copy loop -COPYLOOP: - movel a2@+,a0@+ | Copy word from ROM to RAM -COPYLOOPTEST: - cmpl a1,a0 | Done? - bcs.s COPYLOOP | No, skip -NOCOPY: - - lea clear_start,a0 | Get start of BSS - lea clear_end,a1 | Get end of BSS - clrl d0 | Value to set - bra.s ZEROLOOPTEST | Branch into clear loop -ZEROLOOP: - movel d0,a0@+ | Clear a word -ZEROLOOPTEST: - cmpl a1,a0 | Done? - bcs.s ZEROLOOP | No, skip - - movel #stack_init,a7 | set master stack pointer - movel d0,a7@- | environp - movel d0,a7@- | argv - movel d0,a7@- | argc - jsr SYM(boot_card) | Call C main - - PUBLIC (_mainDone) -SYM(_mainDone): - nop | Leave spot for breakpoint - movew #1,a7 | Force a double bus error - movel d0,a7@- | This should cause a RESET - stop #0x2700 | Stop with interrupts disabled - bra.s SYM(_mainDone) | Stuck forever - - .align 2 - PUBLIC (_HeapSize) -SYM (_HeapSize): - .long HeapSize - PUBLIC (_StackSize) -SYM (_StackSize): - .long StackSize -END_CODE - -BEGIN_DATA_DCL - .align 2 - PUBLIC (environ) -SYM (environ): - .long 0 - PUBLIC (_M68kSpuriousInterruptCount) -SYM (_M68kSpuriousInterruptCount): - .long 0 -END_DATA_DCL - -END - diff --git a/c/src/lib/libbsp/m68k/gen68360/start/Makefile.in b/c/src/lib/libbsp/m68k/gen68360/start/Makefile.in index 4d339f46fc..25c914ea5a 100644 --- a/c/src/lib/libbsp/m68k/gen68360/start/Makefile.in +++ b/c/src/lib/libbsp/m68k/gen68360/start/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=start360 -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/m68k/gen68360/start/start.S b/c/src/lib/libbsp/m68k/gen68360/start/start.S new file mode 100644 index 0000000000..2c979e294f --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68360/start/start.S @@ -0,0 +1,432 @@ +/* + * + * This file contains the entry point for the application. + * The name of this entry point is compiler dependent. + * It jumps to the BSP which is responsible for performing + * all initialization. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * Based on the `gen68302' board support package, and covered by the + * original distribution terms. + * + * W. Eric Norum + * Saskatchewan Accelerator Laboratory + * University of Saskatchewan + * Saskatoon, Saskatchewan, CANADA + * eric@skatter.usask.ca + * + * $Id$ + */ + +#include "asm.h" + +BEGIN_CODE + /* + * Step 1: Decide on Reset Stack Pointer and Initial Program Counter + */ +Entry: + .long SYM(m360)+1024 | 0: Initial SSP + .long start | 1: Initial PC + .long SYM(_uhoh) | 2: Bus error + .long SYM(_uhoh) | 3: Address error + .long SYM(_uhoh) | 4: Illegal instruction + .long SYM(_uhoh) | 5: Zero division + .long SYM(_uhoh) | 6: CHK, CHK2 instruction + .long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions + .long SYM(_uhoh) | 8: Privilege violation + .long SYM(_uhoh) | 9: Trace + .long SYM(_uhoh) | 10: Line 1010 emulator + .long SYM(_uhoh) | 11: Line 1111 emulator + .long SYM(_uhoh) | 12: Hardware breakpoint + .long SYM(_uhoh) | 13: Reserved for coprocessor violation + .long SYM(_uhoh) | 14: Format error + .long SYM(_uhoh) | 15: Uninitialized interrupt + .long SYM(_uhoh) | 16: Unassigned, reserved + .long SYM(_uhoh) | 17: + .long SYM(_uhoh) | 18: + .long SYM(_uhoh) | 19: + .long SYM(_uhoh) | 20: + .long SYM(_uhoh) | 21: + .long SYM(_uhoh) | 22: + .long SYM(_uhoh) | 23: + .long SYM(_spuriousInterrupt) | 24: Spurious interrupt + .long SYM(_uhoh) | 25: Level 1 interrupt autovector + .long SYM(_uhoh) | 26: Level 2 interrupt autovector + .long SYM(_uhoh) | 27: Level 3 interrupt autovector + .long SYM(_uhoh) | 28: Level 4 interrupt autovector + .long SYM(_uhoh) | 29: Level 5 interrupt autovector + .long SYM(_uhoh) | 30: Level 6 interrupt autovector + .long SYM(_uhoh) | 31: Level 7 interrupt autovector + .long SYM(_uhoh) | 32: Trap instruction (0-15) + .long SYM(_uhoh) | 33: + .long SYM(_uhoh) | 34: + .long SYM(_uhoh) | 35: + .long SYM(_uhoh) | 36: + .long SYM(_uhoh) | 37: + .long SYM(_uhoh) | 38: + .long SYM(_uhoh) | 39: + .long SYM(_uhoh) | 40: + .long SYM(_uhoh) | 41: + .long SYM(_uhoh) | 42: + .long SYM(_uhoh) | 43: + .long SYM(_uhoh) | 44: + .long SYM(_uhoh) | 45: + .long SYM(_uhoh) | 46: + .long SYM(_uhoh) | 47: + .long SYM(_uhoh) | 48: Reserved for coprocessor + .long SYM(_uhoh) | 49: + .long SYM(_uhoh) | 50: + .long SYM(_uhoh) | 51: + .long SYM(_uhoh) | 52: + .long SYM(_uhoh) | 53: + .long SYM(_uhoh) | 54: + .long SYM(_uhoh) | 55: + .long SYM(_uhoh) | 56: + .long SYM(_uhoh) | 57: + .long SYM(_uhoh) | 58: + .long SYM(_uhoh) | 59: Unassigned, reserved + .long SYM(_uhoh) | 60: + .long SYM(_uhoh) | 61: + .long SYM(_uhoh) | 62: + .long SYM(_uhoh) | 63: + .long SYM(_uhoh) | 64: User defined vectors (192) + .long SYM(_uhoh) | 65: + .long SYM(_uhoh) | 66: + .long SYM(_uhoh) | 67: + .long SYM(_uhoh) | 68: + .long SYM(_uhoh) | 69: + .long SYM(_uhoh) | 70: + .long SYM(_uhoh) | 71: + .long SYM(_uhoh) | 72: + .long SYM(_uhoh) | 73: + .long SYM(_uhoh) | 74: + .long SYM(_uhoh) | 75: + .long SYM(_uhoh) | 76: + .long SYM(_uhoh) | 77: + .long SYM(_uhoh) | 78: + .long SYM(_uhoh) | 79: + .long SYM(_uhoh) | 80: + .long SYM(_uhoh) | 81: + .long SYM(_uhoh) | 82: + .long SYM(_uhoh) | 83: + .long SYM(_uhoh) | 84: + .long SYM(_uhoh) | 85: + .long SYM(_uhoh) | 86: + .long SYM(_uhoh) | 87: + .long SYM(_uhoh) | 88: + .long SYM(_uhoh) | 89: + .long SYM(_uhoh) | 90: + .long SYM(_uhoh) | 91: + .long SYM(_uhoh) | 92: + .long SYM(_uhoh) | 93: + .long SYM(_uhoh) | 94: + .long SYM(_uhoh) | 95: + .long SYM(_uhoh) | 96: + .long SYM(_uhoh) | 97: + .long SYM(_uhoh) | 98: + .long SYM(_uhoh) | 99: + .long SYM(_uhoh) | 100: + .long SYM(_uhoh) | 101: + .long SYM(_uhoh) | 102: + .long SYM(_uhoh) | 103: + .long SYM(_uhoh) | 104: + .long SYM(_uhoh) | 105: + .long SYM(_uhoh) | 106: + .long SYM(_uhoh) | 107: + .long SYM(_uhoh) | 108: + .long SYM(_uhoh) | 109: + .long SYM(_uhoh) | 110: + .long SYM(_uhoh) | 111: + .long SYM(_uhoh) | 112: + .long SYM(_uhoh) | 113: + .long SYM(_uhoh) | 114: + .long SYM(_uhoh) | 115: + .long SYM(_uhoh) | 116: + .long SYM(_uhoh) | 117: + .long SYM(_uhoh) | 118: + .long SYM(_uhoh) | 119: + .long SYM(_uhoh) | 120: + .long SYM(_uhoh) | 121: + .long SYM(_uhoh) | 122: + .long SYM(_uhoh) | 123: + .long SYM(_uhoh) | 124: + .long SYM(_uhoh) | 125: + .long SYM(_uhoh) | 126: + .long SYM(_uhoh) | 127: + .long SYM(_uhoh) | 128: + .long SYM(_uhoh) | 129: + .long SYM(_uhoh) | 130: + .long SYM(_uhoh) | 131: + .long SYM(_uhoh) | 132: + .long SYM(_uhoh) | 133: + .long SYM(_uhoh) | 134: + .long SYM(_uhoh) | 135: + .long SYM(_uhoh) | 136: + .long SYM(_uhoh) | 137: + .long SYM(_uhoh) | 138: + .long SYM(_uhoh) | 139: + .long SYM(_uhoh) | 140: + .long SYM(_uhoh) | 141: + .long SYM(_uhoh) | 142: + .long SYM(_uhoh) | 143: + .long SYM(_uhoh) | 144: + .long SYM(_uhoh) | 145: + .long SYM(_uhoh) | 146: + .long SYM(_uhoh) | 147: + .long SYM(_uhoh) | 148: + .long SYM(_uhoh) | 149: + .long SYM(_uhoh) | 150: + .long SYM(_uhoh) | 151: + .long SYM(_uhoh) | 152: + .long SYM(_uhoh) | 153: + .long SYM(_uhoh) | 154: + .long SYM(_uhoh) | 155: + .long SYM(_uhoh) | 156: + .long SYM(_uhoh) | 157: + .long SYM(_uhoh) | 158: + .long SYM(_uhoh) | 159: + .long SYM(_uhoh) | 160: + .long SYM(_uhoh) | 161: + .long SYM(_uhoh) | 162: + .long SYM(_uhoh) | 163: + .long SYM(_uhoh) | 164: + .long SYM(_uhoh) | 165: + .long SYM(_uhoh) | 166: + .long SYM(_uhoh) | 167: + .long SYM(_uhoh) | 168: + .long SYM(_uhoh) | 169: + .long SYM(_uhoh) | 170: + .long SYM(_uhoh) | 171: + .long SYM(_uhoh) | 172: + .long SYM(_uhoh) | 173: + .long SYM(_uhoh) | 174: + .long SYM(_uhoh) | 175: + .long SYM(_uhoh) | 176: + .long SYM(_uhoh) | 177: + .long SYM(_uhoh) | 178: + .long SYM(_uhoh) | 179: + .long SYM(_uhoh) | 180: + .long SYM(_uhoh) | 181: + .long SYM(_uhoh) | 182: + .long SYM(_uhoh) | 183: + .long SYM(_uhoh) | 184: + .long SYM(_uhoh) | 185: + .long SYM(_uhoh) | 186: + .long SYM(_uhoh) | 187: + .long SYM(_uhoh) | 188: + .long SYM(_uhoh) | 189: + .long SYM(_uhoh) | 190: + .long SYM(_uhoh) | 191: + .long SYM(_uhoh) | 192: + .long SYM(_uhoh) | 193: + .long SYM(_uhoh) | 194: + .long SYM(_uhoh) | 195: + .long SYM(_uhoh) | 196: + .long SYM(_uhoh) | 197: + .long SYM(_uhoh) | 198: + .long SYM(_uhoh) | 199: + .long SYM(_uhoh) | 200: + .long SYM(_uhoh) | 201: + .long SYM(_uhoh) | 202: + .long SYM(_uhoh) | 203: + .long SYM(_uhoh) | 204: + .long SYM(_uhoh) | 205: + .long SYM(_uhoh) | 206: + .long SYM(_uhoh) | 207: + .long SYM(_uhoh) | 208: + .long SYM(_uhoh) | 209: + .long SYM(_uhoh) | 210: + .long SYM(_uhoh) | 211: + .long SYM(_uhoh) | 212: + .long SYM(_uhoh) | 213: + .long SYM(_uhoh) | 214: + .long SYM(_uhoh) | 215: + .long SYM(_uhoh) | 216: + .long SYM(_uhoh) | 217: + .long SYM(_uhoh) | 218: + .long SYM(_uhoh) | 219: + .long SYM(_uhoh) | 220: + .long SYM(_uhoh) | 221: + .long SYM(_uhoh) | 222: + .long SYM(_uhoh) | 223: + .long SYM(_uhoh) | 224: + .long SYM(_uhoh) | 225: + .long SYM(_uhoh) | 226: + .long SYM(_uhoh) | 227: + .long SYM(_uhoh) | 228: + .long SYM(_uhoh) | 229: + .long SYM(_uhoh) | 230: + .long SYM(_uhoh) | 231: + .long SYM(_uhoh) | 232: + .long SYM(_uhoh) | 233: + .long SYM(_uhoh) | 234: + .long SYM(_uhoh) | 235: + .long SYM(_uhoh) | 236: + .long SYM(_uhoh) | 237: + .long SYM(_uhoh) | 238: + .long SYM(_uhoh) | 239: + .long SYM(_uhoh) | 240: + .long SYM(_uhoh) | 241: + .long SYM(_uhoh) | 242: + .long SYM(_uhoh) | 243: + .long SYM(_uhoh) | 244: + .long SYM(_uhoh) | 245: + .long SYM(_uhoh) | 246: + .long SYM(_uhoh) | 247: + .long SYM(_uhoh) | 248: + .long SYM(_uhoh) | 249: + .long SYM(_uhoh) | 250: + .long SYM(_uhoh) | 251: + .long SYM(_uhoh) | 252: + .long SYM(_uhoh) | 253: + .long SYM(_uhoh) | 254: + .long SYM(_uhoh) | 255: + +/* + * Default trap handler + * With an oscilloscope you can see AS* stop + */ + PUBLIC (_uhoh) +SYM(_uhoh): nop | Leave spot for breakpoint + stop #0x2700 | Stop with interrupts disabled + bra.s SYM(_uhoh) | Stuck forever + +/* + * Log, but otherwise ignore, spurious interrupts + */ + PUBLIC (_spuriousInterrupt) +SYM(_spuriousInterrupt): + addql #1,SYM(_M68kSpuriousInterruptCount) + rte + +/* + * Place the low-order 3 octets of the board's ethernet address at + * a `well-known' fixed location relative to the startup location. + */ + .align 2 + .word 0 | Padding +ethernet_address_buffer: + .word 0x08F3 | Default address + .word 0xDEAD + .word 0xCAFE + +/* + * Initial PC + */ +.globl start +start: + /* + * Step 2: Stay in Supervisor Mode + */ +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) + oriw #0x3000,sr | Switch to Master Stack Pointer + lea SYM(m360)+1024-64,a7 | Put stack in dual-port ram + | a little below the interrupt stack +#endif + + /* + * Step 3: Write the VBR + */ + lea Entry,a0 | Get base of vector table + movec a0,vbr | Set up the VBR + + /* + * Step 4: Write the MBAR + */ + movec dfc,d1 | Save destination register + moveq #7,d0 | CPU-space funcction code + movec d0,dfc | Set destination function code register + movel #SYM(m360)+0x101,d0 | MBAR value (mask CPU space accesses) + movesl d0,0x3FF00 | Set MBAR + movec d1,dfc | Restore destination register + + /* + * Step 5: Verify a dual-port RAM location + */ + lea SYM(m360),a0 | Point a0 to first DPRAM location + moveb #0x33,d0 | Set the test value + moveb d0,a0@ | Set the memory location + cmpb a0@,d0 | Does it read back? + bne SYM(_uhoh) | If not, bad news! + notb d0 | Flip bits + moveb d0,a0@ | Set the memory location + cmpb a0@,d0 | Does it read back? + bne SYM(_uhoh) | If not, bad news! + + /* + * Remaining steps are handled by C code + */ + jmp SYM(_Init68360) | Start C code (which never returns) + +/* + * Copy DATA segment, clear BSS segment, set up real stack, + * initialize heap, start C program. + * Assume that DATA and BSS sizes are multiples of 4. + */ + PUBLIC (_CopyDataClearBSSAndStart) +SYM(_CopyDataClearBSSAndStart): + lea copy_start,a0 | Get start of DATA in RAM + lea SYM(etext),a2 | Get start of DATA in ROM + cmpl a0,a2 | Are they the same? + beq.s NOCOPY | Yes, no copy necessary + lea copy_end,a1 | Get end of DATA in RAM + bra.s COPYLOOPTEST | Branch into copy loop +COPYLOOP: + movel a2@+,a0@+ | Copy word from ROM to RAM +COPYLOOPTEST: + cmpl a1,a0 | Done? + bcs.s COPYLOOP | No, skip +NOCOPY: + + lea clear_start,a0 | Get start of BSS + lea clear_end,a1 | Get end of BSS + clrl d0 | Value to set + bra.s ZEROLOOPTEST | Branch into clear loop +ZEROLOOP: + movel d0,a0@+ | Clear a word +ZEROLOOPTEST: + cmpl a1,a0 | Done? + bcs.s ZEROLOOP | No, skip + + movel #stack_init,a7 | set master stack pointer + movel d0,a7@- | environp + movel d0,a7@- | argv + movel d0,a7@- | argc + jsr SYM(boot_card) | Call C main + + PUBLIC (_mainDone) +SYM(_mainDone): + nop | Leave spot for breakpoint + movew #1,a7 | Force a double bus error + movel d0,a7@- | This should cause a RESET + stop #0x2700 | Stop with interrupts disabled + bra.s SYM(_mainDone) | Stuck forever + + .align 2 + PUBLIC (_HeapSize) +SYM (_HeapSize): + .long HeapSize + PUBLIC (_StackSize) +SYM (_StackSize): + .long StackSize +END_CODE + +BEGIN_DATA_DCL + .align 2 + PUBLIC (environ) +SYM (environ): + .long 0 + PUBLIC (_M68kSpuriousInterruptCount) +SYM (_M68kSpuriousInterruptCount): + .long 0 +END_DATA_DCL + +END + diff --git a/c/src/lib/libbsp/m68k/gen68360/start/start360.s b/c/src/lib/libbsp/m68k/gen68360/start/start360.s deleted file mode 100644 index 2c979e294f..0000000000 --- a/c/src/lib/libbsp/m68k/gen68360/start/start360.s +++ /dev/null @@ -1,432 +0,0 @@ -/* - * - * This file contains the entry point for the application. - * The name of this entry point is compiler dependent. - * It jumps to the BSP which is responsible for performing - * all initialization. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may in - * the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * Based on the `gen68302' board support package, and covered by the - * original distribution terms. - * - * W. Eric Norum - * Saskatchewan Accelerator Laboratory - * University of Saskatchewan - * Saskatoon, Saskatchewan, CANADA - * eric@skatter.usask.ca - * - * $Id$ - */ - -#include "asm.h" - -BEGIN_CODE - /* - * Step 1: Decide on Reset Stack Pointer and Initial Program Counter - */ -Entry: - .long SYM(m360)+1024 | 0: Initial SSP - .long start | 1: Initial PC - .long SYM(_uhoh) | 2: Bus error - .long SYM(_uhoh) | 3: Address error - .long SYM(_uhoh) | 4: Illegal instruction - .long SYM(_uhoh) | 5: Zero division - .long SYM(_uhoh) | 6: CHK, CHK2 instruction - .long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions - .long SYM(_uhoh) | 8: Privilege violation - .long SYM(_uhoh) | 9: Trace - .long SYM(_uhoh) | 10: Line 1010 emulator - .long SYM(_uhoh) | 11: Line 1111 emulator - .long SYM(_uhoh) | 12: Hardware breakpoint - .long SYM(_uhoh) | 13: Reserved for coprocessor violation - .long SYM(_uhoh) | 14: Format error - .long SYM(_uhoh) | 15: Uninitialized interrupt - .long SYM(_uhoh) | 16: Unassigned, reserved - .long SYM(_uhoh) | 17: - .long SYM(_uhoh) | 18: - .long SYM(_uhoh) | 19: - .long SYM(_uhoh) | 20: - .long SYM(_uhoh) | 21: - .long SYM(_uhoh) | 22: - .long SYM(_uhoh) | 23: - .long SYM(_spuriousInterrupt) | 24: Spurious interrupt - .long SYM(_uhoh) | 25: Level 1 interrupt autovector - .long SYM(_uhoh) | 26: Level 2 interrupt autovector - .long SYM(_uhoh) | 27: Level 3 interrupt autovector - .long SYM(_uhoh) | 28: Level 4 interrupt autovector - .long SYM(_uhoh) | 29: Level 5 interrupt autovector - .long SYM(_uhoh) | 30: Level 6 interrupt autovector - .long SYM(_uhoh) | 31: Level 7 interrupt autovector - .long SYM(_uhoh) | 32: Trap instruction (0-15) - .long SYM(_uhoh) | 33: - .long SYM(_uhoh) | 34: - .long SYM(_uhoh) | 35: - .long SYM(_uhoh) | 36: - .long SYM(_uhoh) | 37: - .long SYM(_uhoh) | 38: - .long SYM(_uhoh) | 39: - .long SYM(_uhoh) | 40: - .long SYM(_uhoh) | 41: - .long SYM(_uhoh) | 42: - .long SYM(_uhoh) | 43: - .long SYM(_uhoh) | 44: - .long SYM(_uhoh) | 45: - .long SYM(_uhoh) | 46: - .long SYM(_uhoh) | 47: - .long SYM(_uhoh) | 48: Reserved for coprocessor - .long SYM(_uhoh) | 49: - .long SYM(_uhoh) | 50: - .long SYM(_uhoh) | 51: - .long SYM(_uhoh) | 52: - .long SYM(_uhoh) | 53: - .long SYM(_uhoh) | 54: - .long SYM(_uhoh) | 55: - .long SYM(_uhoh) | 56: - .long SYM(_uhoh) | 57: - .long SYM(_uhoh) | 58: - .long SYM(_uhoh) | 59: Unassigned, reserved - .long SYM(_uhoh) | 60: - .long SYM(_uhoh) | 61: - .long SYM(_uhoh) | 62: - .long SYM(_uhoh) | 63: - .long SYM(_uhoh) | 64: User defined vectors (192) - .long SYM(_uhoh) | 65: - .long SYM(_uhoh) | 66: - .long SYM(_uhoh) | 67: - .long SYM(_uhoh) | 68: - .long SYM(_uhoh) | 69: - .long SYM(_uhoh) | 70: - .long SYM(_uhoh) | 71: - .long SYM(_uhoh) | 72: - .long SYM(_uhoh) | 73: - .long SYM(_uhoh) | 74: - .long SYM(_uhoh) | 75: - .long SYM(_uhoh) | 76: - .long SYM(_uhoh) | 77: - .long SYM(_uhoh) | 78: - .long SYM(_uhoh) | 79: - .long SYM(_uhoh) | 80: - .long SYM(_uhoh) | 81: - .long SYM(_uhoh) | 82: - .long SYM(_uhoh) | 83: - .long SYM(_uhoh) | 84: - .long SYM(_uhoh) | 85: - .long SYM(_uhoh) | 86: - .long SYM(_uhoh) | 87: - .long SYM(_uhoh) | 88: - .long SYM(_uhoh) | 89: - .long SYM(_uhoh) | 90: - .long SYM(_uhoh) | 91: - .long SYM(_uhoh) | 92: - .long SYM(_uhoh) | 93: - .long SYM(_uhoh) | 94: - .long SYM(_uhoh) | 95: - .long SYM(_uhoh) | 96: - .long SYM(_uhoh) | 97: - .long SYM(_uhoh) | 98: - .long SYM(_uhoh) | 99: - .long SYM(_uhoh) | 100: - .long SYM(_uhoh) | 101: - .long SYM(_uhoh) | 102: - .long SYM(_uhoh) | 103: - .long SYM(_uhoh) | 104: - .long SYM(_uhoh) | 105: - .long SYM(_uhoh) | 106: - .long SYM(_uhoh) | 107: - .long SYM(_uhoh) | 108: - .long SYM(_uhoh) | 109: - .long SYM(_uhoh) | 110: - .long SYM(_uhoh) | 111: - .long SYM(_uhoh) | 112: - .long SYM(_uhoh) | 113: - .long SYM(_uhoh) | 114: - .long SYM(_uhoh) | 115: - .long SYM(_uhoh) | 116: - .long SYM(_uhoh) | 117: - .long SYM(_uhoh) | 118: - .long SYM(_uhoh) | 119: - .long SYM(_uhoh) | 120: - .long SYM(_uhoh) | 121: - .long SYM(_uhoh) | 122: - .long SYM(_uhoh) | 123: - .long SYM(_uhoh) | 124: - .long SYM(_uhoh) | 125: - .long SYM(_uhoh) | 126: - .long SYM(_uhoh) | 127: - .long SYM(_uhoh) | 128: - .long SYM(_uhoh) | 129: - .long SYM(_uhoh) | 130: - .long SYM(_uhoh) | 131: - .long SYM(_uhoh) | 132: - .long SYM(_uhoh) | 133: - .long SYM(_uhoh) | 134: - .long SYM(_uhoh) | 135: - .long SYM(_uhoh) | 136: - .long SYM(_uhoh) | 137: - .long SYM(_uhoh) | 138: - .long SYM(_uhoh) | 139: - .long SYM(_uhoh) | 140: - .long SYM(_uhoh) | 141: - .long SYM(_uhoh) | 142: - .long SYM(_uhoh) | 143: - .long SYM(_uhoh) | 144: - .long SYM(_uhoh) | 145: - .long SYM(_uhoh) | 146: - .long SYM(_uhoh) | 147: - .long SYM(_uhoh) | 148: - .long SYM(_uhoh) | 149: - .long SYM(_uhoh) | 150: - .long SYM(_uhoh) | 151: - .long SYM(_uhoh) | 152: - .long SYM(_uhoh) | 153: - .long SYM(_uhoh) | 154: - .long SYM(_uhoh) | 155: - .long SYM(_uhoh) | 156: - .long SYM(_uhoh) | 157: - .long SYM(_uhoh) | 158: - .long SYM(_uhoh) | 159: - .long SYM(_uhoh) | 160: - .long SYM(_uhoh) | 161: - .long SYM(_uhoh) | 162: - .long SYM(_uhoh) | 163: - .long SYM(_uhoh) | 164: - .long SYM(_uhoh) | 165: - .long SYM(_uhoh) | 166: - .long SYM(_uhoh) | 167: - .long SYM(_uhoh) | 168: - .long SYM(_uhoh) | 169: - .long SYM(_uhoh) | 170: - .long SYM(_uhoh) | 171: - .long SYM(_uhoh) | 172: - .long SYM(_uhoh) | 173: - .long SYM(_uhoh) | 174: - .long SYM(_uhoh) | 175: - .long SYM(_uhoh) | 176: - .long SYM(_uhoh) | 177: - .long SYM(_uhoh) | 178: - .long SYM(_uhoh) | 179: - .long SYM(_uhoh) | 180: - .long SYM(_uhoh) | 181: - .long SYM(_uhoh) | 182: - .long SYM(_uhoh) | 183: - .long SYM(_uhoh) | 184: - .long SYM(_uhoh) | 185: - .long SYM(_uhoh) | 186: - .long SYM(_uhoh) | 187: - .long SYM(_uhoh) | 188: - .long SYM(_uhoh) | 189: - .long SYM(_uhoh) | 190: - .long SYM(_uhoh) | 191: - .long SYM(_uhoh) | 192: - .long SYM(_uhoh) | 193: - .long SYM(_uhoh) | 194: - .long SYM(_uhoh) | 195: - .long SYM(_uhoh) | 196: - .long SYM(_uhoh) | 197: - .long SYM(_uhoh) | 198: - .long SYM(_uhoh) | 199: - .long SYM(_uhoh) | 200: - .long SYM(_uhoh) | 201: - .long SYM(_uhoh) | 202: - .long SYM(_uhoh) | 203: - .long SYM(_uhoh) | 204: - .long SYM(_uhoh) | 205: - .long SYM(_uhoh) | 206: - .long SYM(_uhoh) | 207: - .long SYM(_uhoh) | 208: - .long SYM(_uhoh) | 209: - .long SYM(_uhoh) | 210: - .long SYM(_uhoh) | 211: - .long SYM(_uhoh) | 212: - .long SYM(_uhoh) | 213: - .long SYM(_uhoh) | 214: - .long SYM(_uhoh) | 215: - .long SYM(_uhoh) | 216: - .long SYM(_uhoh) | 217: - .long SYM(_uhoh) | 218: - .long SYM(_uhoh) | 219: - .long SYM(_uhoh) | 220: - .long SYM(_uhoh) | 221: - .long SYM(_uhoh) | 222: - .long SYM(_uhoh) | 223: - .long SYM(_uhoh) | 224: - .long SYM(_uhoh) | 225: - .long SYM(_uhoh) | 226: - .long SYM(_uhoh) | 227: - .long SYM(_uhoh) | 228: - .long SYM(_uhoh) | 229: - .long SYM(_uhoh) | 230: - .long SYM(_uhoh) | 231: - .long SYM(_uhoh) | 232: - .long SYM(_uhoh) | 233: - .long SYM(_uhoh) | 234: - .long SYM(_uhoh) | 235: - .long SYM(_uhoh) | 236: - .long SYM(_uhoh) | 237: - .long SYM(_uhoh) | 238: - .long SYM(_uhoh) | 239: - .long SYM(_uhoh) | 240: - .long SYM(_uhoh) | 241: - .long SYM(_uhoh) | 242: - .long SYM(_uhoh) | 243: - .long SYM(_uhoh) | 244: - .long SYM(_uhoh) | 245: - .long SYM(_uhoh) | 246: - .long SYM(_uhoh) | 247: - .long SYM(_uhoh) | 248: - .long SYM(_uhoh) | 249: - .long SYM(_uhoh) | 250: - .long SYM(_uhoh) | 251: - .long SYM(_uhoh) | 252: - .long SYM(_uhoh) | 253: - .long SYM(_uhoh) | 254: - .long SYM(_uhoh) | 255: - -/* - * Default trap handler - * With an oscilloscope you can see AS* stop - */ - PUBLIC (_uhoh) -SYM(_uhoh): nop | Leave spot for breakpoint - stop #0x2700 | Stop with interrupts disabled - bra.s SYM(_uhoh) | Stuck forever - -/* - * Log, but otherwise ignore, spurious interrupts - */ - PUBLIC (_spuriousInterrupt) -SYM(_spuriousInterrupt): - addql #1,SYM(_M68kSpuriousInterruptCount) - rte - -/* - * Place the low-order 3 octets of the board's ethernet address at - * a `well-known' fixed location relative to the startup location. - */ - .align 2 - .word 0 | Padding -ethernet_address_buffer: - .word 0x08F3 | Default address - .word 0xDEAD - .word 0xCAFE - -/* - * Initial PC - */ -.globl start -start: - /* - * Step 2: Stay in Supervisor Mode - */ -#if ( M68K_HAS_SEPARATE_STACKS == 1 ) - oriw #0x3000,sr | Switch to Master Stack Pointer - lea SYM(m360)+1024-64,a7 | Put stack in dual-port ram - | a little below the interrupt stack -#endif - - /* - * Step 3: Write the VBR - */ - lea Entry,a0 | Get base of vector table - movec a0,vbr | Set up the VBR - - /* - * Step 4: Write the MBAR - */ - movec dfc,d1 | Save destination register - moveq #7,d0 | CPU-space funcction code - movec d0,dfc | Set destination function code register - movel #SYM(m360)+0x101,d0 | MBAR value (mask CPU space accesses) - movesl d0,0x3FF00 | Set MBAR - movec d1,dfc | Restore destination register - - /* - * Step 5: Verify a dual-port RAM location - */ - lea SYM(m360),a0 | Point a0 to first DPRAM location - moveb #0x33,d0 | Set the test value - moveb d0,a0@ | Set the memory location - cmpb a0@,d0 | Does it read back? - bne SYM(_uhoh) | If not, bad news! - notb d0 | Flip bits - moveb d0,a0@ | Set the memory location - cmpb a0@,d0 | Does it read back? - bne SYM(_uhoh) | If not, bad news! - - /* - * Remaining steps are handled by C code - */ - jmp SYM(_Init68360) | Start C code (which never returns) - -/* - * Copy DATA segment, clear BSS segment, set up real stack, - * initialize heap, start C program. - * Assume that DATA and BSS sizes are multiples of 4. - */ - PUBLIC (_CopyDataClearBSSAndStart) -SYM(_CopyDataClearBSSAndStart): - lea copy_start,a0 | Get start of DATA in RAM - lea SYM(etext),a2 | Get start of DATA in ROM - cmpl a0,a2 | Are they the same? - beq.s NOCOPY | Yes, no copy necessary - lea copy_end,a1 | Get end of DATA in RAM - bra.s COPYLOOPTEST | Branch into copy loop -COPYLOOP: - movel a2@+,a0@+ | Copy word from ROM to RAM -COPYLOOPTEST: - cmpl a1,a0 | Done? - bcs.s COPYLOOP | No, skip -NOCOPY: - - lea clear_start,a0 | Get start of BSS - lea clear_end,a1 | Get end of BSS - clrl d0 | Value to set - bra.s ZEROLOOPTEST | Branch into clear loop -ZEROLOOP: - movel d0,a0@+ | Clear a word -ZEROLOOPTEST: - cmpl a1,a0 | Done? - bcs.s ZEROLOOP | No, skip - - movel #stack_init,a7 | set master stack pointer - movel d0,a7@- | environp - movel d0,a7@- | argv - movel d0,a7@- | argc - jsr SYM(boot_card) | Call C main - - PUBLIC (_mainDone) -SYM(_mainDone): - nop | Leave spot for breakpoint - movew #1,a7 | Force a double bus error - movel d0,a7@- | This should cause a RESET - stop #0x2700 | Stop with interrupts disabled - bra.s SYM(_mainDone) | Stuck forever - - .align 2 - PUBLIC (_HeapSize) -SYM (_HeapSize): - .long HeapSize - PUBLIC (_StackSize) -SYM (_StackSize): - .long StackSize -END_CODE - -BEGIN_DATA_DCL - .align 2 - PUBLIC (environ) -SYM (environ): - .long 0 - PUBLIC (_M68kSpuriousInterruptCount) -SYM (_M68kSpuriousInterruptCount): - .long 0 -END_DATA_DCL - -END - diff --git a/c/src/lib/libbsp/m68k/gen68360/start360/Makefile.in b/c/src/lib/libbsp/m68k/gen68360/start360/Makefile.in index 4d339f46fc..25c914ea5a 100644 --- a/c/src/lib/libbsp/m68k/gen68360/start360/Makefile.in +++ b/c/src/lib/libbsp/m68k/gen68360/start360/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=start360 -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/m68k/gen68360/start360/start360.S b/c/src/lib/libbsp/m68k/gen68360/start360/start360.S new file mode 100644 index 0000000000..2c979e294f --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68360/start360/start360.S @@ -0,0 +1,432 @@ +/* + * + * This file contains the entry point for the application. + * The name of this entry point is compiler dependent. + * It jumps to the BSP which is responsible for performing + * all initialization. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * Based on the `gen68302' board support package, and covered by the + * original distribution terms. + * + * W. Eric Norum + * Saskatchewan Accelerator Laboratory + * University of Saskatchewan + * Saskatoon, Saskatchewan, CANADA + * eric@skatter.usask.ca + * + * $Id$ + */ + +#include "asm.h" + +BEGIN_CODE + /* + * Step 1: Decide on Reset Stack Pointer and Initial Program Counter + */ +Entry: + .long SYM(m360)+1024 | 0: Initial SSP + .long start | 1: Initial PC + .long SYM(_uhoh) | 2: Bus error + .long SYM(_uhoh) | 3: Address error + .long SYM(_uhoh) | 4: Illegal instruction + .long SYM(_uhoh) | 5: Zero division + .long SYM(_uhoh) | 6: CHK, CHK2 instruction + .long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions + .long SYM(_uhoh) | 8: Privilege violation + .long SYM(_uhoh) | 9: Trace + .long SYM(_uhoh) | 10: Line 1010 emulator + .long SYM(_uhoh) | 11: Line 1111 emulator + .long SYM(_uhoh) | 12: Hardware breakpoint + .long SYM(_uhoh) | 13: Reserved for coprocessor violation + .long SYM(_uhoh) | 14: Format error + .long SYM(_uhoh) | 15: Uninitialized interrupt + .long SYM(_uhoh) | 16: Unassigned, reserved + .long SYM(_uhoh) | 17: + .long SYM(_uhoh) | 18: + .long SYM(_uhoh) | 19: + .long SYM(_uhoh) | 20: + .long SYM(_uhoh) | 21: + .long SYM(_uhoh) | 22: + .long SYM(_uhoh) | 23: + .long SYM(_spuriousInterrupt) | 24: Spurious interrupt + .long SYM(_uhoh) | 25: Level 1 interrupt autovector + .long SYM(_uhoh) | 26: Level 2 interrupt autovector + .long SYM(_uhoh) | 27: Level 3 interrupt autovector + .long SYM(_uhoh) | 28: Level 4 interrupt autovector + .long SYM(_uhoh) | 29: Level 5 interrupt autovector + .long SYM(_uhoh) | 30: Level 6 interrupt autovector + .long SYM(_uhoh) | 31: Level 7 interrupt autovector + .long SYM(_uhoh) | 32: Trap instruction (0-15) + .long SYM(_uhoh) | 33: + .long SYM(_uhoh) | 34: + .long SYM(_uhoh) | 35: + .long SYM(_uhoh) | 36: + .long SYM(_uhoh) | 37: + .long SYM(_uhoh) | 38: + .long SYM(_uhoh) | 39: + .long SYM(_uhoh) | 40: + .long SYM(_uhoh) | 41: + .long SYM(_uhoh) | 42: + .long SYM(_uhoh) | 43: + .long SYM(_uhoh) | 44: + .long SYM(_uhoh) | 45: + .long SYM(_uhoh) | 46: + .long SYM(_uhoh) | 47: + .long SYM(_uhoh) | 48: Reserved for coprocessor + .long SYM(_uhoh) | 49: + .long SYM(_uhoh) | 50: + .long SYM(_uhoh) | 51: + .long SYM(_uhoh) | 52: + .long SYM(_uhoh) | 53: + .long SYM(_uhoh) | 54: + .long SYM(_uhoh) | 55: + .long SYM(_uhoh) | 56: + .long SYM(_uhoh) | 57: + .long SYM(_uhoh) | 58: + .long SYM(_uhoh) | 59: Unassigned, reserved + .long SYM(_uhoh) | 60: + .long SYM(_uhoh) | 61: + .long SYM(_uhoh) | 62: + .long SYM(_uhoh) | 63: + .long SYM(_uhoh) | 64: User defined vectors (192) + .long SYM(_uhoh) | 65: + .long SYM(_uhoh) | 66: + .long SYM(_uhoh) | 67: + .long SYM(_uhoh) | 68: + .long SYM(_uhoh) | 69: + .long SYM(_uhoh) | 70: + .long SYM(_uhoh) | 71: + .long SYM(_uhoh) | 72: + .long SYM(_uhoh) | 73: + .long SYM(_uhoh) | 74: + .long SYM(_uhoh) | 75: + .long SYM(_uhoh) | 76: + .long SYM(_uhoh) | 77: + .long SYM(_uhoh) | 78: + .long SYM(_uhoh) | 79: + .long SYM(_uhoh) | 80: + .long SYM(_uhoh) | 81: + .long SYM(_uhoh) | 82: + .long SYM(_uhoh) | 83: + .long SYM(_uhoh) | 84: + .long SYM(_uhoh) | 85: + .long SYM(_uhoh) | 86: + .long SYM(_uhoh) | 87: + .long SYM(_uhoh) | 88: + .long SYM(_uhoh) | 89: + .long SYM(_uhoh) | 90: + .long SYM(_uhoh) | 91: + .long SYM(_uhoh) | 92: + .long SYM(_uhoh) | 93: + .long SYM(_uhoh) | 94: + .long SYM(_uhoh) | 95: + .long SYM(_uhoh) | 96: + .long SYM(_uhoh) | 97: + .long SYM(_uhoh) | 98: + .long SYM(_uhoh) | 99: + .long SYM(_uhoh) | 100: + .long SYM(_uhoh) | 101: + .long SYM(_uhoh) | 102: + .long SYM(_uhoh) | 103: + .long SYM(_uhoh) | 104: + .long SYM(_uhoh) | 105: + .long SYM(_uhoh) | 106: + .long SYM(_uhoh) | 107: + .long SYM(_uhoh) | 108: + .long SYM(_uhoh) | 109: + .long SYM(_uhoh) | 110: + .long SYM(_uhoh) | 111: + .long SYM(_uhoh) | 112: + .long SYM(_uhoh) | 113: + .long SYM(_uhoh) | 114: + .long SYM(_uhoh) | 115: + .long SYM(_uhoh) | 116: + .long SYM(_uhoh) | 117: + .long SYM(_uhoh) | 118: + .long SYM(_uhoh) | 119: + .long SYM(_uhoh) | 120: + .long SYM(_uhoh) | 121: + .long SYM(_uhoh) | 122: + .long SYM(_uhoh) | 123: + .long SYM(_uhoh) | 124: + .long SYM(_uhoh) | 125: + .long SYM(_uhoh) | 126: + .long SYM(_uhoh) | 127: + .long SYM(_uhoh) | 128: + .long SYM(_uhoh) | 129: + .long SYM(_uhoh) | 130: + .long SYM(_uhoh) | 131: + .long SYM(_uhoh) | 132: + .long SYM(_uhoh) | 133: + .long SYM(_uhoh) | 134: + .long SYM(_uhoh) | 135: + .long SYM(_uhoh) | 136: + .long SYM(_uhoh) | 137: + .long SYM(_uhoh) | 138: + .long SYM(_uhoh) | 139: + .long SYM(_uhoh) | 140: + .long SYM(_uhoh) | 141: + .long SYM(_uhoh) | 142: + .long SYM(_uhoh) | 143: + .long SYM(_uhoh) | 144: + .long SYM(_uhoh) | 145: + .long SYM(_uhoh) | 146: + .long SYM(_uhoh) | 147: + .long SYM(_uhoh) | 148: + .long SYM(_uhoh) | 149: + .long SYM(_uhoh) | 150: + .long SYM(_uhoh) | 151: + .long SYM(_uhoh) | 152: + .long SYM(_uhoh) | 153: + .long SYM(_uhoh) | 154: + .long SYM(_uhoh) | 155: + .long SYM(_uhoh) | 156: + .long SYM(_uhoh) | 157: + .long SYM(_uhoh) | 158: + .long SYM(_uhoh) | 159: + .long SYM(_uhoh) | 160: + .long SYM(_uhoh) | 161: + .long SYM(_uhoh) | 162: + .long SYM(_uhoh) | 163: + .long SYM(_uhoh) | 164: + .long SYM(_uhoh) | 165: + .long SYM(_uhoh) | 166: + .long SYM(_uhoh) | 167: + .long SYM(_uhoh) | 168: + .long SYM(_uhoh) | 169: + .long SYM(_uhoh) | 170: + .long SYM(_uhoh) | 171: + .long SYM(_uhoh) | 172: + .long SYM(_uhoh) | 173: + .long SYM(_uhoh) | 174: + .long SYM(_uhoh) | 175: + .long SYM(_uhoh) | 176: + .long SYM(_uhoh) | 177: + .long SYM(_uhoh) | 178: + .long SYM(_uhoh) | 179: + .long SYM(_uhoh) | 180: + .long SYM(_uhoh) | 181: + .long SYM(_uhoh) | 182: + .long SYM(_uhoh) | 183: + .long SYM(_uhoh) | 184: + .long SYM(_uhoh) | 185: + .long SYM(_uhoh) | 186: + .long SYM(_uhoh) | 187: + .long SYM(_uhoh) | 188: + .long SYM(_uhoh) | 189: + .long SYM(_uhoh) | 190: + .long SYM(_uhoh) | 191: + .long SYM(_uhoh) | 192: + .long SYM(_uhoh) | 193: + .long SYM(_uhoh) | 194: + .long SYM(_uhoh) | 195: + .long SYM(_uhoh) | 196: + .long SYM(_uhoh) | 197: + .long SYM(_uhoh) | 198: + .long SYM(_uhoh) | 199: + .long SYM(_uhoh) | 200: + .long SYM(_uhoh) | 201: + .long SYM(_uhoh) | 202: + .long SYM(_uhoh) | 203: + .long SYM(_uhoh) | 204: + .long SYM(_uhoh) | 205: + .long SYM(_uhoh) | 206: + .long SYM(_uhoh) | 207: + .long SYM(_uhoh) | 208: + .long SYM(_uhoh) | 209: + .long SYM(_uhoh) | 210: + .long SYM(_uhoh) | 211: + .long SYM(_uhoh) | 212: + .long SYM(_uhoh) | 213: + .long SYM(_uhoh) | 214: + .long SYM(_uhoh) | 215: + .long SYM(_uhoh) | 216: + .long SYM(_uhoh) | 217: + .long SYM(_uhoh) | 218: + .long SYM(_uhoh) | 219: + .long SYM(_uhoh) | 220: + .long SYM(_uhoh) | 221: + .long SYM(_uhoh) | 222: + .long SYM(_uhoh) | 223: + .long SYM(_uhoh) | 224: + .long SYM(_uhoh) | 225: + .long SYM(_uhoh) | 226: + .long SYM(_uhoh) | 227: + .long SYM(_uhoh) | 228: + .long SYM(_uhoh) | 229: + .long SYM(_uhoh) | 230: + .long SYM(_uhoh) | 231: + .long SYM(_uhoh) | 232: + .long SYM(_uhoh) | 233: + .long SYM(_uhoh) | 234: + .long SYM(_uhoh) | 235: + .long SYM(_uhoh) | 236: + .long SYM(_uhoh) | 237: + .long SYM(_uhoh) | 238: + .long SYM(_uhoh) | 239: + .long SYM(_uhoh) | 240: + .long SYM(_uhoh) | 241: + .long SYM(_uhoh) | 242: + .long SYM(_uhoh) | 243: + .long SYM(_uhoh) | 244: + .long SYM(_uhoh) | 245: + .long SYM(_uhoh) | 246: + .long SYM(_uhoh) | 247: + .long SYM(_uhoh) | 248: + .long SYM(_uhoh) | 249: + .long SYM(_uhoh) | 250: + .long SYM(_uhoh) | 251: + .long SYM(_uhoh) | 252: + .long SYM(_uhoh) | 253: + .long SYM(_uhoh) | 254: + .long SYM(_uhoh) | 255: + +/* + * Default trap handler + * With an oscilloscope you can see AS* stop + */ + PUBLIC (_uhoh) +SYM(_uhoh): nop | Leave spot for breakpoint + stop #0x2700 | Stop with interrupts disabled + bra.s SYM(_uhoh) | Stuck forever + +/* + * Log, but otherwise ignore, spurious interrupts + */ + PUBLIC (_spuriousInterrupt) +SYM(_spuriousInterrupt): + addql #1,SYM(_M68kSpuriousInterruptCount) + rte + +/* + * Place the low-order 3 octets of the board's ethernet address at + * a `well-known' fixed location relative to the startup location. + */ + .align 2 + .word 0 | Padding +ethernet_address_buffer: + .word 0x08F3 | Default address + .word 0xDEAD + .word 0xCAFE + +/* + * Initial PC + */ +.globl start +start: + /* + * Step 2: Stay in Supervisor Mode + */ +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) + oriw #0x3000,sr | Switch to Master Stack Pointer + lea SYM(m360)+1024-64,a7 | Put stack in dual-port ram + | a little below the interrupt stack +#endif + + /* + * Step 3: Write the VBR + */ + lea Entry,a0 | Get base of vector table + movec a0,vbr | Set up the VBR + + /* + * Step 4: Write the MBAR + */ + movec dfc,d1 | Save destination register + moveq #7,d0 | CPU-space funcction code + movec d0,dfc | Set destination function code register + movel #SYM(m360)+0x101,d0 | MBAR value (mask CPU space accesses) + movesl d0,0x3FF00 | Set MBAR + movec d1,dfc | Restore destination register + + /* + * Step 5: Verify a dual-port RAM location + */ + lea SYM(m360),a0 | Point a0 to first DPRAM location + moveb #0x33,d0 | Set the test value + moveb d0,a0@ | Set the memory location + cmpb a0@,d0 | Does it read back? + bne SYM(_uhoh) | If not, bad news! + notb d0 | Flip bits + moveb d0,a0@ | Set the memory location + cmpb a0@,d0 | Does it read back? + bne SYM(_uhoh) | If not, bad news! + + /* + * Remaining steps are handled by C code + */ + jmp SYM(_Init68360) | Start C code (which never returns) + +/* + * Copy DATA segment, clear BSS segment, set up real stack, + * initialize heap, start C program. + * Assume that DATA and BSS sizes are multiples of 4. + */ + PUBLIC (_CopyDataClearBSSAndStart) +SYM(_CopyDataClearBSSAndStart): + lea copy_start,a0 | Get start of DATA in RAM + lea SYM(etext),a2 | Get start of DATA in ROM + cmpl a0,a2 | Are they the same? + beq.s NOCOPY | Yes, no copy necessary + lea copy_end,a1 | Get end of DATA in RAM + bra.s COPYLOOPTEST | Branch into copy loop +COPYLOOP: + movel a2@+,a0@+ | Copy word from ROM to RAM +COPYLOOPTEST: + cmpl a1,a0 | Done? + bcs.s COPYLOOP | No, skip +NOCOPY: + + lea clear_start,a0 | Get start of BSS + lea clear_end,a1 | Get end of BSS + clrl d0 | Value to set + bra.s ZEROLOOPTEST | Branch into clear loop +ZEROLOOP: + movel d0,a0@+ | Clear a word +ZEROLOOPTEST: + cmpl a1,a0 | Done? + bcs.s ZEROLOOP | No, skip + + movel #stack_init,a7 | set master stack pointer + movel d0,a7@- | environp + movel d0,a7@- | argv + movel d0,a7@- | argc + jsr SYM(boot_card) | Call C main + + PUBLIC (_mainDone) +SYM(_mainDone): + nop | Leave spot for breakpoint + movew #1,a7 | Force a double bus error + movel d0,a7@- | This should cause a RESET + stop #0x2700 | Stop with interrupts disabled + bra.s SYM(_mainDone) | Stuck forever + + .align 2 + PUBLIC (_HeapSize) +SYM (_HeapSize): + .long HeapSize + PUBLIC (_StackSize) +SYM (_StackSize): + .long StackSize +END_CODE + +BEGIN_DATA_DCL + .align 2 + PUBLIC (environ) +SYM (environ): + .long 0 + PUBLIC (_M68kSpuriousInterruptCount) +SYM (_M68kSpuriousInterruptCount): + .long 0 +END_DATA_DCL + +END + diff --git a/c/src/lib/libbsp/m68k/gen68360/start360/start360.s b/c/src/lib/libbsp/m68k/gen68360/start360/start360.s deleted file mode 100644 index 2c979e294f..0000000000 --- a/c/src/lib/libbsp/m68k/gen68360/start360/start360.s +++ /dev/null @@ -1,432 +0,0 @@ -/* - * - * This file contains the entry point for the application. - * The name of this entry point is compiler dependent. - * It jumps to the BSP which is responsible for performing - * all initialization. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may in - * the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * Based on the `gen68302' board support package, and covered by the - * original distribution terms. - * - * W. Eric Norum - * Saskatchewan Accelerator Laboratory - * University of Saskatchewan - * Saskatoon, Saskatchewan, CANADA - * eric@skatter.usask.ca - * - * $Id$ - */ - -#include "asm.h" - -BEGIN_CODE - /* - * Step 1: Decide on Reset Stack Pointer and Initial Program Counter - */ -Entry: - .long SYM(m360)+1024 | 0: Initial SSP - .long start | 1: Initial PC - .long SYM(_uhoh) | 2: Bus error - .long SYM(_uhoh) | 3: Address error - .long SYM(_uhoh) | 4: Illegal instruction - .long SYM(_uhoh) | 5: Zero division - .long SYM(_uhoh) | 6: CHK, CHK2 instruction - .long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions - .long SYM(_uhoh) | 8: Privilege violation - .long SYM(_uhoh) | 9: Trace - .long SYM(_uhoh) | 10: Line 1010 emulator - .long SYM(_uhoh) | 11: Line 1111 emulator - .long SYM(_uhoh) | 12: Hardware breakpoint - .long SYM(_uhoh) | 13: Reserved for coprocessor violation - .long SYM(_uhoh) | 14: Format error - .long SYM(_uhoh) | 15: Uninitialized interrupt - .long SYM(_uhoh) | 16: Unassigned, reserved - .long SYM(_uhoh) | 17: - .long SYM(_uhoh) | 18: - .long SYM(_uhoh) | 19: - .long SYM(_uhoh) | 20: - .long SYM(_uhoh) | 21: - .long SYM(_uhoh) | 22: - .long SYM(_uhoh) | 23: - .long SYM(_spuriousInterrupt) | 24: Spurious interrupt - .long SYM(_uhoh) | 25: Level 1 interrupt autovector - .long SYM(_uhoh) | 26: Level 2 interrupt autovector - .long SYM(_uhoh) | 27: Level 3 interrupt autovector - .long SYM(_uhoh) | 28: Level 4 interrupt autovector - .long SYM(_uhoh) | 29: Level 5 interrupt autovector - .long SYM(_uhoh) | 30: Level 6 interrupt autovector - .long SYM(_uhoh) | 31: Level 7 interrupt autovector - .long SYM(_uhoh) | 32: Trap instruction (0-15) - .long SYM(_uhoh) | 33: - .long SYM(_uhoh) | 34: - .long SYM(_uhoh) | 35: - .long SYM(_uhoh) | 36: - .long SYM(_uhoh) | 37: - .long SYM(_uhoh) | 38: - .long SYM(_uhoh) | 39: - .long SYM(_uhoh) | 40: - .long SYM(_uhoh) | 41: - .long SYM(_uhoh) | 42: - .long SYM(_uhoh) | 43: - .long SYM(_uhoh) | 44: - .long SYM(_uhoh) | 45: - .long SYM(_uhoh) | 46: - .long SYM(_uhoh) | 47: - .long SYM(_uhoh) | 48: Reserved for coprocessor - .long SYM(_uhoh) | 49: - .long SYM(_uhoh) | 50: - .long SYM(_uhoh) | 51: - .long SYM(_uhoh) | 52: - .long SYM(_uhoh) | 53: - .long SYM(_uhoh) | 54: - .long SYM(_uhoh) | 55: - .long SYM(_uhoh) | 56: - .long SYM(_uhoh) | 57: - .long SYM(_uhoh) | 58: - .long SYM(_uhoh) | 59: Unassigned, reserved - .long SYM(_uhoh) | 60: - .long SYM(_uhoh) | 61: - .long SYM(_uhoh) | 62: - .long SYM(_uhoh) | 63: - .long SYM(_uhoh) | 64: User defined vectors (192) - .long SYM(_uhoh) | 65: - .long SYM(_uhoh) | 66: - .long SYM(_uhoh) | 67: - .long SYM(_uhoh) | 68: - .long SYM(_uhoh) | 69: - .long SYM(_uhoh) | 70: - .long SYM(_uhoh) | 71: - .long SYM(_uhoh) | 72: - .long SYM(_uhoh) | 73: - .long SYM(_uhoh) | 74: - .long SYM(_uhoh) | 75: - .long SYM(_uhoh) | 76: - .long SYM(_uhoh) | 77: - .long SYM(_uhoh) | 78: - .long SYM(_uhoh) | 79: - .long SYM(_uhoh) | 80: - .long SYM(_uhoh) | 81: - .long SYM(_uhoh) | 82: - .long SYM(_uhoh) | 83: - .long SYM(_uhoh) | 84: - .long SYM(_uhoh) | 85: - .long SYM(_uhoh) | 86: - .long SYM(_uhoh) | 87: - .long SYM(_uhoh) | 88: - .long SYM(_uhoh) | 89: - .long SYM(_uhoh) | 90: - .long SYM(_uhoh) | 91: - .long SYM(_uhoh) | 92: - .long SYM(_uhoh) | 93: - .long SYM(_uhoh) | 94: - .long SYM(_uhoh) | 95: - .long SYM(_uhoh) | 96: - .long SYM(_uhoh) | 97: - .long SYM(_uhoh) | 98: - .long SYM(_uhoh) | 99: - .long SYM(_uhoh) | 100: - .long SYM(_uhoh) | 101: - .long SYM(_uhoh) | 102: - .long SYM(_uhoh) | 103: - .long SYM(_uhoh) | 104: - .long SYM(_uhoh) | 105: - .long SYM(_uhoh) | 106: - .long SYM(_uhoh) | 107: - .long SYM(_uhoh) | 108: - .long SYM(_uhoh) | 109: - .long SYM(_uhoh) | 110: - .long SYM(_uhoh) | 111: - .long SYM(_uhoh) | 112: - .long SYM(_uhoh) | 113: - .long SYM(_uhoh) | 114: - .long SYM(_uhoh) | 115: - .long SYM(_uhoh) | 116: - .long SYM(_uhoh) | 117: - .long SYM(_uhoh) | 118: - .long SYM(_uhoh) | 119: - .long SYM(_uhoh) | 120: - .long SYM(_uhoh) | 121: - .long SYM(_uhoh) | 122: - .long SYM(_uhoh) | 123: - .long SYM(_uhoh) | 124: - .long SYM(_uhoh) | 125: - .long SYM(_uhoh) | 126: - .long SYM(_uhoh) | 127: - .long SYM(_uhoh) | 128: - .long SYM(_uhoh) | 129: - .long SYM(_uhoh) | 130: - .long SYM(_uhoh) | 131: - .long SYM(_uhoh) | 132: - .long SYM(_uhoh) | 133: - .long SYM(_uhoh) | 134: - .long SYM(_uhoh) | 135: - .long SYM(_uhoh) | 136: - .long SYM(_uhoh) | 137: - .long SYM(_uhoh) | 138: - .long SYM(_uhoh) | 139: - .long SYM(_uhoh) | 140: - .long SYM(_uhoh) | 141: - .long SYM(_uhoh) | 142: - .long SYM(_uhoh) | 143: - .long SYM(_uhoh) | 144: - .long SYM(_uhoh) | 145: - .long SYM(_uhoh) | 146: - .long SYM(_uhoh) | 147: - .long SYM(_uhoh) | 148: - .long SYM(_uhoh) | 149: - .long SYM(_uhoh) | 150: - .long SYM(_uhoh) | 151: - .long SYM(_uhoh) | 152: - .long SYM(_uhoh) | 153: - .long SYM(_uhoh) | 154: - .long SYM(_uhoh) | 155: - .long SYM(_uhoh) | 156: - .long SYM(_uhoh) | 157: - .long SYM(_uhoh) | 158: - .long SYM(_uhoh) | 159: - .long SYM(_uhoh) | 160: - .long SYM(_uhoh) | 161: - .long SYM(_uhoh) | 162: - .long SYM(_uhoh) | 163: - .long SYM(_uhoh) | 164: - .long SYM(_uhoh) | 165: - .long SYM(_uhoh) | 166: - .long SYM(_uhoh) | 167: - .long SYM(_uhoh) | 168: - .long SYM(_uhoh) | 169: - .long SYM(_uhoh) | 170: - .long SYM(_uhoh) | 171: - .long SYM(_uhoh) | 172: - .long SYM(_uhoh) | 173: - .long SYM(_uhoh) | 174: - .long SYM(_uhoh) | 175: - .long SYM(_uhoh) | 176: - .long SYM(_uhoh) | 177: - .long SYM(_uhoh) | 178: - .long SYM(_uhoh) | 179: - .long SYM(_uhoh) | 180: - .long SYM(_uhoh) | 181: - .long SYM(_uhoh) | 182: - .long SYM(_uhoh) | 183: - .long SYM(_uhoh) | 184: - .long SYM(_uhoh) | 185: - .long SYM(_uhoh) | 186: - .long SYM(_uhoh) | 187: - .long SYM(_uhoh) | 188: - .long SYM(_uhoh) | 189: - .long SYM(_uhoh) | 190: - .long SYM(_uhoh) | 191: - .long SYM(_uhoh) | 192: - .long SYM(_uhoh) | 193: - .long SYM(_uhoh) | 194: - .long SYM(_uhoh) | 195: - .long SYM(_uhoh) | 196: - .long SYM(_uhoh) | 197: - .long SYM(_uhoh) | 198: - .long SYM(_uhoh) | 199: - .long SYM(_uhoh) | 200: - .long SYM(_uhoh) | 201: - .long SYM(_uhoh) | 202: - .long SYM(_uhoh) | 203: - .long SYM(_uhoh) | 204: - .long SYM(_uhoh) | 205: - .long SYM(_uhoh) | 206: - .long SYM(_uhoh) | 207: - .long SYM(_uhoh) | 208: - .long SYM(_uhoh) | 209: - .long SYM(_uhoh) | 210: - .long SYM(_uhoh) | 211: - .long SYM(_uhoh) | 212: - .long SYM(_uhoh) | 213: - .long SYM(_uhoh) | 214: - .long SYM(_uhoh) | 215: - .long SYM(_uhoh) | 216: - .long SYM(_uhoh) | 217: - .long SYM(_uhoh) | 218: - .long SYM(_uhoh) | 219: - .long SYM(_uhoh) | 220: - .long SYM(_uhoh) | 221: - .long SYM(_uhoh) | 222: - .long SYM(_uhoh) | 223: - .long SYM(_uhoh) | 224: - .long SYM(_uhoh) | 225: - .long SYM(_uhoh) | 226: - .long SYM(_uhoh) | 227: - .long SYM(_uhoh) | 228: - .long SYM(_uhoh) | 229: - .long SYM(_uhoh) | 230: - .long SYM(_uhoh) | 231: - .long SYM(_uhoh) | 232: - .long SYM(_uhoh) | 233: - .long SYM(_uhoh) | 234: - .long SYM(_uhoh) | 235: - .long SYM(_uhoh) | 236: - .long SYM(_uhoh) | 237: - .long SYM(_uhoh) | 238: - .long SYM(_uhoh) | 239: - .long SYM(_uhoh) | 240: - .long SYM(_uhoh) | 241: - .long SYM(_uhoh) | 242: - .long SYM(_uhoh) | 243: - .long SYM(_uhoh) | 244: - .long SYM(_uhoh) | 245: - .long SYM(_uhoh) | 246: - .long SYM(_uhoh) | 247: - .long SYM(_uhoh) | 248: - .long SYM(_uhoh) | 249: - .long SYM(_uhoh) | 250: - .long SYM(_uhoh) | 251: - .long SYM(_uhoh) | 252: - .long SYM(_uhoh) | 253: - .long SYM(_uhoh) | 254: - .long SYM(_uhoh) | 255: - -/* - * Default trap handler - * With an oscilloscope you can see AS* stop - */ - PUBLIC (_uhoh) -SYM(_uhoh): nop | Leave spot for breakpoint - stop #0x2700 | Stop with interrupts disabled - bra.s SYM(_uhoh) | Stuck forever - -/* - * Log, but otherwise ignore, spurious interrupts - */ - PUBLIC (_spuriousInterrupt) -SYM(_spuriousInterrupt): - addql #1,SYM(_M68kSpuriousInterruptCount) - rte - -/* - * Place the low-order 3 octets of the board's ethernet address at - * a `well-known' fixed location relative to the startup location. - */ - .align 2 - .word 0 | Padding -ethernet_address_buffer: - .word 0x08F3 | Default address - .word 0xDEAD - .word 0xCAFE - -/* - * Initial PC - */ -.globl start -start: - /* - * Step 2: Stay in Supervisor Mode - */ -#if ( M68K_HAS_SEPARATE_STACKS == 1 ) - oriw #0x3000,sr | Switch to Master Stack Pointer - lea SYM(m360)+1024-64,a7 | Put stack in dual-port ram - | a little below the interrupt stack -#endif - - /* - * Step 3: Write the VBR - */ - lea Entry,a0 | Get base of vector table - movec a0,vbr | Set up the VBR - - /* - * Step 4: Write the MBAR - */ - movec dfc,d1 | Save destination register - moveq #7,d0 | CPU-space funcction code - movec d0,dfc | Set destination function code register - movel #SYM(m360)+0x101,d0 | MBAR value (mask CPU space accesses) - movesl d0,0x3FF00 | Set MBAR - movec d1,dfc | Restore destination register - - /* - * Step 5: Verify a dual-port RAM location - */ - lea SYM(m360),a0 | Point a0 to first DPRAM location - moveb #0x33,d0 | Set the test value - moveb d0,a0@ | Set the memory location - cmpb a0@,d0 | Does it read back? - bne SYM(_uhoh) | If not, bad news! - notb d0 | Flip bits - moveb d0,a0@ | Set the memory location - cmpb a0@,d0 | Does it read back? - bne SYM(_uhoh) | If not, bad news! - - /* - * Remaining steps are handled by C code - */ - jmp SYM(_Init68360) | Start C code (which never returns) - -/* - * Copy DATA segment, clear BSS segment, set up real stack, - * initialize heap, start C program. - * Assume that DATA and BSS sizes are multiples of 4. - */ - PUBLIC (_CopyDataClearBSSAndStart) -SYM(_CopyDataClearBSSAndStart): - lea copy_start,a0 | Get start of DATA in RAM - lea SYM(etext),a2 | Get start of DATA in ROM - cmpl a0,a2 | Are they the same? - beq.s NOCOPY | Yes, no copy necessary - lea copy_end,a1 | Get end of DATA in RAM - bra.s COPYLOOPTEST | Branch into copy loop -COPYLOOP: - movel a2@+,a0@+ | Copy word from ROM to RAM -COPYLOOPTEST: - cmpl a1,a0 | Done? - bcs.s COPYLOOP | No, skip -NOCOPY: - - lea clear_start,a0 | Get start of BSS - lea clear_end,a1 | Get end of BSS - clrl d0 | Value to set - bra.s ZEROLOOPTEST | Branch into clear loop -ZEROLOOP: - movel d0,a0@+ | Clear a word -ZEROLOOPTEST: - cmpl a1,a0 | Done? - bcs.s ZEROLOOP | No, skip - - movel #stack_init,a7 | set master stack pointer - movel d0,a7@- | environp - movel d0,a7@- | argv - movel d0,a7@- | argc - jsr SYM(boot_card) | Call C main - - PUBLIC (_mainDone) -SYM(_mainDone): - nop | Leave spot for breakpoint - movew #1,a7 | Force a double bus error - movel d0,a7@- | This should cause a RESET - stop #0x2700 | Stop with interrupts disabled - bra.s SYM(_mainDone) | Stuck forever - - .align 2 - PUBLIC (_HeapSize) -SYM (_HeapSize): - .long HeapSize - PUBLIC (_StackSize) -SYM (_StackSize): - .long StackSize -END_CODE - -BEGIN_DATA_DCL - .align 2 - PUBLIC (environ) -SYM (environ): - .long 0 - PUBLIC (_M68kSpuriousInterruptCount) -SYM (_M68kSpuriousInterruptCount): - .long 0 -END_DATA_DCL - -END - diff --git a/c/src/lib/libbsp/m68k/idp/timer/Makefile.in b/c/src/lib/libbsp/m68k/idp/timer/Makefile.in index 0c8ec3ccaa..4fabb39e55 100644 --- a/c/src/lib/libbsp/m68k/idp/timer/Makefile.in +++ b/c/src/lib/libbsp/m68k/idp/timer/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=timerisr -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/m68k/idp/timer/timerisr.S b/c/src/lib/libbsp/m68k/idp/timer/timerisr.S new file mode 100644 index 0000000000..74461f3714 --- /dev/null +++ b/c/src/lib/libbsp/m68k/idp/timer/timerisr.S @@ -0,0 +1,38 @@ +/* timer_isr() + * + * This routine provides the ISR for the MC68230 timer on the Motorola + * IDP board. The timer is set up to generate an interrupt at maximum + * intervals. + * + * Code modified by Doug McBride, Colorado Space Grant College + * countdown should be loaded automatically + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include "asm.h" + +BEGIN_CODE + +.set TSR, 0x00c0106B | base address of PIT register "TSR" + + PUBLIC (timerisr) +SYM (timerisr): + movb #1,TSR | acknowledge interrupt + addql #1, SYM (Ttimer_val) | increment timer value + rte + +END_CODE +END diff --git a/c/src/lib/libbsp/m68k/idp/timer/timerisr.s b/c/src/lib/libbsp/m68k/idp/timer/timerisr.s deleted file mode 100644 index 74461f3714..0000000000 --- a/c/src/lib/libbsp/m68k/idp/timer/timerisr.s +++ /dev/null @@ -1,38 +0,0 @@ -/* timer_isr() - * - * This routine provides the ISR for the MC68230 timer on the Motorola - * IDP board. The timer is set up to generate an interrupt at maximum - * intervals. - * - * Code modified by Doug McBride, Colorado Space Grant College - * countdown should be loaded automatically - * - * Input parameters: NONE - * - * Output parameters: NONE - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include "asm.h" - -BEGIN_CODE - -.set TSR, 0x00c0106B | base address of PIT register "TSR" - - PUBLIC (timerisr) -SYM (timerisr): - movb #1,TSR | acknowledge interrupt - addql #1, SYM (Ttimer_val) | increment timer value - rte - -END_CODE -END diff --git a/c/src/lib/libbsp/m68k/mvme136/timer/Makefile.in b/c/src/lib/libbsp/m68k/mvme136/timer/Makefile.in index 24809cbed8..21ca9675e7 100644 --- a/c/src/lib/libbsp/m68k/mvme136/timer/Makefile.in +++ b/c/src/lib/libbsp/m68k/mvme136/timer/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=timerisr -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/m68k/mvme136/timer/timerisr.S b/c/src/lib/libbsp/m68k/mvme136/timer/timerisr.S new file mode 100644 index 0000000000..63ee63bd8e --- /dev/null +++ b/c/src/lib/libbsp/m68k/mvme136/timer/timerisr.S @@ -0,0 +1,39 @@ +/* timer_isr() + * + * This routine provides the ISR for the Z8036 timer on the MVME136 + * board. The timer is set up to generate an interrupt at maximum + * intervals. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include "asm.h" + +BEGIN_CODE + +.set CT1_CMD_STATUS, 0xfffb000a | port A +.set RELOAD, 0x24 | clr IP & IUS,allow countdown + + PUBLIC (timerisr) +SYM (timerisr): + movl a0,a7@- | save a0 + movl #CT1_CMD_STATUS,a0 | a0 = addr of cmd status reg + movb #RELOAD,a0@ | reload countdown + addql #1, SYM (Ttimer_val) | increment timer value + movl a7@+,a0 | save a0 + rte + +END_CODE +END diff --git a/c/src/lib/libbsp/m68k/mvme136/timer/timerisr.s b/c/src/lib/libbsp/m68k/mvme136/timer/timerisr.s deleted file mode 100644 index 63ee63bd8e..0000000000 --- a/c/src/lib/libbsp/m68k/mvme136/timer/timerisr.s +++ /dev/null @@ -1,39 +0,0 @@ -/* timer_isr() - * - * This routine provides the ISR for the Z8036 timer on the MVME136 - * board. The timer is set up to generate an interrupt at maximum - * intervals. - * - * Input parameters: NONE - * - * Output parameters: NONE - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#include "asm.h" - -BEGIN_CODE - -.set CT1_CMD_STATUS, 0xfffb000a | port A -.set RELOAD, 0x24 | clr IP & IUS,allow countdown - - PUBLIC (timerisr) -SYM (timerisr): - movl a0,a7@- | save a0 - movl #CT1_CMD_STATUS,a0 | a0 = addr of cmd status reg - movb #RELOAD,a0@ | reload countdown - addql #1, SYM (Ttimer_val) | increment timer value - movl a7@+,a0 | save a0 - rte - -END_CODE -END diff --git a/c/src/lib/libbsp/m68k/mvme136/wrapup/Makefile.in b/c/src/lib/libbsp/m68k/mvme136/wrapup/Makefile.in index 4dc4ea5208..aecc98b975 100644 --- a/c/src/lib/libbsp/m68k/mvme136/wrapup/Makefile.in +++ b/c/src/lib/libbsp/m68k/mvme136/wrapup/Makefile.in @@ -8,17 +8,22 @@ VPATH = @srcdir@ RTEMS_ROOT = @top_srcdir@ PROJECT_ROOT = @PROJECT_ROOT@ -BSP_PIECES=startup clock console shmsupp timer -GENERIC_PIECES=shmdr +BSP_PIECES=startup clock console timer +GENERIC_PIECES= + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/lib.cfg + +ifeq ($(HAS_MP),yes) +GENERIC_PIECES += shmdr +BSP_PIECES += shmsupp +endif # bummer; have to use $foreach since % pattern subst rules only replace 1x OBJS=$(foreach piece, $(BSP_PIECES), ../$(piece)/$(ARCH)/$(piece).rel) \ $(foreach piece, $(GENERIC_PIECES), ../../../$(piece)/$(ARCH)/$(piece).rel) LIB=$(ARCH)/libbsp.a -include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg -include $(RTEMS_ROOT)/make/lib.cfg - # # (OPTIONAL) Add local stuff here using += # diff --git a/c/src/lib/libbsp/m68k/mvme147/timer/Makefile.in b/c/src/lib/libbsp/m68k/mvme147/timer/Makefile.in index 24809cbed8..21ca9675e7 100644 --- a/c/src/lib/libbsp/m68k/mvme147/timer/Makefile.in +++ b/c/src/lib/libbsp/m68k/mvme147/timer/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=timerisr -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/m68k/mvme147/timer/timerisr.s b/c/src/lib/libbsp/m68k/mvme147/timer/timerisr.s deleted file mode 100644 index 7debd13849..0000000000 --- a/c/src/lib/libbsp/m68k/mvme147/timer/timerisr.s +++ /dev/null @@ -1,28 +0,0 @@ -/* timer_isr() - * - * This routine provides the ISR for the PCC timer on the MVME147 - * board. The timer is set up to generate an interrupt at maximum - * intervals. - * - * MVME147 port for TNI - Telecom Bretagne - * by Dominique LE CAMPION (Dominique.LECAMPION@enst-bretagne.fr) - * May 1996 - * - * $Id$ - */ - -#include "asm.h" - -BEGIN_CODE - -.set T1_CONTROL_REGISTER, 0xfffe1018 | timer 1 control register - - PUBLIC (timerisr) -SYM (timerisr): - orb #0x80, T1_CONTROL_REGISTER | clear T1 int status bit - addql #1, SYM (Ttimer_val) | increment timer value -end_timerisr: - rte - -END_CODE -END diff --git a/c/src/lib/libbsp/m68k/mvme147/wrapup/Makefile.in b/c/src/lib/libbsp/m68k/mvme147/wrapup/Makefile.in index 33d990d882..a42a827299 100644 --- a/c/src/lib/libbsp/m68k/mvme147/wrapup/Makefile.in +++ b/c/src/lib/libbsp/m68k/mvme147/wrapup/Makefile.in @@ -8,8 +8,8 @@ VPATH = @srcdir@ RTEMS_ROOT = @top_srcdir@ PROJECT_ROOT = @PROJECT_ROOT@ -BSP_PIECES=startup clock console timer # shmsupp -GENERIC_PIECES=# shmdr +BSP_PIECES=startup clock console timer +GENERIC_PIECES= # bummer; have to use $foreach since % pattern subst rules only replace 1x OBJS=$(foreach piece, $(BSP_PIECES), ../$(piece)/$(ARCH)/$(piece).rel) \ diff --git a/c/src/lib/libbsp/m68k/mvme147s/timer/Makefile.in b/c/src/lib/libbsp/m68k/mvme147s/timer/Makefile.in index c12e535ace..03902da08d 100644 --- a/c/src/lib/libbsp/m68k/mvme147s/timer/Makefile.in +++ b/c/src/lib/libbsp/m68k/mvme147s/timer/Makefile.in @@ -15,10 +15,10 @@ C_PIECES=timer C_FILES=$(C_PIECES:%=%.c) C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=timerisr -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) H_FILES= diff --git a/c/src/lib/libbsp/m68k/mvme147s/wrapup/Makefile.in b/c/src/lib/libbsp/m68k/mvme147s/wrapup/Makefile.in index 8c70b9398f..aecc98b975 100644 --- a/c/src/lib/libbsp/m68k/mvme147s/wrapup/Makefile.in +++ b/c/src/lib/libbsp/m68k/mvme147s/wrapup/Makefile.in @@ -8,17 +8,22 @@ VPATH = @srcdir@ RTEMS_ROOT = @top_srcdir@ PROJECT_ROOT = @PROJECT_ROOT@ -BSP_PIECES=startup clock console timer shmsupp -GENERIC_PIECES=shmdr +BSP_PIECES=startup clock console timer +GENERIC_PIECES= + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/lib.cfg + +ifeq ($(HAS_MP),yes) +GENERIC_PIECES += shmdr +BSP_PIECES += shmsupp +endif # bummer; have to use $foreach since % pattern subst rules only replace 1x OBJS=$(foreach piece, $(BSP_PIECES), ../$(piece)/$(ARCH)/$(piece).rel) \ $(foreach piece, $(GENERIC_PIECES), ../../../$(piece)/$(ARCH)/$(piece).rel) LIB=$(ARCH)/libbsp.a -include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg -include $(RTEMS_ROOT)/make/lib.cfg - # # (OPTIONAL) Add local stuff here using += # diff --git a/c/src/lib/libbsp/m68k/mvme162/timer/Makefile.in b/c/src/lib/libbsp/m68k/mvme162/timer/Makefile.in index 24809cbed8..21ca9675e7 100644 --- a/c/src/lib/libbsp/m68k/mvme162/timer/Makefile.in +++ b/c/src/lib/libbsp/m68k/mvme162/timer/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=timerisr -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/m68k/mvme162/timer/timerisr.S b/c/src/lib/libbsp/m68k/mvme162/timer/timerisr.S new file mode 100644 index 0000000000..9380fac0f0 --- /dev/null +++ b/c/src/lib/libbsp/m68k/mvme162/timer/timerisr.S @@ -0,0 +1,47 @@ +/* timer_isr() + * + * This routine provides the ISR for the Z8036 timer on the MVME136 + * board. The timer is set up to generate an interrupt at maximum + * intervals. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * Modifications of respective RTEMS file: COPYRIGHT (c) 1994. + * EISCAT Scientific Association. M.Savitski + * + * This material is a part of the MVME162 Board Support Package + * for the RTEMS executive. Its licensing policies are those of the + * RTEMS above. + * + * $Id$ + */ + +#include "asm.h" + +BEGIN_CODE + +.set INTR_CLEAR_REG, 0xfff40074 | interrupt clear register +.set RELOAD, 0x01000000 | clear tick 1 interrupt + + PUBLIC (Ttimer_val) + PUBLIC (timerisr) +SYM (timerisr): + move.l a0, -(a7) | save a0 + movea.l #INTR_CLEAR_REG, a0 | a0 = addr of cmd status reg + ori.l #RELOAD, (a0) | reload countdown + addq.l #1, SYM (Ttimer_val) | increment timer value + move.l (a7)+, a0 | restore a0 + rte + +END_CODE +END diff --git a/c/src/lib/libbsp/m68k/mvme162/timer/timerisr.s b/c/src/lib/libbsp/m68k/mvme162/timer/timerisr.s deleted file mode 100644 index 9380fac0f0..0000000000 --- a/c/src/lib/libbsp/m68k/mvme162/timer/timerisr.s +++ /dev/null @@ -1,47 +0,0 @@ -/* timer_isr() - * - * This routine provides the ISR for the Z8036 timer on the MVME136 - * board. The timer is set up to generate an interrupt at maximum - * intervals. - * - * Input parameters: NONE - * - * Output parameters: NONE - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * Modifications of respective RTEMS file: COPYRIGHT (c) 1994. - * EISCAT Scientific Association. M.Savitski - * - * This material is a part of the MVME162 Board Support Package - * for the RTEMS executive. Its licensing policies are those of the - * RTEMS above. - * - * $Id$ - */ - -#include "asm.h" - -BEGIN_CODE - -.set INTR_CLEAR_REG, 0xfff40074 | interrupt clear register -.set RELOAD, 0x01000000 | clear tick 1 interrupt - - PUBLIC (Ttimer_val) - PUBLIC (timerisr) -SYM (timerisr): - move.l a0, -(a7) | save a0 - movea.l #INTR_CLEAR_REG, a0 | a0 = addr of cmd status reg - ori.l #RELOAD, (a0) | reload countdown - addq.l #1, SYM (Ttimer_val) | increment timer value - move.l (a7)+, a0 | restore a0 - rte - -END_CODE -END diff --git a/c/src/lib/libbsp/m68k/ods68302/start/Makefile.in b/c/src/lib/libbsp/m68k/ods68302/start/Makefile.in index a6d3ba2c08..8344f4f8a9 100644 --- a/c/src/lib/libbsp/m68k/ods68302/start/Makefile.in +++ b/c/src/lib/libbsp/m68k/ods68302/start/Makefile.in @@ -24,10 +24,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=$(RESET_SRC) -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(S_O_FILES) $(C_O_FILES) diff --git a/c/src/lib/libbsp/m68k/ods68302/start302/Makefile.in b/c/src/lib/libbsp/m68k/ods68302/start302/Makefile.in index a6d3ba2c08..8344f4f8a9 100644 --- a/c/src/lib/libbsp/m68k/ods68302/start302/Makefile.in +++ b/c/src/lib/libbsp/m68k/ods68302/start302/Makefile.in @@ -24,10 +24,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=$(RESET_SRC) -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(S_O_FILES) $(C_O_FILES) diff --git a/c/src/lib/libbsp/m68k/ods68302/timer/Makefile.in b/c/src/lib/libbsp/m68k/ods68302/timer/Makefile.in index 24809cbed8..21ca9675e7 100644 --- a/c/src/lib/libbsp/m68k/ods68302/timer/Makefile.in +++ b/c/src/lib/libbsp/m68k/ods68302/timer/Makefile.in @@ -17,10 +17,10 @@ C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= -# Assembly source names, if any, go here -- minus the .s +# Assembly source names, if any, go here -- minus the .S S_PIECES=timerisr -S_FILES=$(S_PIECES:%=%.s) -S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) SRCS=$(C_FILES) $(H_FILES) $(S_FILES) OBJS=$(C_O_FILES) $(S_O_FILES) diff --git a/c/src/lib/libbsp/m68k/ods68302/timer/timerisr.S b/c/src/lib/libbsp/m68k/ods68302/timer/timerisr.S new file mode 100644 index 0000000000..c804b9dfa6 --- /dev/null +++ b/c/src/lib/libbsp/m68k/ods68302/timer/timerisr.S @@ -0,0 +1,28 @@ +/* + * Handle 68302 TIMER2 interrupts. + * + * All code in this routine is pure overhead which can perturb the + * accuracy of RTEMS' timing test suite. + * + * See also: Read_timer() + * + * To reduce overhead this is best to be the "rawest" hardware interupt + * handler you can write. This should be the only interrupt which can + * occur during the measured time period. + * + * An external counter, Timer_interrupts, is incremented. + * + * $Id$ + */ + +#include "asm.h" + +BEGIN_CODE + PUBLIC(timerisr) +SYM(timerisr): + move.w #0x0040,SYM(m302)+2072 | clear interrupt in-service bit + move.b #3,SYM(m302)+2137 | clear timer interrupt event register + addq.l #1,SYM(Timer_interrupts) | increment timer value + rte +END_CODE +END diff --git a/c/src/lib/libbsp/m68k/ods68302/timer/timerisr.s b/c/src/lib/libbsp/m68k/ods68302/timer/timerisr.s deleted file mode 100644 index c804b9dfa6..0000000000 --- a/c/src/lib/libbsp/m68k/ods68302/timer/timerisr.s +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Handle 68302 TIMER2 interrupts. - * - * All code in this routine is pure overhead which can perturb the - * accuracy of RTEMS' timing test suite. - * - * See also: Read_timer() - * - * To reduce overhead this is best to be the "rawest" hardware interupt - * handler you can write. This should be the only interrupt which can - * occur during the measured time period. - * - * An external counter, Timer_interrupts, is incremented. - * - * $Id$ - */ - -#include "asm.h" - -BEGIN_CODE - PUBLIC(timerisr) -SYM(timerisr): - move.w #0x0040,SYM(m302)+2072 | clear interrupt in-service bit - move.b #3,SYM(m302)+2137 | clear timer interrupt event register - addq.l #1,SYM(Timer_interrupts) | increment timer value - rte -END_CODE -END diff --git a/c/src/lib/libbsp/m68k/shared/start.S b/c/src/lib/libbsp/m68k/shared/start.S new file mode 100644 index 0000000000..72849170d9 --- /dev/null +++ b/c/src/lib/libbsp/m68k/shared/start.S @@ -0,0 +1,153 @@ +/* entry.s + * + * This file contains the entry point for the application. + * The name of this entry point is compiler dependent. + * It jumps to the BSP which is responsible for performing + * all initialization. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include "asm.h" + +#if (M68K_COLDFIRE_ARCH == 0) /* All ColdFire BSPs must provide their own start vector */ + +BEGIN_CODE + | Default entry points for: + PUBLIC (start) | GNU + PUBLIC (M68Kvec) | Vector Table + +SYM (start): +SYM (M68Kvec): | standard location for vectors + nop | for linkers with problem + | location zero + jmp SYM (start_around) + + /* + * We can use the following space as our vector table + * if the CPU has a VBR or we can save vector table in it + * if the CPU does not. + */ + + .space 4088 | to avoid initial intr stack + | from 135BUG on MVME13? + | and start code at 0x4000 +SYM (vectors): + .space 1016 | reserve space for rest of vectors + +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) +SYM (lowintstack): + .space 4092 | reserve for interrupt stack +SYM (hiintstack): + .space 4 | end of interrupt stack +#endif + + PUBLIC (start_around) +SYM (start_around): + move.w sr, SYM (initial_sr) + oriw #0x3700,sr | SUPV MODE,INTERRUPTS OFF!!! +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) + movec isp,a0 + move.l a0, SYM (initial_isp) + movec usp,a0 + move.l a0, SYM (initial_usp) + movec msp,a0 + move.l a0, SYM (initial_msp) +#else + move.l a7, SYM (initial_msp) +#endif + + | + | zero out uninitialized data area + | +zerobss: + moveal # SYM (end),a0 | find end of .bss + moveal # SYM (bss_start),a1 | find beginning of .bss + movel #0,d0 + +loop: movel #0,a1@+ | to zero out uninitialized + cmpal a0,a1 + jlt loop | loop until _end reached + + movel # SYM (stack_init),d0 | d0 = stop of stack + andl #0xffffffc0,d0 | align it on 16 byte boundary + movw #0x3700,sr | SUPV MODE,INTERRUPTS OFF!!! + movel d0,a7 | set master stack pointer + movel d0,a6 | set base pointer + + /* + * RTEMS should maintain a separate interrupt stack on CPUs + * without one in hardware. This is currently not supported + * on versions of the m68k without a HW intr stack. + */ + +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) + lea SYM (hiintstack),a0 | a0 = high end of intr stack + movec a0,isp | set interrupt stack +#endif + movel #0,a7@- | push environp + movel #0,a7@- | push argv + movel #0,a7@- | push argc + + jsr SYM (boot_card) + addl #12,a7 + +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) + move.l SYM (initial_isp),a0 + movec a0,isp + move.l SYM (initial_usp),a0 + movec a0,usp + move.l SYM (initial_msp),a0 + movec a0,msp +#else + movea.l SYM (initial_msp),a7 +#endif + move.w SYM (initial_sr),sr + rts + +END_CODE + +BEGIN_DATA + + PUBLIC (start_frame) +SYM (start_frame): + .space 4,0 + +END_DATA + +BEGIN_BSS + + PUBLIC (environ) + .align 2 +SYM (environ): + .long 0 + + PUBLIC (initial_isp) +SYM (initial_isp): + .space 4 + + PUBLIC (initial_msp) +SYM (initial_msp): + .space 4 + + PUBLIC (initial_usp) +SYM (initial_usp): + .space 4 + + PUBLIC (initial_sr) +SYM (initial_sr): + .space 2 + +END_DATA +#endif +END + + -- cgit v1.2.3