From 2fbe159e9ace91a32649683c97f729c4d40c5b7d Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Fri, 19 Sep 2008 15:49:28 +0000 Subject: 2008-09-19 Joel Sherrill * Makefile.am, startup/bspstart.c: Split out bspstart contents. Move cache code to libcpu. * startup/bspgetcpuclockspeed.c: New file. --- c/src/lib/libbsp/m68k/mcf5235/startup/bspstart.c | 126 ++--------------------- 1 file changed, 9 insertions(+), 117 deletions(-) (limited to 'c/src/lib/libbsp/m68k/mcf5235/startup/bspstart.c') diff --git a/c/src/lib/libbsp/m68k/mcf5235/startup/bspstart.c b/c/src/lib/libbsp/m68k/mcf5235/startup/bspstart.c index b0193d6a62..cbfa25124f 100644 --- a/c/src/lib/libbsp/m68k/mcf5235/startup/bspstart.c +++ b/c/src/lib/libbsp/m68k/mcf5235/startup/bspstart.c @@ -1,16 +1,5 @@ /* - * BSP startup - * - * This routine starts the application. It includes application, - * board, and monitor specific initialization and configuration. - * The generic CPU dependent initialization has been performed - * before this routine is invoked. - * - * Author: - * David Fiddes, D.J@fiddes.surfaid.org - * http://www.calm.hw.ac.uk/davidf/coldfire/ - * - * COPYRIGHT (c) 1989-1998. + * COPYRIGHT (c) 1989-2008. * On-Line Applications Research Corporation (OAR). * * The license and distribution terms for this file may be @@ -23,19 +12,6 @@ #include -/* - * Cacheable areas - */ -#define SDRAM_BASE 0 -#define SDRAM_SIZE (16*1024*1024) - -/* - * CPU-space access - */ -#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr)) -#define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0)) -#define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1)) - /* * Read/write copy of common cache * Split I/D cache @@ -44,90 +20,13 @@ * No burst transfers on non-cacheable accesses * Default cache mode is *disabled* (cache only ACRx areas) */ -static uint32_t cacr_mode = MCF5XXX_CACR_CENB | - MCF5XXX_CACR_DBWE | - MCF5XXX_CACR_DCM; -/* - * Cannot be frozen - */ -void _CPU_cache_freeze_data(void) {} -void _CPU_cache_unfreeze_data(void) {} -void _CPU_cache_freeze_instruction(void) {} -void _CPU_cache_unfreeze_instruction(void) {} +uint32_t cacr_mode = MCF5XXX_CACR_CENB | MCF5XXX_CACR_DBWE | MCF5XXX_CACR_DCM; /* - * Write-through data cache -- flushes are unnecessary + * Cacheable areas */ -void _CPU_cache_flush_1_data_line(const void *d_addr) {} -void _CPU_cache_flush_entire_data(void) {} - -void _CPU_cache_enable_instruction(void) -{ - rtems_interrupt_level level; - - rtems_interrupt_disable(level); - cacr_mode &= ~MCF5XXX_CACR_DIDI; - m68k_set_cacr(cacr_mode); - rtems_interrupt_enable(level); -} - -void _CPU_cache_disable_instruction(void) -{ - rtems_interrupt_level level; - - rtems_interrupt_disable(level); - cacr_mode |= MCF5XXX_CACR_DIDI; - m68k_set_cacr(cacr_mode); - rtems_interrupt_enable(level); -} - -void _CPU_cache_invalidate_entire_instruction(void) -{ - m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI); -} - -void _CPU_cache_invalidate_1_instruction_line(const void *addr) -{ - /* - * Top half of cache is I-space - */ - addr = (void *)((int)addr | 0x400); - asm volatile ("cpushl %%bc,(%0)" :: "a" (addr)); -} - -void _CPU_cache_enable_data(void) -{ - rtems_interrupt_level level; - - rtems_interrupt_disable(level); - cacr_mode &= ~MCF5XXX_CACR_DISD; - m68k_set_cacr(cacr_mode); - rtems_interrupt_enable(level); -} - -void _CPU_cache_disable_data(void) -{ - rtems_interrupt_level level; - - rtems_interrupt_disable(level); - cacr_mode |= MCF5XXX_CACR_DISD; - m68k_set_cacr(cacr_mode); - rtems_interrupt_enable(level); -} - -void _CPU_cache_invalidate_entire_data(void) -{ - m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD); -} - -void _CPU_cache_invalidate_1_data_line(const void *addr) -{ - /* - * Bottom half of cache is D-space - */ - addr = (void *)((int)addr & ~0x400); - asm volatile ("cpushl %%bc,(%0)" :: "a" (addr)); -} +extern char RamBase[]; +extern char RamSize[]; /* * bsp_start @@ -146,10 +45,10 @@ void bsp_start( void ) /* * Cache SDRAM */ - m68k_set_acr0(MCF5XXX_ACR_AB(SDRAM_BASE) | - MCF5XXX_ACR_AM(SDRAM_SIZE-1) | - MCF5XXX_ACR_EN | - MCF5XXX_ACR_BWE | + m68k_set_acr0(MCF5XXX_ACR_AB((uintptr_t)RamBase) | + MCF5XXX_ACR_AM((uintptr_t)RamSize-1) | + MCF5XXX_ACR_EN | + MCF5XXX_ACR_BWE | MCF5XXX_ACR_SM_IGNORE); /* @@ -157,10 +56,3 @@ void bsp_start( void ) */ m68k_set_cacr(cacr_mode); } - -extern char _CPUClockSpeed[]; - -uint32_t get_CPU_clock_speed(void) -{ - return( (uint32_t)_CPUClockSpeed); -} -- cgit v1.2.3