From 334427722c30d1086786e37bca2ff33752bb5aa0 Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Mon, 30 Mar 1998 13:42:13 +0000 Subject: Update from "erik.ivanenko" . Also removed bsp_postdriver_hook() from every bsp possible and moved to shared version. --- c/src/lib/libbsp/i386/i386ex/Makefile.in | 2 +- c/src/lib/libbsp/i386/i386ex/bsp_specs | 2 +- c/src/lib/libbsp/i386/i386ex/console/console.c | 2 +- c/src/lib/libbsp/i386/i386ex/start/80386ex.h | 254 ++++++++++ c/src/lib/libbsp/i386/i386ex/start/80386ex.inc | 252 ++++++++++ c/src/lib/libbsp/i386/i386ex/start/Makefile.in | 57 +++ c/src/lib/libbsp/i386/i386ex/start/macros.inc | 115 +++++ c/src/lib/libbsp/i386/i386ex/start/start.s | 572 +++++++++++++++++++++++ c/src/lib/libbsp/i386/i386ex/startup/Makefile.in | 6 +- c/src/lib/libbsp/i386/i386ex/startup/README | 26 +- c/src/lib/libbsp/i386/i386ex/startup/bspstart.c | 114 ++--- c/src/lib/libbsp/i386/i386ex/startup/linkcmds | 160 +++++-- 12 files changed, 1432 insertions(+), 130 deletions(-) create mode 100644 c/src/lib/libbsp/i386/i386ex/start/80386ex.h create mode 100644 c/src/lib/libbsp/i386/i386ex/start/80386ex.inc create mode 100644 c/src/lib/libbsp/i386/i386ex/start/Makefile.in create mode 100644 c/src/lib/libbsp/i386/i386ex/start/macros.inc create mode 100644 c/src/lib/libbsp/i386/i386ex/start/start.s (limited to 'c/src/lib/libbsp/i386') diff --git a/c/src/lib/libbsp/i386/i386ex/Makefile.in b/c/src/lib/libbsp/i386/i386ex/Makefile.in index 59f67b5c4e..23420b1a4f 100644 --- a/c/src/lib/libbsp/i386/i386ex/Makefile.in +++ b/c/src/lib/libbsp/i386/i386ex/Makefile.in @@ -16,4 +16,4 @@ include $(RTEMS_ROOT)/make/directory.cfg #was: #SUB_DIRS=include startup clock console shmsupp timer wrapup #is -SUB_DIRS=include startup clock console timer wrapup +SUB_DIRS=include start startup clock console timer wrapup diff --git a/c/src/lib/libbsp/i386/i386ex/bsp_specs b/c/src/lib/libbsp/i386/i386ex/bsp_specs index 61dac86b53..3d4b66ec40 100644 --- a/c/src/lib/libbsp/i386/i386ex/bsp_specs +++ b/c/src/lib/libbsp/i386/i386ex/bsp_specs @@ -19,5 +19,5 @@ %{qrtems_debug: start_g.o%s}} *link: -%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N -e start} +%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N -e reset} diff --git a/c/src/lib/libbsp/i386/i386ex/console/console.c b/c/src/lib/libbsp/i386/i386ex/console/console.c index 8920951e4c..0d05e84b30 100644 --- a/c/src/lib/libbsp/i386/i386ex/console/console.c +++ b/c/src/lib/libbsp/i386/i386ex/console/console.c @@ -19,7 +19,7 @@ #include -#include "../startup/80386ex.h" +#include "../start/80386ex.h" /* console_cleanup * diff --git a/c/src/lib/libbsp/i386/i386ex/start/80386ex.h b/c/src/lib/libbsp/i386/i386ex/start/80386ex.h new file mode 100644 index 0000000000..24e4b9a8ee --- /dev/null +++ b/c/src/lib/libbsp/i386/i386ex/start/80386ex.h @@ -0,0 +1,254 @@ +/* + * Submitted by: + * + * Erik Ivanenko + * University of Toronto + * erik.ivanenko@utoronto.ca + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +/* REMAP ADDRESSING Registers */ +#define REMAPCFGH 0x0023 +#define REMAPCFGL 0x0022 +#define REMAPCFG 0x0022 +/* INTERRUPT CONTROL REGISTERS -- SLOT 15 ADDRESSES */ +#define ICW1M 0xF020 +#define ICW1S 0xF0A0 +#define ICW2M 0xF021 +#define ICW2S 0xF0A1 +#define ICW3M 0xF021 +#define ICW3S 0xF0A1 +#define ICW4M 0xF021 +#define ICW4S 0xF0A1 +#define OCW1M 0xF021 +#define OCW1S 0xF0A1 +#define OCW2M 0xF020 +#define OCW2S 0xF0A0 +#define OCW3M 0xF020 +#define OCW3S 0xF0A0 +/* INTERRUPT CONTROL REGISTERS -- SLOT 0 ADDRESSES */ +#define ICW1MDOS 0x0020 +#define ICW1SDOS 0x00A0 +#define ICW2MDOS 0x0021 +#define ICW2SDOS 0x00A1 +#define ICW3MDOS 0x0021 +#define ICW3SDOS 0x00A1 +#define ICW4MDOS 0x0021 +#define ICW4SDOS 0x00A1 +#define OCW1MDOS 0x0021 +#define OCW1SDOS 0x00A1 +#define OCW2MDOS 0x0020 +#define OCW2SDOS 0x00A0 +#define OCW3MDOS 0x0020 +#define OCW3SDOS 0x00A0 + + +/* CONFIGURATION Registers */ +#define DMACFG 0xF830 +#define INTCFG 0xF832 +#define TMRCFG 0xF834 +#define SIOCFG 0xF836 +#define P1CFG 0xF820 +#define P2CFG 0xF822 +#define P3CFG 0xF824 +#define PINCFG 0xF826 + +/* WATCHDOG TIMER Registers */ +#define WDTRLDH 0xF4C0 +#define WDTRLDL 0xF4C2 +#define WDTCNTH 0xF4C4 +#define WDTCNTL 0xF4C6 +#define WDTCLR 0xF4C8 +#define WDTSTATUS 0xF4CA + +/* TIMER CONTROL REGISTERS -- SLOT 15 ADDRESSES */ +#define TMR0 0xF040 +#define TMR1 0xF041 +#define TMR2 0xF042 +#define TMRCON 0xF043 +/* TIMER CONTROL REGISTERS -- SLOT 0 ADDRESSES */ +#define TMR0DOS 0x0040 +#define TMR1DOS 0x0041 +#define TMR2DOS 0x0042 +#define TMRCONDOS 0x0043 + +/* INPUT/OUTPUT PORT UNIT Registers */ +#define P1PIN 0xF860 +#define P1LTC 0xF862 +#define P1DIR 0xF864 +#define P2PIN 0xF868 +#define P2LTC 0xF86A +#define P2DIR 0xF86C +#define P3PIN 0xF870 +#define P3LTC 0xF872 +#define P3DIR 0xF874 + +/* ASYNCHRONOUS SERIAL CHANNEL 0 -- SLOT 15 ADDRESSES */ +#define RBR0 0xF4F8 +#define THR0 0xF4F8 +#define TBR0 0xF4F8 +#define DLL0 0xF4F8 +#define IER0 0xF4F9 +#define DLH0 0xF4F9 +#define IIR0 0xF4FA +#define LCR0 0xF4FB +#define MCR0 0xF4FC +#define LSR0 0xF4FD +#define MSR0 0xF4FE +#define SCR0 0xF4FF +/* ASYNCHRONOUS SERIAL CHANNEL 0 -- SLOT 0 ADDRESSES */ +#define RBR0DOS 0x03F8 +#define THR0DOS 0x03F8 +#define TBR0DOS 0x03F8 +#define DLL0DOS 0x03F8 +#define IER0DOS 0x03F9 +#define DLH0DOS 0x03F9 +#define IIR0DOS 0x03FA +#define LCR0DOS 0x03FB +#define MCR0DOS 0x03FC +#define LSR0DOS 0x03FD +#define MSR0DOS 0x03FE +#define SCR0DOS 0x03FF + +/* ASYNCHRONOUS SERIAL CHANNEL 1 -- SLOT 15 ADDRESSES */ +#define RBR1 0xF8F8 +#define THR1 0xF8F8 +#define TBR1 0XF8F8 +#define DLL1 0xF8F8 +#define IER1 0xF8F9 +#define DLH1 0xF8F9 +#define IIR1 0xF8FA +#define LCR1 0xF8FB +#define MCR1 0xF8FC +#define LSR1 0xF8FD +#define MSR1 0xF8FE +#define SCR1 0xF8FF +/* ASYNCHRONOUS SERIAL CHANNEL 1 -- SLOT 0 ADDRESSES */ +#define RBR1DOS 0x02F8 +#define THR1DOS 0x02F8 +#define TBR1DOS 0x02F8 +#define DLL1DOS 0x02F8 +#define IER1DOS 0x02F9 +#define DLH1DOS 0x02F9 +#define IIR1DOS 0x02FA +#define LCR1DOS 0x02FB +#define MCR1DOS 0x02FC +#define LSR1DOS 0x02FD +#define MSR1DOS 0x02FE +#define SCR1DOS 0x02FF + +/* SYNCHRONOUS SERIAL CHANNEL REGISTERS */ +#define SSIOTBUF 0xF480 +#define SSIORBUF 0xF482 +#define SSIOBAUD 0xF484 +#define SSIOCON1 0xF486 +#define SSIOCON2 0xF488 +#define SSIOCTR 0xF48A + +/* CHIP SELECT UNIT Registers */ +#define CS0ADL 0xF400 +#define CS0ADH 0xF402 +#define CS0MSKL 0xF404 +#define CS0MSKH 0xF406 +#define CS1ADL 0xF408 +#define CS1ADH 0xF40A +#define CS1MSKL 0xF40C +#define CS1MSKH 0xF40E +#define CS2ADL 0xF410 +#define CS2ADH 0xF412 +#define CS2MSKL 0xF414 +#define CS2MSKH 0xF416 +#define CS3ADL 0xF418 +#define CS3ADH 0xF41A +#define CS3MSKL 0xF41C +#define CS3MSKH 0xF41E +#define CS4ADL 0xF420 +#define CS4ADH 0xF422 +#define CS4MSKL 0xF424 +#define CS4MSKH 0xF426 +#define CS5ADL 0xF428 +#define CS5ADH 0xF42A +#define CS5MSKL 0xF42C +#define CS5MSKH 0xF42E +#define CS6ADL 0xF430 +#define CS6ADH 0xF432 +#define CS6MSKL 0xF434 +#define CS6MSKH 0xF436 +#define UCSADL 0xF438 +#define UCSADH 0xF43A +#define UCSMSKL 0xF43C +#define UCSMSKH 0xF43E + +/* REFRESH CONTROL UNIT Registers */ + +#define RFSBAD 0xF4A0 +#define RFSCIR 0xF4A2 +#define RFSCON 0xF4A4 +#define RFSADD 0xF4A6 + +/* POWER MANAGEMENT CONTROL Registers */ + +#define PWRCON 0xF800 +#define CLKPRS 0xF804 + +/* DMA UNIT REGISTERS -- SLOT 15 ADDRESSES */ +#define DMA0TAR 0xF000 +#define DMA0BYC 0xF001 +#define DMA1TAR 0xF002 +#define DMA1BYC 0xF003 +#define DMACMD1 0xF008 +#define DMASTS 0xF008 +#define DMASRR 0xF009 +#define DMAMSK 0xF00A +#define DMAMOD1 0xF00B +#define DMACLRBP 0xF00C +#define DMACLR 0xF00D +#define DMACLRMSK 0xF00E +#define DMAGRPMSK 0xF00F +#define DMA0REQL 0xF010 +#define DMA0REQH 0xF011 +#define DMA1REQL 0xF012 +#define DMA1REQH 0xF013 +#define DMABSR 0xF018 +#define DMACHR 0xF019 +#define DMAIS 0xF019 +#define DMACMD2 0xF01A +#define DMAMOD2 0xF01B +#define DMAIEN 0xF01C +#define DMAOVFE 0xF01D +#define DMACLRTC 0xF01E +#define DMA1TARPL 0xF083 +#define DMA1TARPH 0xF085 +#define DMA0TARPH 0xF086 +#define DMA0TARPL 0xF087 +#define DMA0BYCH 0xF098 +#define DMA1BYCH 0xF099 + +/* DMA UNIT REGISTERS -- SLOT 0 ADDRESSES */ +#define DMA0TARDOS 0x0000 +#define DMA0BYCDOS 0x0001 +#define DMA1TARDOS 0x0002 +#define DMA1BYCDOS 0x0003 +#define DMACMD1DOS 0x0008 +#define DMASTSDOS 0x0008 +#define DMASRRDOS 0x0009 +#define DMAMSKDOS 0x000A +#define DMAMOD1DOS 0x000B +#define DMACLRBPDOS 0x000C +#define DMACLRDOS 0x000D +#define DMACLRMSKDOS 0x000E +#define DMAGRPMSKDOS 0x000F +#define DMA1TARPLDOS 0x0083 +#define DMA0TARPLDOS 0x0087 + +/* A20GATE AND FAST CPU RESET -- SLOT 15 ADDRESS */ +#define PORT92 0xF092 +/* A20GATE AND FAST CPU RESET -- SLOT 0 ADDRESS */ +#define PORT92DOS 0x0092 + +/* end of include file */ diff --git a/c/src/lib/libbsp/i386/i386ex/start/80386ex.inc b/c/src/lib/libbsp/i386/i386ex/start/80386ex.inc new file mode 100644 index 0000000000..798dda4215 --- /dev/null +++ b/c/src/lib/libbsp/i386/i386ex/start/80386ex.inc @@ -0,0 +1,252 @@ +/* + * Submitted by: + * + * Erik Ivanenko + * University of Toronto + * erik.ivanenko@utoronto.ca + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +/* REMAP ADDRESSING Registers */ +.set REMAPCFGH , 0x0023 +.set REMAPCFGL , 0x0022 +.set REMAPCFG , 0x0022 +/* INTERRUPT CONTROL REGISTERS -- SLOT 15 ADDRESSES */ +.set ICW1M , 0xF020 +.set ICW1S , 0xF0A0 +.set ICW2M , 0xF021 +.set ICW2S , 0xF0A1 +.set ICW3M , 0xF021 +.set ICW3S , 0xF0A1 +.set ICW4M , 0xF021 +.set ICW4S , 0xF0A1 +.set OCW1M , 0xF021 +.set OCW1S , 0xF0A1 +.set OCW2M , 0xF020 +.set OCW2S , 0xF0A0 +.set OCW3M , 0xF020 +.set OCW3S , 0xF0A0 +/* INTERRUPT CONTROL REGISTERS -- SLOT 0 ADDRESSES */ +.set ICW1MDOS , 0x0020 +.set ICW1SDOS , 0x00A0 +.set ICW2MDOS , 0x0021 +.set ICW2SDOS , 0x00A1 +.set ICW3MDOS , 0x0021 +.set ICW3SDOS , 0x00A1 +.set ICW4MDOS , 0x0021 +.set ICW4SDOS , 0x00A1 +.set OCW1MDOS , 0x0021 +.set OCW1SDOS , 0x00A1 +.set OCW2MDOS , 0x0020 +.set OCW2SDOS , 0x00A0 +.set OCW3MDOS , 0x0020 +.set OCW3SDOS , 0x00A0 + + +/* CONFIGURATION Registers */ +.set DMACFG , 0xF830 +.set INTCFG , 0xF832 +.set TMRCFG , 0xF834 +.set SIOCFG , 0xF836 +.set P1CFG , 0xF820 +.set P2CFG , 0xF822 +.set P3CFG , 0xF824 +.set PINCFG , 0xF826 + +/* WATCHDOG TIMER Registers */ +.set WDTRLDH , 0xF4C0 +.set WDTRLDL , 0xF4C2 +.set WDTCNTH , 0xF4C4 +.set WDTCNTL , 0xF4C6 +.set WDTCLR , 0xF4C8 +.set WDTSTATUS , 0xF4CA + +/* TIMER CONTROL REGISTERS -- SLOT 15 ADDRESSES */ +.set TMR0 , 0xF040 +.set TMR1 , 0xF041 +.set TMR2 , 0xF042 +.set TMRCON , 0xF043 +/* TIMER CONTROL REGISTERS -- SLOT 0 ADDRESSES */ +.set TMR0DOS , 0x0040 +.set TMR1DOS , 0x0041 +.set TMR2DOS , 0x0042 +.set TMRCONDOS , 0x0043 + +/* INPUT/OUTPUT PORT UNIT Registers */ +.set P1PIN , 0xF860 +.set P1LTC , 0xF862 +.set P1DIR , 0xF864 +.set P2PIN , 0xF868 +.set P2LTC , 0xF86A +.set P2DIR , 0xF86C +.set P3PIN , 0xF870 +.set P3LTC , 0xF872 +.set P3DIR , 0xF874 + +/* ASYNCHRONOUS SERIAL CHANNEL 0 -- SLOT 15 ADDRESSES */ +.set RBR0 , 0xF4F8 +.set THR0 , 0xF4F8 +.set TBR0 , 0xF4F8 +.set DLL0 , 0xF4F8 +.set IER0 , 0xF4F9 +.set DLH0 , 0xF4F9 +.set IIR0 , 0xF4FA +.set LCR0 , 0xF4FB +.set MCR0 , 0xF4FC +.set LSR0 , 0xF4FD +.set MSR0 , 0xF4FE +.set SCR0 , 0xF4FF +/* ASYNCHRONOUS SERIAL CHANNEL 0 -- SLOT 0 ADDRESSES */ +.set RBR0DOS , 0x03F8 +.set THR0DOS , 0x03F8 +.set TBR0DOS , 0x03F8 +.set DLL0DOS , 0x03F8 +.set IER0DOS , 0x03F9 +.set DLH0DOS , 0x03F9 +.set IIR0DOS , 0x03FA +.set LCR0DOS , 0x03FB +.set MCR0DOS , 0x03FC +.set LSR0DOS , 0x03FD +.set MSR0DOS , 0x03FE +.set SCR0DOS , 0x03FF + +/* ASYNCHRONOUS SERIAL CHANNEL 1 -- SLOT 15 ADDRESSES */ +.set RBR1 , 0xF8F8 +.set THR1 , 0xF8F8 +.set TBR1 , 0XF8F8 +.set DLL1 , 0xF8F8 +.set IER1 , 0xF8F9 +.set DLH1 , 0xF8F9 +.set IIR1 , 0xF8FA +.set LCR1 , 0xF8FB +.set MCR1 , 0xF8FC +.set LSR1 , 0xF8FD +.set MSR1 , 0xF8FE +.set SCR1 , 0xF8FF +/* ASYNCHRONOUS SERIAL CHANNEL 1 -- SLOT 0 ADDRESSES */ +.set RBR1DOS , 0x02F8 +.set THR1DOS , 0x02F8 +.set TBR1DOS , 0x02F8 +.set DLL1DOS , 0x02F8 +.set IER1DOS , 0x02F9 +.set DLH1DOS , 0x02F9 +.set IIR1DOS , 0x02FA +.set LCR1DOS , 0x02FB +.set MCR1DOS , 0x02FC +.set LSR1DOS , 0x02FD +.set MSR1DOS , 0x02FE +.set SCR1DOS , 0x02FF + +/* SYNCHRONOUS SERIAL CHANNEL REGISTERS */ +.set SSIOTBUF , 0xF480 +.set SSIORBUF , 0xF482 +.set SSIOBAUD , 0xF484 +.set SSIOCON1 , 0xF486 +.set SSIOCON2 , 0xF488 +.set SSIOCTR , 0xF48A + +/* CHIP SELECT UNIT Registers */ +.set CS0ADL , 0xF400 +.set CS0ADH , 0xF402 +.set CS0MSKL , 0xF404 +.set CS0MSKH , 0xF406 +.set CS1ADL , 0xF408 +.set CS1ADH , 0xF40A +.set CS1MSKL , 0xF40C +.set CS1MSKH , 0xF40E +.set CS2ADL , 0xF410 +.set CS2ADH , 0xF412 +.set CS2MSKL , 0xF414 +.set CS2MSKH , 0xF416 +.set CS3ADL , 0xF418 +.set CS3ADH , 0xF41A +.set CS3MSKL , 0xF41C +.set CS3MSKH , 0xF41E +.set CS4ADL , 0xF420 +.set CS4ADH , 0xF422 +.set CS4MSKL , 0xF424 +.set CS4MSKH , 0xF426 +.set CS5ADL , 0xF428 +.set CS5ADH , 0xF42A +.set CS5MSKL , 0xF42C +.set CS5MSKH , 0xF42E +.set CS6ADL , 0xF430 +.set CS6ADH , 0xF432 +.set CS6MSKL , 0xF434 +.set CS6MSKH , 0xF436 +.set UCSADL , 0xF438 +.set UCSADH , 0xF43A +.set UCSMSKL , 0xF43C +.set UCSMSKH , 0xF43E + +/* REFRESH CONTROL UNIT Registers */ + +.set RFSBAD , 0xF4A0 +.set RFSCIR , 0xF4A2 +.set RFSCON , 0xF4A4 +.set RFSADD , 0xF4A6 + +/* POWER MANAGEMENT CONTROL Registers */ + +.set PWRCON , 0xF800 +.set CLKPRS , 0xF804 + +/* DMA UNIT REGISTERS -- SLOT 15 ADDRESSES */ +.set DMA0TAR , 0xF000 +.set DMA0BYC , 0xF001 +.set DMA1TAR , 0xF002 +.set DMA1BYC , 0xF003 +.set DMACMD1 , 0xF008 +.set DMASTS , 0xF008 +.set DMASRR , 0xF009 +.set DMAMSK , 0xF00A +.set DMAMOD1 , 0xF00B +.set DMACLRBP , 0xF00C +.set DMACLR , 0xF00D +.set DMACLRMSK , 0xF00E +.set DMAGRPMSK , 0xF00F +.set DMA0REQL , 0xF010 +.set DMA0REQH , 0xF011 +.set DMA1REQL , 0xF012 +.set DMA1REQH , 0xF013 +.set DMABSR , 0xF018 +.set DMACHR , 0xF019 +.set DMAIS , 0xF019 +.set DMACMD2 , 0xF01A +.set DMAMOD2 , 0xF01B +.set DMAIEN , 0xF01C +.set DMAOVFE , 0xF01D +.set DMACLRTC , 0xF01E +.set DMA1TARPL , 0xF083 +.set DMA1TARPH , 0xF085 +.set DMA0TARPH , 0xF086 +.set DMA0TARPL , 0xF087 +.set DMA0BYCH , 0xF098 +.set DMA1BYCH , 0xF099 + +/* DMA UNIT REGISTERS -- SLOT 0 ADDRESSES */ +.set DMA0TARDOS , 0x0000 +.set DMA0BYCDOS , 0x0001 +.set DMA1TARDOS , 0x0002 +.set DMA1BYCDOS , 0x0003 +.set DMACMD1DOS , 0x0008 +.set DMASTSDOS , 0x0008 +.set DMASRRDOS , 0x0009 +.set DMAMSKDOS , 0x000A +.set DMAMOD1DOS , 0x000B +.set DMACLRBPDOS , 0x000C +.set DMACLRDOS , 0x000D +.set DMACLRMSKDOS , 0x000E +.set DMAGRPMSKDOS , 0x000F +.set DMA1TARPLDOS , 0x0083 +.set DMA0TARPLDOS , 0x0087 + +/* A20GATE AND FAST CPU RESET -- SLOT 15 ADDRESS */ +.set PORT92 , 0xF092 +/* A20GATE AND FAST CPU RESET -- SLOT 0 ADDRESS */ +.set PORT92DOS , 0x0092 diff --git a/c/src/lib/libbsp/i386/i386ex/start/Makefile.in b/c/src/lib/libbsp/i386/i386ex/start/Makefile.in new file mode 100644 index 0000000000..388e25b482 --- /dev/null +++ b/c/src/lib/libbsp/i386/i386ex/start/Makefile.in @@ -0,0 +1,57 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH = @srcdir@ +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +PGMS=${ARCH}/start.o + +# C source names, if any, go here -- minus the .c +C_PIECES= +C_FILES=$(C_PIECES:%=%.c) +C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) + +H_FILES= + +# Assembly source names, if any, go here -- minus the .s +S_PIECES=start +S_FILES=$(S_PIECES:%=%.s) +S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) + +SRCS=$(C_FILES) $(H_FILES) $(S_FILES) +OBJS=$(C_O_FILES) $(S_O_FILES) + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += +CPPFLAGS += +CFLAGS += + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +all: ${ARCH} $(SRCS) $(OBJS) $(PGM) + $(INSTALL_VARIANT) -m 555 ${PGMS} ${PROJECT_RELEASE}/lib + +# Install the program(s), appending _g or _p as appropriate. +# for include files, just use $(INSTALL) diff --git a/c/src/lib/libbsp/i386/i386ex/start/macros.inc b/c/src/lib/libbsp/i386/i386ex/start/macros.inc new file mode 100644 index 0000000000..53016ad62a --- /dev/null +++ b/c/src/lib/libbsp/i386/i386ex/start/macros.inc @@ -0,0 +1,115 @@ +/* macros.inc + * + * This file assists the board independent startup code + * by initializing the chip-select channels to + * reflect the proper memory configuration. + * + * NOTE: No stack has been established when this routine + * is invoked. It returns to start.s through ldsegs + * + * Submitted by: + * + * Erik Ivanenko + * University of Toronto + * erik.ivanenko@utoronto.ca + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +.set GDT_CODE_PTR , 0x10 +.set GDT_DATA_PTR , 0x18 + +.set BOARD_SELECT , 0x301 +.set BOARD_DATA , 0x302 +.set BOARD_LATCH , 0x303 + + +#define SetExRegByte(_register,_value) \ + movb $ ## _value, al; \ + movw $ ## _register, dx; \ + outb al, dx + +#define SetExRegWord(_register,_value) \ + movw $ ## _value, ax; \ + movw $ ## _register, dx ; \ + outw ax, dx + + +#define DESC2(lim_0_15, bas_0_15, bas_16_23, access, gran, bas_24_31) \ + .word lim_0_15 ; \ + .word bas_0_15 ; \ + .byte bas_16_23 ; \ + .byte access ; \ + .byte gran ; \ + .byte bas_24_31 + +#define DESC3( _base, _limit) \ +.word _limit ; \ +.long _base + +/* THE GET_ACCESS IS CHANGED FROM 8E TO 9E */ + +#define INTERRUPT_GATE( _vector ) \ + .word _vector ; \ + .word GDT_CODE_PTR ; \ + .byte 0x0 ; \ + .byte 0x8E ; \ + .word 0x0 + +#define rLOAD_INDEX( _selector, _segment_register) \ + movl _selector , _segment_register ; \ + addb al, ( eax ) + +#define rLOAD_SEGMENT( _reg, _segment_register) \ + mov _reg , _segment_register ; \ + +/* #define rLOAD_SEGMENT( _reg, _segment_register) \ + .code16 ; \ + mov _reg , _segment_register ; \ + .code32 +*/ +#define pLOAD_SEGMENT( _selector, _segment_register) \ + movl $ ## _selector , eax ; .code16 ; \ + mov ax, _segment_register ; .code32 + +/* #define MOVE_WORD( _immed32, _reg ) \ + data16 ; \ + movl _immed32, _reg +*/ + +#define MOVE_WORD( _immed32, _reg ) \ + movw _immed32, _reg + +/* #define MOVE_IMMED_WORD( _immed32, _reg ) \ + data16 ; \ + mov $ ## _immed32, _reg + +#define CS_OFF( _cs_symbol, _reg ) \ + data16 ; \ + mov _cs_symbol, _reg ; \ + data16 ;\ + andl $0x000ffff, _reg + +#define _16_NOPS \ + nop ; \ + nop ; \ + nop ; \ + nop ; \ + nop ; \ + nop ; \ + nop ; \ + nop ; \ + nop ; \ + nop ; \ + nop ; \ + nop ; \ + nop ; \ + nop ; \ + nop ; \ + nop ; +*/ + diff --git a/c/src/lib/libbsp/i386/i386ex/start/start.s b/c/src/lib/libbsp/i386/i386ex/start/start.s new file mode 100644 index 0000000000..51bbea97d4 --- /dev/null +++ b/c/src/lib/libbsp/i386/i386ex/start/start.s @@ -0,0 +1,572 @@ +/* + * This file is the main boot and configuration file for the i386ex. It is + * solely responsible for initializing the internal register set to reflect + * the proper board configuration. This version is the "generic" i386ex + * startup: + * + * 1) 512K flask ROM @3f80000 + * 2) 1 Mb RAM @ 0x0 + * 3) Timer0 used as RTEMS clock ticker, 1 msec tick rate. + * 4) READY# is generated by CPU + * + * The file is a multi-section file, with sections as follows: + * 1) interrupt gates, in section "ints" + * 2) interrupt descriptor table, in section "idt" + * 3) global descriptor table, in section "gdt" + * 4) reset in section "reset" + * 5) and initial boot code in section " initial" + * + * Submitted by: + * + * Erik Ivanenko + * University of Toronto + * erik.ivanenko@utoronto.ca + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include "asm.h" +#include "macros.inc" +#include "80386ex.inc" + + + EXTERN (main) /* exits to bspstart */ + EXTERN (stack_start) /* defined in startup/linkcmds */ + + .section .idt + +BEGIN_DATA + PUBLIC (Interrupt_descriptor_table) + PUBLIC(SYM(IDTR) ) +SYM(IDTR): DESC3( SYM(IDT), 0x188 ); +SYM (Interrupt_descriptor_table): +SYM(IDT): +SYM(GATE_DIVIDE_ERROR): INTERRUPT_GATE( DIVIDE_ERROR ); +SYM(GATE_DEBUG_EXCEPTION): INTERRUPT_GATE( DEBUG_EXCEPTION ); +SYM(GATE_NMI_INTERRUPT): INTERRUPT_GATE( NMI_INTERRUPT ); +SYM(GATE_BREAKPOINT): INTERRUPT_GATE( BREAKPOINT ); +SYM(GATE_INTO_OVERFLOW ): INTERRUPT_GATE( INTO_OVERFLOW ); +SYM(GATE_BOUND_EXCEEDED ): INTERRUPT_GATE( BOUND_EXCEEDED ); +SYM(GATE_INVALID_OPCODE ): INTERRUPT_GATE( INVALID_OPCODE ); +SYM(GATE_COPRO_NA ): INTERRUPT_GATE( COPRO_NA ); +SYM(GATE_DOUBLE_FAULT ): INTERRUPT_GATE( DOUBLE_FAULT ); +SYM(GATE_COPRO_SEG_OVERRUN ): INTERRUPT_GATE( COPRO_SEG_OVERRUN ); +SYM(GATE_INVALID_TSS ): INTERRUPT_GATE( INVALID_TSS ); +SYM(GATE_SEGMENT_NOT_PRESENT ): INTERRUPT_GATE( SEGMENT_NOT_PRESENT ); +SYM(GATE_STACK_FAULT ): INTERRUPT_GATE( STACK_FAULT ); +SYM(GATE_GPF ): INTERRUPT_GATE( GPF ); +SYM(GATE_PAGE_FAULT ): INTERRUPT_GATE( PAGE_FAULT ); +SYM(GATE_RESERVED_1 ): INTERRUPT_GATE( RESERVED ); +SYM(GATE_COPRO_ERROR ): INTERRUPT_GATE( COPRO_ERROR ); +SYM(GATE_RESERVED_17): INTERRUPT_GATE( RESERVED_17 ); +SYM(GATE_RESERVED_18): INTERRUPT_GATE( RESERVED_18 ); +SYM(GATE_RESERVED_19): INTERRUPT_GATE( RESERVED_19 ); +SYM(GATE_RESERVED_20): INTERRUPT_GATE( RESERVED_20 ); +SYM(GATE_RESERVED_21): INTERRUPT_GATE( RESERVED_21 ); +SYM(GATE_RESERVED_22): INTERRUPT_GATE( RESERVED_22 ); +SYM(GATE_RESERVED_23): INTERRUPT_GATE( RESERVED_23 ); +SYM(GATE_RESERVED_24): INTERRUPT_GATE( RESERVED_24 ); +SYM(GATE_RESERVED_25): INTERRUPT_GATE( RESERVED_25 ); +SYM(GATE_RESERVED_26): INTERRUPT_GATE( RESERVED_26 ); +SYM(GATE_RESERVED_27): INTERRUPT_GATE( RESERVED_27 ); +SYM(GATE_RESERVED_28): INTERRUPT_GATE( RESERVED_28 ); +SYM(GATE_RESERVED_29): INTERRUPT_GATE( RESERVED_29 ); +SYM(GATE_RESERVED_30): INTERRUPT_GATE( RESERVED_30 ); +SYM(GATE_RESERVED_31): INTERRUPT_GATE( RESERVED_31 ); + +SYM ( GATE_TIMINT0): INTERRUPT_GATE( TIMINT0 ); +SYM ( GATE_MASTER_IR2 ): INTERRUPT_GATE( MASTER_IR2 ); +SYM ( GATE_SIOINT1 ): INTERRUPT_GATE( SIOINT1 ); +SYM ( GATE_SIOINT2 ): INTERRUPT_GATE( SIOINT2 ); +SYM ( GATE_DMAINT ): INTERRUPT_GATE( DMAINT ); +SYM ( GATE_UNUSED_IR5 ): INTERRUPT_GATE( UNUSED_IR5); +SYM ( GATE_UNUSED_IR6 ): INTERRUPT_GATE( UNUSED_IR6); +SYM ( GATE_UNUSED_IR7 ): INTERRUPT_GATE( UNUSED_IR7); +SYM ( GATE_SLAVE_IR0 ): INTERRUPT_GATE( SLAVE_IR0 ); +SYM ( GATE_SLAVE_IR1 ): INTERRUPT_GATE( SLAVE_IR1 ); +SYM ( GATE_SLAVE_IR2 ): INTERRUPT_GATE( SLAVE_IR2 ); +SYM ( GATE_SLAVE_IR3 ): INTERRUPT_GATE( SLAVE_IR3 ); +SYM ( GATE_SLAVE_IR4 ): INTERRUPT_GATE( SLAVE_IR4 ); +SYM ( GATE_SLAVE_IR5 ): INTERRUPT_GATE( SLAVE_IR5 ); +SYM ( GATE_SLAVE_IR6 ): INTERRUPT_GATE( SLAVE_IR6 ); +SYM ( GATE_SLAVE_IR7 ): INTERRUPT_GATE( SLAVE_IR7 ); +END_DATA + + .section .gdt +BEGIN_DATA + PUBLIC (_Global_descriptor_table) + +SYM(GDTR): DESC3( GDT_TABLE, 0x1f ); # one less than the size +SYM (_Global_descriptor_table): +SYM(GDT): +SYM(GDT_TABLE): DESC2(0,0,0,0,0,0); +SYM(GDT_ALIAS): DESC2(32,0x1000,0x0,0x93,0,0x0); +SYM(GDT_CODE): DESC2(0xffff,0,0x0,0x9B,0xDF,0x00); +SYM(GDT_DATA): DESC2(0xffff,0,0x0,0x92,0xDF,0x00); # was CF +SYM(GDT_END): + +END_DATA + + +/* This section is the section that is used by the interrupt + descriptor table. It is used to provide the IDT with the + correct vector offsets. It is for symbol definition only. +*/ + + .section .ints + +SYM(INTERRUPT_HANDLERS): +SYM(DIVIDE_ERROR): jmp SYM(DIVIDE_ERROR) +SYM(DEBUG_EXCEPTION): jmp SYM(DEBUG_EXCEPTION) +SYM(NMI_INTERRUPT): jmp SYM(NMI_INTERRUPT) +SYM(BREAKPOINT): jmp SYM(BREAKPOINT) +SYM(INTO_OVERFLOW): jmp SYM(INTO_OVERFLOW) +SYM(BOUND_EXCEEDED): jmp SYM(BOUND_EXCEEDED) +SYM(INVALID_OPCODE): jmp SYM(INVALID_OPCODE) +SYM(COPRO_NA): jmp SYM(COPRO_NA) +SYM(DOUBLE_FAULT): jmp SYM(DOUBLE_FAULT) +SYM(COPRO_SEG_OVERRUN): jmp SYM(COPRO_SEG_OVERRUN) +SYM(INVALID_TSS): jmp SYM(INVALID_TSS) +SYM(RESERVED): JMP SYM(RESERVED) +SYM(COPRO_ERROR): JMP SYM(COPRO_ERROR) +SYM(PAGE_FAULT): JMP SYM(PAGE_FAULT) +SYM(GPF): JMP SYM(GPF) +SYM(STACK_FAULT): JMP SYM(STACK_FAULT) +SYM(SEGMENT_NOT_PRESENT): jmp SYM(SEGMENT_NOT_PRESENT) +SYM(RESERVED_17): jmp SYM(RESERVED_17) +SYM(RESERVED_18): jmp SYM(RESERVED_18) +SYM(RESERVED_19): jmp SYM(RESERVED_19) +SYM(RESERVED_20): jmp SYM(RESERVED_20) +SYM(RESERVED_21): jmp SYM(RESERVED_21) +SYM(RESERVED_22): jmp SYM(RESERVED_22) +SYM(RESERVED_23): jmp SYM(RESERVED_23) +SYM(RESERVED_24): jmp SYM(RESERVED_24) +SYM(RESERVED_25): jmp SYM(RESERVED_25) +SYM(RESERVED_26): jmp SYM(RESERVED_26) +SYM(RESERVED_27): jmp SYM(RESERVED_27) +SYM(RESERVED_28): jmp SYM(RESERVED_28) +SYM(RESERVED_29): jmp SYM(RESERVED_29) +SYM(RESERVED_30): jmp SYM(RESERVED_30) +SYM(RESERVED_31): jmp SYM(RESERVED_31) +SYM(TIMINT0): nop; iret +SYM(MASTER_IR2): jmp SYM(MASTER_IR2) +SYM(SIOINT1): jmp SYM(SIOINT1) +SYM(SIOINT2): jmp SYM(SIOINT2) +SYM(DMAINT): jmp SYM(DMAINT) +SYM(UNUSED_IR5): jmp SYM(UNUSED_IR5) +SYM(UNUSED_IR6): JMP SYM(UNUSED_IR6) +SYM(UNUSED_IR7): JMP SYM(UNUSED_IR7) +SYM(SLAVE_IR0): JMP SYM(SLAVE_IR0) +SYM(SLAVE_IR1): JMP SYM(SLAVE_IR1) +SYM(SLAVE_IR2): nop; iret +SYM(SLAVE_IR3): JMP SYM(SLAVE_IR3) +SYM(SLAVE_IR4): JMP SYM(SLAVE_IR4) +SYM(SLAVE_IR5): JMP SYM(SLAVE_IR5) +SYM(SLAVE_IR6): JMP SYM(SLAVE_IR6) +SYM(SLAVE_IR7): JMP SYM(SLAVE_IR7) + + PUBLIC( SYM(_initInternalRegisters) ) + + + .section .reset + + PUBLIC ( SYM(reset) ) +SYM(reset): + .code16 + nop + cli + jmp SYM(_initInternalRegisters) /* different section in this file */ + .code32 /* in case this section moves */ + nop /* required by CHIP LAB to pad out size */ + nop + nop + nop + nop + + .section .initial + +/* + * Enable access to peripheral register at expanded I/O addresses + */ + .code16 +SYM(_initInternalRegisters): + movw $0x8000 , ax + outb al , $REMAPCFGH + xchg al , ah + outb al,$REMAPCFGL + outw ax, $REMAPCFG ; + + +/* + * Configure operation of the A20 Address Line + */ +SYM(A20): + movw $PORT92 , dx + + inb dx , al # clear A20 port reset + andb $0xfe , al # b0 Fast Reset(0)=disabled,(1)=reset triggered + orb $0x02 , al # Bit 1 Fast A20 = 0 (always 0) else enabled. + outb al , dx + +SYM(Watchdog): + SetExRegByte( WDTSTATUS, 0x01 ) # disable watchdog timer + +/* + * Initialize Refresh Control Unit for: + * Refresh Address = 0x0000 + + * Refresh gate between rows is 15.6 uSec + * Using a CLK2 frequency of 50Mhz ( 25Mhz CPU ) + * The refresh unit is enabled + * The refresh pin is not used. + */ + +SYM(InitRCU): + SetExRegWord( RFSCIR , 390) # refresh interval was 390, tried 312 + SetExRegWord( RFSBAD , 0x0) # base address + SetExRegWord( RFSADD , 0x0) # address register + SetExRegWord( RFSCON , 0x8000) # enable bit + +/* + * Initialize clock and power mgmt unit for: + * Clock Frequency = 50 Mhz + * Prescaled clock output = 1.19318 Mhz + * ( matches standard PC ) + * Normal halt instructions + */ + +SYM(InitClk): + SetExRegByte( PWRCON, 0x0 ) + SetExRegWord( CLKPRS, 0x13) + +/************************************************************** + * Initialize the Pin Configurations + *************************************************************/ + +/* + * Initialize I/O port 1 for: + * PIN 0 = 1, DCD0# to package pin + * PIN 1 = 1, RTS0# to package pin + * PIN 2 = 1, DTR0# to package pin + * PIN 3 = 1, DSR0# to package pin + * PIN 4 = 1, RI0# to package pin + * PIN 5 = 0, Outport (FLASH Vpp Enable, 0=Enable 1=Disable) + * PIN 6 = 0, Outport (P16_HOLD to 386ex option header JP7 pin 5) + * PIN 7 = 0, Outport (P17_HOLD to 386ex option header JP7 pin 3) + */ + +SYM(InitPort1): + SetExRegByte( P1LTC , 0xff ) + SetExRegByte( P1DIR , 0x0 ) + SetExRegByte( P1CFG , 0x1f) + +/* + * Initialize I/O port 2 for: + * PIN 0 = 0, Outport (P20_CS0# to 386ex option header JP7 pin 11) + * PIN 1 = 0, Outport (P21_CS1# to 386ex option header JP7 pin 9) + * PIN 2 = 1, CS2# (SMRAM) If not using CS2 can be configured as.? + * PIN 3 = 0, Outport ( no connect ) + * PIN 4 = 1, CS#4 (DRAM) + * PIN 5 = 1, RXD0 input. See not for I/0 port 1 pins 1-4 + * PIN 6 = 1, TXD0 output. + * PIN 7 = 1, CTS0# input. + */ + +SYM(InitPort2): + SetExRegByte( P2LTC , 0xff ) + SetExRegByte( P2DIR , 0x0 ) + SetExRegByte( P2CFG , 0xfe) + +/* + * Initialize I/O port 3 P3CFG + * PIN 0 = 1, TMROUT0 to package pin + * PIN 1 = 0, (TMROUT1 to 386ex option header JP7 pin 23) + * PIN 2 = 0, INT0 (IR1) disabled, (P3.2 out to JP7 pin 21) + * PIN 3 = 0, INT1 (IR5) disbled (P3.3 to option header JP7 pin 19) + * PIN 4 = 0, INT2 (IR6) disbled (P3.4 to option header JP7 pin 17) + * PIN 5 = 0, INT2 (IR7) disabled (P3.5 to 386ex header JP7 pin 15) + * PIN 6 = 0, Inport (Debugger Break P3.6/PWRD to package pin ) + * P3.6 selected + * PIN 7 = 0, COMCLK output disabled, 1.8432 Mhz OSC1 oscillator. + * ( Debbugger uses COMCLK as the clocking source ) + * P3.7 connected to package pin. + */ + +SYM(InitPort3): + SetExRegByte( P3LTC , 0xff ) + SetExRegByte( P3DIR , 0x41 ) + SetExRegByte( P3CFG , 0x09 ) # can check TMROUT0 +/* + * Initialize Peripheral Pin Configurations: + * PIN 0 = 1, RTS1# to package pin + * PIN 1 = 1, DTR1# to package pin + * PIN 2 = 1, TXD1 out to package pin + * PIN 3 = 0, EOP#/TC + * PIN 4 = 0, DACK0# + * PIN 5 = 1, Timer2 + * PIN 6 = 0, 0 => CS6# connected to package pin + * PIN 7 = 0, Don't care + */ + +SYM(InitPeriph): + SetExRegByte( PINCFG , 0x24) + +/* + * Initialize the Asynchronous Serial Ports: + * BIT 7 = 1, Internal SIO1 modem signals + * BIT 6 = 1, Internal SIO0 modem signals + * BIT 2 = 0, PSCLK for SSIO clock + * BIT 1 = 1, SERCLK for SIO1 clock + * BIT 0 = 1, SERCLK for SIO0 clock + */ + +SYM(InitSIO): + SetExRegByte( SIOCFG, 0xC3 ) # SIOn clocked internally + + SetExRegByte( LCR0, 0x80 ) # latch DLL0, DLH0 + SetExRegByte( DLL0, 0x51 ) # 0x51 sets to 9600 baud 0x7 -> 115,200 + SetExRegByte( DLH0, 0x00 ) # 0x145 is 2400 baud + SetExRegByte( LCR0, 0x03 ) # enable r/w buffers, IER0 accessible + # mode 8-n-1 + SetExRegByte( IER0, 0x00 ) # was 0x0f All interrupts detected + + SetExRegByte( LCR1, 0x80 ) # latch DLL0, DLH0 + SetExRegByte( DLL1, 0x51 ) # 0x51 set to 9600 baud, 0x7 = 115200 + SetExRegByte( DLH1, 0x00 ) # 0x145 is 2400 baud + SetExRegByte( LCR1, 0x03 ) # enable r/w buffers, IER1 accessible + # reg 8-n-1 + SetExRegByte( IER1, 0x00 ) # was 0x0f - All interrupts detected + +SYM(InitMCR): +/* + * Initialize Timer for: + * BIT 7 = 1, Timer clocks disabled + * BIT 6 = 0, Reserved + * BIT 5 = 1, TMRCLK2 instead of Vcc to Gate2 + * BIT 4 = 0, PSCLK to CLK2 + * BIT 3 = 1, TMRCLK1 instead of Vcc to Gate1 + * BIT 2 = 0, PSCLK to Gate1 + * BIT 1 = 0, Vcc to Gate0 + * BIT 0 = 0, PSCLK to Gate0 + */ + +SYM(InitTimer): + SetExRegByte(TMRCFG , 0x80 ) # All counters disabled, Gates 0,1 + # and 2 are set to Vcc + + SetExRegByte(TMRCON , 0x34 ) # prepare to write counter 0 LSB,MSB + SetExRegByte(TMR0 , 0xA8 ) # LSB = 0B count, followed by MSB + SetExRegByte(TMR0 , 0x04 ) # for INT every 50 msec. MSB = 0xE900 + # for INT every 5 msec. 0x174c + # for INT every 1 msec. 0x04A8 + # was 0xe900 + + SetExRegByte(TMRCON , 0x70 ) # mode 0 disables on Gate= Vcc + SetExRegByte(TMR1 , 0x00 ) # sfa + SetExRegByte(TMR1 , 0x00 ) # sfa + + SetExRegByte(TMRCON , 0xB0 ) # mode 0 disables on gate =Vcc + SetExRegByte(TMR2 , 0x00 ) # + SetExRegByte(TMR2 , 0x00 ) # + SetExRegByte(TMRCFG , 0x80 ) # Enable timers = 0x00 + + +/* + * Initialize the DMACFG register for: + * BIT 7 = 1 , Disable DACK#1 + * BITs 6:4 = 100, TMROUT2 connected to DRQ1 + * BIT 3 = 1 , Disable DACK0# + * BIT 2:0 = 000, Pin is connected to DRQ0 + */ + + SetExRegByte(DMACFG , 0xC0 ) + SetExRegByte(DMACMD1, 0x00 ) # disable both DMA channels + SetExRegByte(DMAMOD1, 0x40 ) +/* + * Initialize the INTCFG register for: + * BIT 7 = 0, 8259 cascade disabled + * BIT 3 = 0, SLAVE IR6 connected to Vss + * BIT 2 = 0, SLAVE IR5 connected to Vss + * BIT 1 = 0, SLAVE IR1 connected to SSIOINT + * BIT 0 = 0, SLAVE IR0 connected to Vss + */ + +SYM(InitInt): + + cli # ! + + SetExRegByte(ICW1S , 0x11 ) # EDGE TRIGGERED + SetExRegByte(ICW2S , 0x28 ) # Slave base vector after Master + SetExRegByte(ICW3S , 0x04 ) # ( was 0x02! )slave cascaded to IR2 on master + SetExRegByte(ICW4S , 0x01 ) # must be 0x01 + + SetExRegByte(ICW1M , 0x11 ) # edge triggered + SetExRegByte(ICW2M , 0x20 ) # base vector starts at byte 32 + SetExRegByte(ICW3M , 0x04 ) # IR2 is cascaded internally + SetExRegByte(ICW4M , 0X03 ) # AEOI MODE FIRST! + + SetExRegByte(OCW1M , 0xde ) # IR0 only = 0xfe. for IR5 and IR0 active use 0xde + SetExRegByte(INTCFG , 0x00 ) + +SYM(SetCS4): + SetExRegWord(CS4ADL , 0x702) #Configure chip select 4 + SetExRegWord(CS4ADH , 0x00) + SetExRegWord(CS4MSKH, 0x03F) + SetExRegWord(CS4MSKL, 0xFC01) + +SYM(SetUCS1): + SetExRegWord(UCSADL , 0x0304) # 512K block starting at 0x80000 until 0x3f80000 + SetExRegWord(UCSADH , 0x03F8) + SetExRegWord(UCSMSKH, 0x03F7) + SetExRegWord(UCSMSKL, 0xFC01) # configure upper chip select + +SYM(xfer_idt): + movw $ _ram_idt_offset , di + movw $ _ram_idt_segment , cx + mov cx, es + + movw $ _rom_idt_offset , si + movw $ _rom_idt_segment , ax + mov ax , ds + + movw $ _idt_size , cx + + repne + movsb + +SYM(xfer_ints): + + movw $ _ram_ints_offset , di + movw $ _ram_ints_segment , ax + mov ax , es + + movw $ _rom_ints_offset , si + movw $ _rom_ints_segment, ax + mov ax , ds + + movw $ _ints_size , cx + + repne + movsb + +SYM(lidt): + movw $ _ram_idt_offset , di + movw $ 0x0 , si + + movw $ _ram_idt_segment , ax + + mov ax , ds + lidt _ram_idt_offset +SYM(xfer_gdt): + movw $ _ram_gdt_offset , di + movw $ _ram_gdt_segment , cx + mov cx , es + + movw $ _gdt_size , cx + movw $ _rom_gdt_segment , ax + movw $ _rom_gdt_offset , si + mov ax , ds + + repne + movsb + +/***************************** + * Load the Global Descriptor + * Table Register + ****************************/ + + movw $ _ram_gdt_segment, ax + mov ax , ds + + lgdt _ram_gdt_offset # location of GDT + + +SYM(SetUCS): + SetExRegWord(UCSADL, 0x0704) # now 512K starting at 0x3f80000. + SetExRegWord(UCSADH, 0x03f8) + SetExRegWord(UCSMSKH, 0x0007) + SetExRegWord(UCSMSKL, 0xFC01) # configure upper chip select + +/*************************** + * Switch to Protected Mode + ***************************/ + mov %cr0, eax + orw $0x1, ax + mov eax, %cr0 + +/************************** + * Flush prefetch queue, + * and load CS selector + *********************/ + + ljmp $ GDT_CODE_PTR , $ SYM(_copy_data) # sets the code selector +/* + * Copy the data section down to RAM + */ +SYM(_copy_data): + .code32 + pLOAD_SEGMENT( GDT_DATA_PTR, fs) + pLOAD_SEGMENT( GDT_DATA_PTR, gs) + pLOAD_SEGMENT( GDT_DATA_PTR, ss) + pLOAD_SEGMENT( GDT_DATA_PTR, ds) + pLOAD_SEGMENT( GDT_DATA_PTR, es) + + movl $ SYM(_data_start) , edi # ram destination + movl $ SYM(_rom_data_start) , esi # rom data source + movl $ SYM(_edata) , ecx # end of data section + subl $ SYM(_data_start) , ecx # length of data section + # es, ds preloaded + repne # while ecx != 0 + movsb # move a byte + +/* + * Set up the stack + */ + +SYM (_establish_stack): + movl $end, eax # stack starts right after bss +/* movl eax, stack_start # save for brk() routine */ + movl $stack_origin, esp # this is the high starting address + movl $stack_origin, ebp +/* + * Zero out the BSS segment + */ +SYM (zero_bss): + cld # make direction flag count up + movl $ SYM (end),ecx # find end of .bss + movl $ SYM (_bss_start),edi # edi = beginning of .bss + subl edi,ecx # ecx = size of .bss in bytes + shrl ecx # size of .bss in longs + shrl ecx + xorl eax,eax # value to clear out memory + repne # while ecx != 0 + stosl # clear a long in the bss + +/* + * Transfer control to User's Board Support Package + */ + pushl $0 # environp + pushl $0 # argv + pushl $0 # argc + call SYM (main) # does not return + addl $12,esp + +BEGIN_DATA_DCL + +/* .align 2 + PUBLIC (start_frame) +SYM (start_frame): + .long 0 +*/ +/* PUBLIC (stack_start) +SYM (stack_start): + .long 0 +*/ + +END_DATA_DCL + +END diff --git a/c/src/lib/libbsp/i386/i386ex/startup/Makefile.in b/c/src/lib/libbsp/i386/i386ex/startup/Makefile.in index 8042d83b24..b62746f5bd 100644 --- a/c/src/lib/libbsp/i386/i386ex/startup/Makefile.in +++ b/c/src/lib/libbsp/i386/i386ex/startup/Makefile.in @@ -11,17 +11,15 @@ PROJECT_ROOT = @PROJECT_ROOT@ PGM=${ARCH}/startup.rel # C source names, if any, go here -- minus the .c -C_PIECES=bspclean bspstart main sbrk setvec +C_PIECES=bspclean bsppost bspstart main sbrk setvec C_FILES=$(C_PIECES:%=%.c) C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) H_FILES= - # Assembly source names, if any, go here -- minus the .s # removed initcsu piece, ldsegs piece and flush -S_PIECES= gdt idt interrupts interns reset_jmp - +S_PIECES= S_FILES=$(S_PIECES:%=%.s) S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) diff --git a/c/src/lib/libbsp/i386/i386ex/startup/README b/c/src/lib/libbsp/i386/i386ex/startup/README index 6a61b9f3c3..17fde76a91 100644 --- a/c/src/lib/libbsp/i386/i386ex/startup/README +++ b/c/src/lib/libbsp/i386/i386ex/startup/README @@ -3,25 +3,15 @@ # - The doit shell file cd's to $H, which refers to the directory -that contains the hello world test. The console is a raw com port. -Certain test programs behave differently with different com port speeds. -To test the programs, it is required that you hook up a terminal -( or minicom or procomm it doesn't really matter ) to the comm port of -the target hardware. You must ensure that the baud rate, parity etc -is set properly. This is done on the target hardware within interns.s . -( Set your terminal emulator to match. ) Currently, the settings -are 9600,8,n,1 . +The requirements for this BSP are only that the GAS used supports the +.code16 directive. The GAS released with any GCC version 2.8.0 or better +is required. The BSP was built with an egcs snapshot pre-1.0.2 and +post-1.0.1. However, any egcs should work. -The format and layout of the file interns.s is taken from the -intel ApBuilder software, freely distributed by Intel. Some -easy macros ( SetExRegByte and SetExRegWord ) are basically lifted -from the Intel macros. Similarly for the names of the IO ports. -This "port" begain with the forceCPU bsp. Hence I am sure that -there is some real trash that is not appropriate. For example -the act of copying the Interrupt Descriptor tables and Global -descriptor tables "into our space". ( in start.s I think ) +The only "real" differences are in bspstart.c, where the initialization now +configures all available RAM, (after setting up the Workspaces) as heap. +The location of the stack was changed so that the heap was not trapped +between low memory and the stack; the stack comes before the heap. -Erik diff --git a/c/src/lib/libbsp/i386/i386ex/startup/bspstart.c b/c/src/lib/libbsp/i386/i386ex/startup/bspstart.c index 77bba61cf3..5022148c06 100644 --- a/c/src/lib/libbsp/i386/i386ex/startup/bspstart.c +++ b/c/src/lib/libbsp/i386/i386ex/startup/bspstart.c @@ -1,14 +1,9 @@ -/* bsp_start() - * +/* * This routine starts the application. It includes application, * board, and monitor specific initialization and configuration. * The generic CPU dependent initialization has been performed * before this routine is invoked. * - * INPUT: NONE - * - * OUTPUT: NONE - * * COPYRIGHT (c) 1989-1998. * On-Line Applications Research Corporation (OAR). * Copyright assigned to U.S. Government, 1994. @@ -17,6 +12,12 @@ * found in the file LICENSE in this distribution or at * http://www.OARcorp.com/rtems/license.html. * + * Ported to the i386ex and submitted by: + * + * Erik Ivanenko + * University of Toronto + * erik.ivanenko@utoronto.ca + * * $Id$ */ @@ -24,12 +25,9 @@ #include #include - -#include -#ifdef PRINTON -extern char inbyte(void); -extern void outbyte(char); +#ifdef STACK_CHECKER_ON +#include #endif /* @@ -42,23 +40,35 @@ rtems_configuration_table BSP_Configuration; rtems_cpu_table Cpu_table; -char *rtems_progname; +/* + * Tells us where to put the workspace in case remote debugger is present. + */ + +extern rtems_unsigned32 rdb_start; -/* Initialize whatever libc we are using - * called from postdriver hook +/* + * bsp_libc_init + * + * Initialize whatever libc we are using called from bsp_postdriver_hook. */ + void bsp_libc_init() { - extern int end; - rtems_unsigned32 heap_start; - - heap_start = (rtems_unsigned32) &end; + extern int heap_bottom; + rtems_unsigned32 heap_start; + rtems_unsigned32 heap_size; + + heap_start = (rtems_unsigned32) &heap_bottom; if (heap_start & (CPU_ALIGNMENT-1)) - heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1); - - RTEMS_Malloc_Initialize((void *) heap_start, 64 * 1024, 0); - + heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1); + + heap_size = BSP_Configuration.work_space_start -(void *) heap_start ; + heap_size &= 0xfffffff0; /* keep it as a multiple of 16 bytes */ + + heap_size &= 0xfffffff0; /* keep it as a multiple of 16 bytes */ + RTEMS_Malloc_Initialize((void *) heap_start, heap_size, 0); + /* * Init the RTEMS libio facility to provide UNIX-like system * calls for use by newlib (ie: provide __rtems_open, __rtems_close, etc) @@ -104,7 +114,7 @@ bsp_pretasking_hook(void) Stack_check_Initialize(); #endif - + #ifdef RTEMS_DEBUG rtems_debug_enable( RTEMS_DEBUG_ALL_MASK ); #endif @@ -112,45 +122,13 @@ bsp_pretasking_hook(void) /* - * After drivers are setup, register some "filenames" - * and open stdin, stdout, stderr files - * - * Newlib will automatically associate the files with these - * (it hardcodes the numbers) + * Use the shared bsp_postdriver_hook() implementation */ -void -bsp_postdriver_hook(void) -{ - int stdin_fd, stdout_fd, stderr_fd; - int error_code; - - error_code = 'S' << 24 | 'T' << 16; - - if ((stdin_fd = __rtems_open("/dev/console", O_RDONLY, 0)) == -1) - rtems_fatal_error_occurred( error_code | 'D' << 8 | '0' ); - - if ((stdout_fd = __rtems_open("/dev/console", O_WRONLY, 0)) == -1) - rtems_fatal_error_occurred( error_code | 'D' << 8 | '1' ); - - if ((stderr_fd = __rtems_open("/dev/console", O_WRONLY, 0)) == -1) - rtems_fatal_error_occurred( error_code | 'D' << 8 | '2' ); - - if ((stdin_fd != 0) || (stdout_fd != 1) || (stderr_fd != 2)) - rtems_fatal_error_occurred( error_code | 'I' << 8 | 'O' ); -} - +void bsp_postdriver_hook(void); void bsp_start( void ) { - -#ifdef PRINTON - outbyte('a'); - outbyte('b'); - outbyte('c'); - outbyte ('S'); -#endif - /* * we do not use the pretasking_hook. */ @@ -169,7 +147,7 @@ void bsp_start( void ) Cpu_table.interrupt_table_offset = (void *)Interrupt_descriptor_table; - Cpu_table.interrupt_stack_size = 4096; + Cpu_table.interrupt_stack_size = 4096; /* STACK_MINIMUM_SIZE */ Cpu_table.extra_mpci_receive_server_stack = 0; @@ -179,24 +157,26 @@ void bsp_start( void ) BSP_Configuration = Configuration; +#if defined(RTEMS_POSIX_API) + BSP_Configuration.work_space_size *= 3; +#endif + BSP_Configuration.work_space_start = (void *) RAM_END - BSP_Configuration.work_space_size; - -#ifdef SPRINTON - sprintf( x_buffer, "ram end : %u, work_space_size: %d\n", - RAM_END , BSP_Configuration.work_space_size ); - do { - outbyte ( x_buffer[i] ); - } while ( x_buffer[i++] != '\n'); -#endif - /* * Add 1 region for Malloc in libc_low */ BSP_Configuration.RTEMS_api_configuration->maximum_regions++; + /* + * Account for the console's resources + */ + + /* console_reserve_resources( &BSP_Configuration ); */ + + /* * Add 1 extension for newlib libc */ diff --git a/c/src/lib/libbsp/i386/i386ex/startup/linkcmds b/c/src/lib/libbsp/i386/i386ex/startup/linkcmds index 2834cbeafb..24202aa59c 100644 --- a/c/src/lib/libbsp/i386/i386ex/startup/linkcmds +++ b/c/src/lib/libbsp/i386/i386ex/startup/linkcmds @@ -17,60 +17,112 @@ ENTRY(reset) ; SECTIONS { - _rom_ints = 0x3fb0000; - .ints 0x0100 : - AT ( _rom_ints ) /* was 0x3fb3300 */ + +/******************************************************************************* + * Interrupts section: + * + * This section defines the layout of the interrupts in ROM ( VMA ) as well as their + * location in RAM (LMA). The _rom_ and _ram_ variables are used in start.s + * in order for the code to move the interrupt vector tables from ROM to RAM + * while still running in real-mode. The tables are moved from ROM, as the IDT + * is initialized with only 16-bit offsets for the interrupt handlers. + * This is purely an implementation issue. If you prefer the interrupt handlers + * to be resident in flash, then you must provide the code to create the interrupt + * gates with full 32bit offsets. The code in the current start.s does NOT support + * interrupts in ROM by merely redefining their location. + ******************************************************************************/ + _rom_ints = 0x3ff0000; /* was 0x3fb0000 */ + _rom_ints_segment = 0xF000 ; + _rom_ints_offset = 0x0000 ; + + _ram_ints_segment = 0x0000 ; + _ram_ints_offset = 0x0100 ; + + + .ints _ram_ints_offset : + AT ( _rom_ints ) { _sints = .; *(.ints); _eints = ALIGN (0x010); } - _cs4_ints_segment = 0x0010 ; - _cs4_ints_offset = 0x0000 ; - _cs6_t_ints_segment = 0xF000 ; /* was 0xF000 */ - _cs6_t_ints_offset = 0x0000 ; /* was 0x3300 */ - _cs6_t_ints_size = _eints - _sints ; - - _rom_gdt = _rom_ints + _cs6_t_ints_size; - .gdt 0x1000 : + + _ints_size = _eints - _sints ; +/************************************************************************************** + * GDT section: + * + * This section defines the locations of the GDT in ROM as well as in RAM. The _rom_ and + * _ram_ variables are used by start.s to copy the GDT from ROM to RAM when still in + * real-mode. The move from ROM to RAM is made as a writeable GDT is required for the + * jump to protected mode to be successful. + **************************************************************************************/ + + _rom_gdt = _rom_ints + _ints_size; + _rom_gdt_segment = 0xF000; + _rom_gdt_offset = _rom_ints_offset + _ints_size; + + _ram_gdt_segment = 0x0000 ; + _ram_gdt_offset = _ram_ints_offset + _ints_size; + + .gdt _ram_gdt_offset : AT ( _rom_gdt ) { _sgdt = .; *(.gdt); _egdt = ALIGN (0x10); } - _cs4_gdt_segment = 0x0100 ; /* evaluates to 0x1000 */ - _cs4_gdt_offset = 0x0000 ; - _cs6_t_gdt_segment = 0xF000; - _cs6_t_gdt_offset = _cs6_t_ints_size; /* was 0x0 */ - _cs6_t_gdt_size = _egdt - _sgdt; - - _rom_idt = _rom_gdt + _cs6_t_gdt_size + _cs6_t_ints_size ; - .idt 0x1200 : + _gdt_size = _egdt - _sgdt; + +/***************************************************************************************** + * IDT section: + * + * This section defines the locations of the IDT in ROM as well as in RAM. The _rom_ and + * _ram_ variables are used by start.s to copy the IDT from ROM to RAM when still in real-mode. + * The move from ROM to RAM is required to enable RTEMS to hook the interrupts, however, + * this move could be made when in protected mode. + ****************************************************************************************/ + + _rom_idt = _rom_gdt + _gdt_size ; + _rom_idt_segment = 0xF000 ; + _rom_idt_offset = _rom_gdt_offset + _gdt_size ; + + _ram_idt_segment = 0x0000 ; + _ram_idt_offset = _ram_gdt_offset + _gdt_size ; + + .idt _ram_idt_offset : AT ( _rom_idt ) { _sidt = .; *(.idt); _eidt = ALIGN (0x10); } - _cs4_idt_segment = 0x0120; - _cs4_idt_offset = 0x0000 ; - _cs6_t_idt_segment = 0xF000 ; - _cs6_t_idt_offset = _cs6_t_ints_size + _cs6_t_gdt_size ; /* was 0x1000 */ - _cs6_t_idt_size = _eidt - _sidt; - - _rom_data_start = _rom_idt + _cs6_t_idt_size ; - .data : - AT ( _rom_data_start ) /* was 0x3fd0000 */ + _idt_size = _eidt - _sidt; + +/**************************************************************************************** + * data section: + * + * This section defines the locations of the data section in ROM as well as in RAM. + * start.s copies the data section to RAM when in protected mode. + ***********************************************************************************/ + + _rom_data_start = _rom_idt + _idt_size ; + + .data : + AT ( _rom_data_start ) { _sdata = .; *(.data); _edata = ALIGN( 0x10 ) ; } _data_start = ADDR(.data) ; + data_start = _data_start ; _data_size = _edata - _sdata ; - _edata = _data_start + _data_size ; +/************************************************************************************** + * bss section: + * + * The bss section is the last section in RAM. + *************************************************************************************/ .bss : { _bss_start = .; @@ -81,11 +133,29 @@ SECTIONS _end = end; __end = end; } - _bss_size = _ebss - _bss_start ; + _bss_size = _ebss - _bss_start ; - +/************************************************************************************** + * General variables: + * + * The stack_size variable is customizable here. The heap is located directly after + * The stack in RAM. A routine within bspstart.c uses these variables to ensure that + * the heap used by RTEMS is as large as the RAM remaining after all workspace configurations + * are complete. + *************************************************************************************/ + stack_size = 0x1000 ; + stack_origin = end + stack_size ; + heap_bottom = stack_origin + 4 ; + +/*************************************************************************************** + * text section: + * + * This section is NOT copied into RAM. It is left in ROM, as the flash ROM is quick enough. + ***************************************************************************************/ .text ( 0x3f80000 ): { + CREATE_OBJECT_SYMBOLS + text_start = . ; _text_start = . ; *(.text ) ; . = ALIGN (16); @@ -101,24 +171,38 @@ SECTIONS *(.ctors) LONG(0) __CTOR_END__ = .; + . = ALIGN (4) ; __DTOR_LIST__ = .; LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2) *(.dtors) LONG(0) __DTOR_END__ = .; - _etext = ALIGN( 0x10 ); + _etext = ALIGN( 0x10 ); + _endtext = . ; } - .initial 0x3ff1000: +/******************************************************************************************* + * initial section: + * + * This section is defined after the data section. It must be in the top 64K of memory + * to enable the initial short jmp from the reset section while still in real-mode. It + * contains ALL initialization and data movement directives. + ******************************************************************************************/ + + .initial _rom_data_start + _data_size : { *(.initial); } - .reset 0x3fffff0: +/******************************************************************************************* + * reset section: + * + * This section contains the short jmp from the reset section to the initial section. It is + * the first code executed on reset/power on. + ******************************************************************************************/ + + .reset 0x3fffff0: { *(.reset); } -} - - - +} \ No newline at end of file -- cgit v1.2.3