From 7cdabc49ca3828c9aeeb6beca4a0beeb71bf23f1 Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Sun, 14 Dec 2014 16:27:06 -0600 Subject: pc386: Add Edison base support The current support for the Edison supports a single polled UART for input and output plus a simulated clock tick. The activities forward for supporting the Edison have been posted on the RTEMS mailing lists and at: http://rtemsramblings.blogspot.com/2014/12/intel-edison-and-rtems-road-forward.html --- c/src/lib/libbsp/i386/pc386/startup/ldsegs.S | 3 +++ 1 file changed, 3 insertions(+) (limited to 'c/src/lib/libbsp/i386/pc386/startup/ldsegs.S') diff --git a/c/src/lib/libbsp/i386/pc386/startup/ldsegs.S b/c/src/lib/libbsp/i386/pc386/startup/ldsegs.S index 14cbb9599b..f527ff9ebd 100644 --- a/c/src/lib/libbsp/i386/pc386/startup/ldsegs.S +++ b/c/src/lib/libbsp/i386/pc386/startup/ldsegs.S @@ -35,6 +35,7 @@ #include #include /* contains sizes of GDT and IDT */ +#include /*----------------------------------------------------------------------------+ | CODE section @@ -109,6 +110,7 @@ next_step: movw ax, fs movw ax, gs +#if (BSP_IS_EDISON == 0) /*---------------------------------------------------------------------+ | Now we have to reprogram the interrupts :-(. We put them right after | the intel-reserved hardware interrupts, at int 0x20-0x2F. There they @@ -154,6 +156,7 @@ next_step: movw $0xFFFB, SYM(i8259s_cache) /* set up same values in cache */ + #endif jmp SYM (_establish_stack) # return to the bsp entry code /*-------------------------------------------------------------------------+ -- cgit v1.2.3