From 64501892a93468ccd04048bb83b35dc8eeb43b95 Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Wed, 27 May 2009 11:58:16 +0000 Subject: 2009-05-25 Allan Hessenflow PR 1415/bsps * startup/bspstart.c, startup/linkcmds: Enable caches and therefore enable the mmu. * start/start.S: Correct call to boot_card to meet bfin abi by clearing l0 - l3 and allocating some stack space. --- c/src/lib/libbsp/bfin/bf537Stamp/ChangeLog | 7 +++ .../lib/libbsp/bfin/bf537Stamp/startup/bspstart.c | 60 ++++++++++++++++++++-- c/src/lib/libbsp/bfin/bf537Stamp/startup/linkcmds | 6 ++- 3 files changed, 68 insertions(+), 5 deletions(-) (limited to 'c/src/lib/libbsp/bfin') diff --git a/c/src/lib/libbsp/bfin/bf537Stamp/ChangeLog b/c/src/lib/libbsp/bfin/bf537Stamp/ChangeLog index 096236cc77..0b2de64dcc 100644 --- a/c/src/lib/libbsp/bfin/bf537Stamp/ChangeLog +++ b/c/src/lib/libbsp/bfin/bf537Stamp/ChangeLog @@ -1,3 +1,10 @@ +2009-05-25 Allan Hessenflow + + * startup/bspstart.c, startup/linkcmds: Enable caches and therefore + enable the mmu. + * start/start.S: Correct call to boot_card to meet bfin abi by + clearing l0 - l3 and allocating some stack space. + 2009-04-28 Chris Johns * start/start.S: Update for boot_card command line change. diff --git a/c/src/lib/libbsp/bfin/bf537Stamp/startup/bspstart.c b/c/src/lib/libbsp/bfin/bf537Stamp/startup/bspstart.c index bc66e37f3a..7a54306d75 100644 --- a/c/src/lib/libbsp/bfin/bf537Stamp/startup/bspstart.c +++ b/c/src/lib/libbsp/bfin/bf537Stamp/startup/bspstart.c @@ -19,15 +19,53 @@ #include #include +#include #include #include +#include #include -#if 0 -static bfin_mmu_region_t mmuRegions[] = { +static bfin_mmu_config_t mmuRegions = { + /* instruction */ + { + {(void *) 0x00000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, + {(void *) 0x00400000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, + {(void *) 0x00800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, + {(void *) 0x00c00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, + {(void *) 0x01000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, + {(void *) 0x01400000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, + {(void *) 0x01800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, + {(void *) 0x01c00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, + {(void *) 0x02000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, + {(void *) 0x02400000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, + {(void *) 0x02800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, + {(void *) 0x02c00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, + {(void *) 0x03000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, + {(void *) 0x20000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, + {(void *) 0xff800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_NOCACHE}, + {(void *) 0xffc00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_NOCACHE} + }, + /* data */ + { + {(void *) 0x00000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, + {(void *) 0x00400000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, + {(void *) 0x00800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, + {(void *) 0x00c00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, + {(void *) 0x01000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, + {(void *) 0x01400000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, + {(void *) 0x01800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, + {(void *) 0x01c00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, + {(void *) 0x02000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, + {(void *) 0x02400000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, + {(void *) 0x02800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, + {(void *) 0x02c00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, + {(void *) 0x03000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, + {(void *) 0x20000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, + {(void *) 0xff800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_NOCACHE}, + {(void *) 0xffc00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_NOCACHE} + } }; -#endif void Init_RTC(void); @@ -52,7 +90,11 @@ void bsp_start(void) { /* BSP Hardware Initialization*/ - /*bfin_mmu_init(sizeof(mmuRegions) / sizeof(mmuRegions[0]), mmuRegions);*/ + *(uint32_t volatile *) DMEM_CONTROL |= DMEM_CONTROL_PORT_PREF0; + *(uint32_t volatile *) DMEM_CONTROL &= ~DMEM_CONTROL_PORT_PREF1; + bfin_mmu_init(&mmuRegions); + rtems_cache_enable_instruction(); + rtems_cache_enable_data(); Init_RTC(); /* Blackfin Real Time Clock initialization */ @@ -96,6 +138,16 @@ static void initPLL(void) { */ static void initEBIU(void) { + + /* by default the processor has priority over dma channels for access to + external memory. this has been seen to result in dma unerruns on + ethernet transmit; it seems likely it could cause dma overruns on + ethernet receive as well. setting the following bit gives the dma + channels priority over the cpu, fixing that problem. unfortunately + we don't have finer grain control than that; all dma channels now + have priority over the cpu. */ + *(uint16_t volatile *) EBIU_AMGCTL |= EBIU_AMGCTL_CDPRIO; + #ifdef BISON /* Configure FLASH */ *((uint32_t*)EBIU_AMBCTL0) = 0x7bb07bb0L; diff --git a/c/src/lib/libbsp/bfin/bf537Stamp/startup/linkcmds b/c/src/lib/libbsp/bfin/bf537Stamp/startup/linkcmds index 90b2ae59b4..b4102ee9f3 100644 --- a/c/src/lib/libbsp/bfin/bf537Stamp/startup/linkcmds +++ b/c/src/lib/libbsp/bfin/bf537Stamp/startup/linkcmds @@ -12,7 +12,11 @@ ENTRY(__start) * Declare some sizes. */ _RamBase = DEFINED(_RamBase) ? _RamBase : 0x0; -_RamSize = DEFINED(_RamSize) ? _RamSize : 0x04000000; +/* bf537stamp has 64MB ram, but dynamic mmu tables have not yet been + implemented. there are not enough static entries to support 64MB + along with banks for io and flash, so waste some RAM at the end + to free up mmu entries. */ +_RamSize = DEFINED(_RamSize) ? _RamSize : 0x03400000; _HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0; _StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000; -- cgit v1.2.3