From 50440c065e247899ee739d56cb1392c259289031 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Wed, 19 Nov 2014 15:30:24 +0100 Subject: bsps/arm: Enable L2C for Cortex-A9 MPCore BSPs --- c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am | 9 ++++---- c/src/lib/libbsp/arm/xilinx-zynq/configure.ac | 8 ++++++++ c/src/lib/libbsp/arm/xilinx-zynq/startup/bspsmp.c | 24 ++++++++++++++++++++++ .../libbsp/arm/xilinx-zynq/startup/bspstarthooks.c | 10 ++++++++- 4 files changed, 46 insertions(+), 5 deletions(-) create mode 100644 c/src/lib/libbsp/arm/xilinx-zynq/startup/bspsmp.c (limited to 'c/src/lib/libbsp/arm/xilinx-zynq') diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am index 15f8af4f90..df4aa15104 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am +++ b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am @@ -94,6 +94,10 @@ libbsp_a_SOURCES += ../shared/arm-cp15-set-ttb-entries.c # Startup libbsp_a_SOURCES += startup/bspreset.c libbsp_a_SOURCES += startup/bspstart.c +if HAS_SMP +libbsp_a_SOURCES += ../shared/arm-a9mpcore-smp.c +libbsp_a_SOURCES += startup/bspsmp.c +endif # IRQ libbsp_a_SOURCES += ../../shared/src/irq-default-handler.c @@ -122,16 +126,13 @@ libbsp_a_SOURCES += i2c/cadence-i2c.c # Cache libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c +libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h libbsp_a_SOURCES += ../shared/arm-l2c-310/cache_.h libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/arm-l2c-310 # Start hooks libbsp_a_SOURCES += startup/bspstarthooks.c startup/bspstartmmu.c -if HAS_SMP -libbsp_a_SOURCES += ../shared/arm-a9mpcore-smp.c -endif - ############################################################################### # Special Rules # ############################################################################### diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/configure.ac b/c/src/lib/libbsp/arm/xilinx-zynq/configure.ac index 580049a621..8f47f2f072 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynq/configure.ac +++ b/c/src/lib/libbsp/arm/xilinx-zynq/configure.ac @@ -24,6 +24,14 @@ AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes") RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[*],[]) RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start]) +RTEMS_BSPOPTS_SET([BSP_DATA_CACHE_ENABLED],[*qemu],[]) +RTEMS_BSPOPTS_SET([BSP_DATA_CACHE_ENABLED],[*],[1]) +RTEMS_BSPOPTS_HELP([BSP_DATA_CACHE_ENABLED],[enable data cache]) + +RTEMS_BSPOPTS_SET([BSP_INSTRUCTION_CACHE_ENABLED],[*qemu],[]) +RTEMS_BSPOPTS_SET([BSP_INSTRUCTION_CACHE_ENABLED],[*],[1]) +RTEMS_BSPOPTS_HELP([BSP_INSTRUCTION_CACHE_ENABLED],[enable instruction cache]) + RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[xilinx_zynq_zc702*],[333333333U]) RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[xilinx_zynq_zedboard*],[666666667U]) RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[*],[100000000U]) diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspsmp.c b/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspsmp.c new file mode 100644 index 0000000000..3940352d9b --- /dev/null +++ b/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspsmp.c @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include + +bool _CPU_SMP_Start_processor(uint32_t cpu_index) +{ + /* + * Wait for secondary processor to complete its basic initialization so that + * we can enable the unified L2 cache. + */ + return _Per_CPU_State_wait_for_non_initial_state(cpu_index, 0); +} diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstarthooks.c b/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstarthooks.c index d8834f017e..58f5ec63ff 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstarthooks.c +++ b/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstarthooks.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. * * embedded brains GmbH * Dornierstr. 4 @@ -29,5 +29,13 @@ BSP_START_TEXT_SECTION void bsp_start_hook_1(void) arm_a9mpcore_start_hook_1(); bsp_start_copy_sections(); zynq_setup_mmu_and_cache(); + +#if !defined(RTEMS_SMP) \ + && (defined(BSP_DATA_CACHE_ENABLED) \ + || defined(BSP_INSTRUCTION_CACHE_ENABLED)) + /* Enable unified L2 cache */ + rtems_cache_enable_data(); +#endif + bsp_start_clear_bss(); } -- cgit v1.2.3