From cbc433c7a25dbe19414f70edc64f9de1f630a117 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Tue, 25 Nov 2014 08:40:20 +0100 Subject: bsps/arm: Add .nocache section This section can be use to provide a cache coherent memory area via rtems_cache_coherent_add_area(). --- c/src/lib/libbsp/arm/xilinx-zynq/startup/linkcmds.in | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'c/src/lib/libbsp/arm/xilinx-zynq/startup/linkcmds.in') diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/startup/linkcmds.in b/c/src/lib/libbsp/arm/xilinx-zynq/startup/linkcmds.in index 7239f0de85..7fd6e2772d 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynq/startup/linkcmds.in +++ b/c/src/lib/libbsp/arm/xilinx-zynq/startup/linkcmds.in @@ -2,7 +2,8 @@ MEMORY { RAM_INT_0 : ORIGIN = @ZYNQ_RAM_INT_0_ORIGIN@, LENGTH = @ZYNQ_RAM_INT_0_LENGTH@ RAM_INT_1 : ORIGIN = @ZYNQ_RAM_INT_1_ORIGIN@, LENGTH = @ZYNQ_RAM_INT_1_LENGTH@ RAM_MMU : ORIGIN = @ZYNQ_RAM_MMU@, LENGTH = @ZYNQ_RAM_MMU_LENGTH@ - RAM : ORIGIN = @ZYNQ_RAM_ORIGIN_AVAILABLE@, LENGTH = @ZYNQ_RAM_LENGTH_AVAILABLE@ + RAM : ORIGIN = @ZYNQ_RAM_ORIGIN_AVAILABLE@, LENGTH = @ZYNQ_RAM_LENGTH_AVAILABLE@ - @ZYNQ_RAM_NOCACHE_LENGTH@ + NOCACHE : ORIGIN = @ZYNQ_RAM_ORIGIN_AVAILABLE@ + @ZYNQ_RAM_LENGTH_AVAILABLE@ - @ZYNQ_RAM_NOCACHE_LENGTH@, LENGTH = @ZYNQ_RAM_NOCACHE_LENGTH@ } bsp_processor_count = DEFINED (bsp_processor_count) ? bsp_processor_count : @ZYNQ_CPUS@; @@ -22,6 +23,8 @@ REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM); REGION_ALIAS ("REGION_BSS", RAM); REGION_ALIAS ("REGION_WORK", RAM); REGION_ALIAS ("REGION_STACK", RAM); +REGION_ALIAS ("REGION_NOCACHE", NOCACHE); +REGION_ALIAS ("REGION_NOCACHE_LOAD", NOCACHE); bsp_stack_irq_size = DEFINED (bsp_stack_irq_size) ? bsp_stack_irq_size : 4096; bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 1024; -- cgit v1.2.3