From 50440c065e247899ee739d56cb1392c259289031 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Wed, 19 Nov 2014 15:30:24 +0100 Subject: bsps/arm: Enable L2C for Cortex-A9 MPCore BSPs --- c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstarthooks.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstarthooks.c') diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstarthooks.c b/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstarthooks.c index d8834f017e..58f5ec63ff 100644 --- a/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstarthooks.c +++ b/c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstarthooks.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. * * embedded brains GmbH * Dornierstr. 4 @@ -29,5 +29,13 @@ BSP_START_TEXT_SECTION void bsp_start_hook_1(void) arm_a9mpcore_start_hook_1(); bsp_start_copy_sections(); zynq_setup_mmu_and_cache(); + +#if !defined(RTEMS_SMP) \ + && (defined(BSP_DATA_CACHE_ENABLED) \ + || defined(BSP_INSTRUCTION_CACHE_ENABLED)) + /* Enable unified L2 cache */ + rtems_cache_enable_data(); +#endif + bsp_start_clear_bss(); } -- cgit v1.2.3