From 040ed0b4cdd1c663408664ba3a8b2e5de0cf54e0 Mon Sep 17 00:00:00 2001 From: Chris Nott Date: Sat, 18 Oct 2014 01:55:37 -0700 Subject: bsp/stm32f4: Add header files Added register definition headers for STM32F4 ADC, EXTI, PWR, SYSCFG, TIM, OTGFS and updated FLASH and RCC. Fixed PLL_Q for USB 48MHz operation. Added flash prefetch enable. --- c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c') diff --git a/c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c b/c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c index 0d08458c2e..8d4bf6b82b 100644 --- a/c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c +++ b/c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c @@ -174,7 +174,7 @@ static rtems_status_code set_system_clk( /* pll_q is a prescaler from VCO for the USB OTG FS, SDIO and RNG, * best if results in the 48MHz for the USB */ - pll_q = ( (long) ( src_clk * pll_n + src_clk * pll_n / 2 ) ) / pll_m / 48; + pll_q = ( (long) ( src_clk * pll_n ) ) / pll_m / 48; if ( pll_q < 2 ) { pll_q = 2; @@ -257,9 +257,10 @@ static rtems_status_code set_system_clk( * Set flash parameters, hard coded for now for fast system clocks. * TODO implement some math to use flash on as low latancy as possible */ - flash->acr = FLASH_ACR_LATENCY( 5 ) | /* latency */ - FLASH_ACR_ICEN | /* instruction cache */ - FLASH_ACR_DCEN; /* data cache */ + flash->acr = STM32F4_FLASH_ACR_LATENCY( 5 ) | /* latency */ + STM32F4_FLASH_ACR_ICEN | /* instruction cache */ + STM32F4_FLASH_ACR_DCEN | /* data cache */ + STM32F4_FLASH_ACR_PRFTEN; /* turn on PLL */ rcc->cr |= RCC_CR_PLLON; -- cgit v1.2.3