From c468f18bb73a570bf2b3eb279a7dea60b91c3319 Mon Sep 17 00:00:00 2001 From: Thomas Doerfler Date: Tue, 15 Dec 2009 15:20:47 +0000 Subject: add support for LPC32xx --- .../libbsp/arm/shared/lpc/clock/lpc-clock-config.c | 121 +++++++++++++++++++++ .../lib/libbsp/arm/shared/lpc/include/lpc-timer.h | 103 ++++++++++++++++++ 2 files changed, 224 insertions(+) create mode 100644 c/src/lib/libbsp/arm/shared/lpc/clock/lpc-clock-config.c create mode 100644 c/src/lib/libbsp/arm/shared/lpc/include/lpc-timer.h (limited to 'c/src/lib/libbsp/arm/shared/lpc') diff --git a/c/src/lib/libbsp/arm/shared/lpc/clock/lpc-clock-config.c b/c/src/lib/libbsp/arm/shared/lpc/clock/lpc-clock-config.c new file mode 100644 index 0000000000..7dbb6c4b32 --- /dev/null +++ b/c/src/lib/libbsp/arm/shared/lpc/clock/lpc-clock-config.c @@ -0,0 +1,121 @@ +/** + * @file + * + * @ingroup lpc + * + * @brief Clock driver configuration. + */ + +/* + * Copyright (c) 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + */ + +#include +#include + +/* This is defined in ../../../shared/clockdrv_shell.h */ +rtems_isr Clock_isr(rtems_vector_number vector); + +static volatile lpc_timer *const lpc_clock = + (volatile lpc_timer *) LPC_CLOCK_TIMER_BASE; + +static void lpc_clock_at_tick(void) +{ + lpc_clock->ir = LPC_TIMER_IR_MR0; +} + +static void lpc_clock_handler_install(void) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + + sc = rtems_interrupt_handler_install( + LPC_CLOCK_INTERRUPT, + "Clock", + RTEMS_INTERRUPT_UNIQUE, + (rtems_interrupt_handler) Clock_isr, + NULL + ); + if (sc != RTEMS_SUCCESSFUL) { + rtems_fatal_error_occurred(0xdeadbeef); + } +} + +static void lpc_clock_initialize(void) +{ + uint64_t interval = ((uint64_t) LPC_CLOCK_REFERENCE + * (uint64_t) rtems_configuration_get_microseconds_per_tick()) / 1000000; + + /* Enable module */ + LPC_CLOCK_MODULE_ENABLE(); + + /* Reset timer */ + lpc_clock->tcr = LPC_TIMER_TCR_RST; + + /* Clear interrupt flags */ + lpc_clock->ir = LPC_TIMER_IR_ALL; + + /* Set timer mode */ + lpc_clock->ccr = 0; + + /* Timer is incremented every PERIPH_CLK tick */ + lpc_clock->pr = 0; + + /* Set match registers */ + lpc_clock->mr0 = (uint32_t) interval; + + /* Generate interrupt and reset counter on match with MR0 */ + lpc_clock->mcr = LPC_TIMER_MCR_MR0_INTR | LPC_TIMER_MCR_MR0_RST; + + /* No external match */ + lpc_clock->emr = 0x0; + + /* Enable timer */ + lpc_clock->tcr = LPC_TIMER_TCR_EN; +} + +static void lpc_clock_cleanup(void) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + + /* Disable timer */ + lpc_clock->tcr = 0x0; + + /* Remove interrupt handler */ + sc = rtems_interrupt_handler_remove( + LPC_CLOCK_INTERRUPT, + (rtems_interrupt_handler) Clock_isr, + NULL + ); + if (sc != RTEMS_SUCCESSFUL) { + rtems_fatal_error_occurred(0xdeadbeef); + } +} + +static uint32_t lpc_clock_nanoseconds_since_last_tick(void) +{ + uint64_t clock = LPC_CLOCK_REFERENCE; + uint64_t clicks = lpc_clock->tc; + uint64_t ns = (clicks * 1000000000) / clock; + + return (uint32_t) ns; +} + +#define Clock_driver_support_at_tick() lpc_clock_at_tick() +#define Clock_driver_support_initialize_hardware() lpc_clock_initialize() +#define Clock_driver_support_install_isr(isr, old_isr) \ + lpc_clock_handler_install() +#define Clock_driver_support_shutdown_hardware() lpc_clock_cleanup() +#define Clock_driver_nanoseconds_since_last_tick \ + lpc_clock_nanoseconds_since_last_tick + +/* Include shared source clock driver code */ +#include "../../../../shared/clockdrv_shell.h" diff --git a/c/src/lib/libbsp/arm/shared/lpc/include/lpc-timer.h b/c/src/lib/libbsp/arm/shared/lpc/include/lpc-timer.h new file mode 100644 index 0000000000..2adf0bec19 --- /dev/null +++ b/c/src/lib/libbsp/arm/shared/lpc/include/lpc-timer.h @@ -0,0 +1,103 @@ +/** + * @file + * + * @ingroup lpc + * + * @brief Timer API. + */ + +/* + * Copyright (c) 2009 + * embedded brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_LPC_TIMER_H +#define LIBBSP_ARM_SHARED_LPC_TIMER_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define LPC_TIMER_IR_MR0 0x1U +#define LPC_TIMER_IR_MR1 0x2U +#define LPC_TIMER_IR_MR2 0x4U +#define LPC_TIMER_IR_MR3 0x8U +#define LPC_TIMER_IR_CR0 0x10U +#define LPC_TIMER_IR_CR1 0x20U +#define LPC_TIMER_IR_CR2 0x40U +#define LPC_TIMER_IR_CR3 0x80U +#define LPC_TIMER_IR_ALL 0xffU + +#define LPC_TIMER_TCR_EN 0x1U +#define LPC_TIMER_TCR_RST 0x2U + +#define LPC_TIMER_MCR_MR0_INTR 0x1U +#define LPC_TIMER_MCR_MR0_RST 0x2U +#define LPC_TIMER_MCR_MR0_STOP 0x4U +#define LPC_TIMER_MCR_MR1_INTR 0x8U +#define LPC_TIMER_MCR_MR1_RST 0x10U +#define LPC_TIMER_MCR_MR1_STOP 0x20U +#define LPC_TIMER_MCR_MR2_INTR 0x40U +#define LPC_TIMER_MCR_MR2_RST 0x80U +#define LPC_TIMER_MCR_MR2_STOP 0x100U +#define LPC_TIMER_MCR_MR3_INTR 0x200U +#define LPC_TIMER_MCR_MR3_RST 0x400U +#define LPC_TIMER_MCR_MR3_STOP 0x800U + +#define LPC_TIMER_CCR_CAP0_RE 0x1U +#define LPC_TIMER_CCR_CAP0_FE 0x2U +#define LPC_TIMER_CCR_CAP0_INTR 0x4U +#define LPC_TIMER_CCR_CAP1_RE 0x8U +#define LPC_TIMER_CCR_CAP1_FE 0x10U +#define LPC_TIMER_CCR_CAP1_INTR 0x20U +#define LPC_TIMER_CCR_CAP2_RE 0x40U +#define LPC_TIMER_CCR_CAP2_FE 0x80U +#define LPC_TIMER_CCR_CAP2_INTR 0x100U +#define LPC_TIMER_CCR_CAP3_RE 0x200U +#define LPC_TIMER_CCR_CAP3_FE 0x400U +#define LPC_TIMER_CCR_CAP3_INTR 0x800U + +#define LPC_TIMER_EMR_EM0_RE 0x1U +#define LPC_TIMER_EMR_EM1_FE 0x2U +#define LPC_TIMER_EMR_EM2_INTR 0x4U +#define LPC_TIMER_EMR_EM3_RE 0x8U +#define LPC_TIMER_EMR_EMC0_FE 0x10U +#define LPC_TIMER_EMR_EMC1_INTR 0x20U +#define LPC_TIMER_EMR_EMC2_RE 0x40U +#define LPC_TIMER_EMR_EMC3_FE 0x80U + +typedef struct { + uint32_t ir; + uint32_t tcr; + uint32_t tc; + uint32_t pr; + uint32_t pc; + uint32_t mcr; + uint32_t mr0; + uint32_t mr1; + uint32_t mr2; + uint32_t mr3; + uint32_t ccr; + uint32_t cr0; + uint32_t cr1; + uint32_t cr2; + uint32_t cr3; + uint32_t emr; + uint32_t ctcr; +} lpc_timer; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_LPC_TIMER_H */ -- cgit v1.2.3