From 8c5c8b27007dcc9ffa6f91e457ee73350f39f3cf Mon Sep 17 00:00:00 2001 From: Pavel Pisa Date: Sun, 17 Jul 2016 19:31:33 +0200 Subject: arm/bsps: CP15 and basic cache support entire cache clean for more architecture variants now. Next cache operations should work on most of cores now rtems_cache_flush_entire_data() rtems_cache_invalidate_entire_data() rtems_cache_invalidate_entire_instruction() Instruction cache invalidate works on the first level for now only. Data cacache operations are extended to ensure flush/invalidate on all cache levels. The CP15 arm_cp15_data_cache_clean_all_levels() function extended to continue through unified levels too (ctype = 4). Updates #2782 Updates #2783 --- c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'c/src/lib/libbsp/arm/shared/include') diff --git a/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h b/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h index 74a65c5ac7..9caa2685bc 100644 --- a/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h +++ b/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h @@ -329,9 +329,13 @@ static inline void arm_cache_l1_invalidate_entire_instruction( void ) arm_cp15_instruction_cache_invalidate(); #endif /* RTEMS_SMP */ - if ( ( ctrl & ARM_CP15_CTRL_Z ) == 0 ) { + if ( ( ctrl & ARM_CP15_CTRL_Z ) != 0 ) { + #if defined(__ARM_ARCH_7A__) arm_cp15_branch_predictor_inner_shareable_invalidate_all(); + #endif + #if defined(__ARM_ARCH_6KZ__) || defined(__ARM_ARCH_7A__) arm_cp15_branch_predictor_invalidate_all(); + #endif } } -- cgit v1.2.3