From 0b74e10fff05de92b15bf29de8608951cb5370fa Mon Sep 17 00:00:00 2001 From: Ralf Kirchner Date: Mon, 17 Feb 2014 11:57:19 +0100 Subject: bsp/arm: Add SCU errata handling for L2C-310 cache --- c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h') diff --git a/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h b/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h index 28640d2a42..861d1aea83 100644 --- a/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h +++ b/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h @@ -58,7 +58,10 @@ typedef struct { #define A9MPCORE_SCU_INVSS_CPU3(ways) BSP_FLD32(val, 12, 15) #define A9MPCORE_SCU_INVSS_CPU3_GET(reg) /* Write only register */ #define A9MPCORE_SCU_INVSS_CPU3_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) - uint32_t reserved_10[12]; + uint32_t reserved_09[8]; + uint32_t diagn_ctrl; +#define A9MPCORE_SCU_DIAGN_CTRL_MIGRATORY_BIT_DISABLE BSP_BIT32(0) + uint32_t reserved_10[3]; uint32_t fltstart; uint32_t fltend; uint32_t reserved_48[2]; -- cgit v1.2.3