From f73cfe99d099e600be3205efae7980e426ad9ea0 Mon Sep 17 00:00:00 2001
From: Ralf Kirchner <ralf.kirchner@embedded-brains.de>
Date: Wed, 31 Jul 2013 09:45:59 +0200
Subject: bsp/altera-cyclone-v: New BSP

Implemented so far:
- nocache heap for uncached RAM
- basic timer
- level 1 cache handling for arm cache controller
  in arm-cache-l1.h
- level 2 L2C-310 cache controller
- MMU
- DWMAC 1000 ethernet controller
- basic errata handling
- smp startup for second core
---
 c/src/lib/libbsp/arm/acinclude.m4 | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'c/src/lib/libbsp/arm/acinclude.m4')

diff --git a/c/src/lib/libbsp/arm/acinclude.m4 b/c/src/lib/libbsp/arm/acinclude.m4
index b800a60833..b4a597d340 100644
--- a/c/src/lib/libbsp/arm/acinclude.m4
+++ b/c/src/lib/libbsp/arm/acinclude.m4
@@ -2,6 +2,8 @@
 AC_DEFUN([RTEMS_CHECK_BSPDIR],
 [
   case "$1" in
+  altera-cyclone-v )
+    AC_CONFIG_SUBDIRS([altera-cyclone-v]);;
   csb336 )
     AC_CONFIG_SUBDIRS([csb336]);;
   csb337 )
-- 
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