From d6b2bbaf1b5f86c29ddc20c5e698fa0f426a8e9a Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Wed, 18 Sep 1996 20:56:35 +0000 Subject: new files submitted by Craig Lebakken (lebakken@minn.net) and Derrick Ostertag (ostertag@transition.com) --- c/src/lib/libbsp/a29k/portsw/start/amd.ah | 517 +++++++++++++++++++++++++ c/src/lib/libbsp/a29k/portsw/start/pswmacro.ah | 442 +++++++++++++++++++++ c/src/lib/libbsp/a29k/portsw/start/register.ah | 214 ++++++++++ 3 files changed, 1173 insertions(+) create mode 100644 c/src/lib/libbsp/a29k/portsw/start/amd.ah create mode 100644 c/src/lib/libbsp/a29k/portsw/start/pswmacro.ah create mode 100644 c/src/lib/libbsp/a29k/portsw/start/register.ah (limited to 'c/src/lib/libbsp/a29k') diff --git a/c/src/lib/libbsp/a29k/portsw/start/amd.ah b/c/src/lib/libbsp/a29k/portsw/start/amd.ah new file mode 100644 index 0000000000..69f34f173e --- /dev/null +++ b/c/src/lib/libbsp/a29k/portsw/start/amd.ah @@ -0,0 +1,517 @@ +; /* @(#)amd.ah 1.1 96/05/23 08:56:58, TEI */ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Initialization values for registers after RESET +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; /* $Id$ */ +; +;* File information and includes. + + .file "amd.ah" + .ident "@(#)amd.ah 1.1 96/05/23 08:56:58, TEI" + + + +; +;* AMD PROCESSOR SPECIFIC VALUES... +; + +; +;* Processor revision levels... +; + +; PRL values: 31-28 27-24 +; Am29000 0 x +; Am29005 1 x +; Am29050 2 x +; Am29035 3 x +; Am29030 4 x +; Am29200 5 x +; Am29205 5 1x +; Am29240 6 0 +; Manx 7 0 +; Cougar 8 0 + + + .equ AM29000_PRL, 0x00 + + .equ AM29005_PRL, 0x10 + + .equ AM29050_PRL, 0x20 + + .equ AM29035_PRL, 0x30 + + .equ AM29030_PRL, 0x40 + + .equ AM29200_PRL, 0x50 + + .equ AM29205_PRL, 0x58 + + .equ AM29240_PRL, 0x60 + + .equ AM29040_PRL, 0x70 + + .equ MANX_PRL, 0x70 + + .equ COUGAR_PRL, 0x80 + +; +;* data structures sizes. +; + .equ CFGINFO_SIZE, 16*4 + + .equ PGMINFO_SIZE, 16*4 + + .equ VARARGS_SPACE, 16*4 + + .equ WINDOWSIZE, 0x80 +; +;* Am29027 Mode registers +; + + .equ Am29027Mode1, 0x0fc00820 + + .equ Am29027Mode2, 0x00001375 + + + +;* Processor Based Equates and Defines + + .equ SIG_SYNC, -1 + + .equ ENABLE, (SM) + + .equ DISABLE, (ENABLE | DI | DA) + + .equ DISABLE_FZ, (FZ | ENABLE | DI | DA) + + .equ CLR_TRAP, (FZ | DA) + + .equ InitOPS, (TD | SM | (3<'rfb + jmpt v0, $3 ; if rfb==rfb' + const tav, (0x80<<2) ; prepare for fill + or tav, tav, v2 ; + + mtsr IPA, tav ; IPA=LA<<2 + sub tav, v3, gr98 ; cache fill LA->rfb + srl tav, tav, 2 ; convert to words + sub tav, tav, 1 ; + + mtsr cr, tav ; + loadm 0, 0, gr0, v2 ; fill from LA->rfb +$3: + add rfb, v3, 0 ; move rfb upto 'rfb + sub rab, v1, 0 ; assign rab to rfb-512 + + add v0, msp, SIGCTX_GR1 ; + load 0, 0, v2, v0 ; v0 = interrupted gr1 + add gr1, v2, 0 ; move gr1 upto 'gr1 + nop ; + .endm + + .macro repair_regs + mtsrim cr, 29 - 1 ; to restore locals + loadm 0, 0, v0, msp ; + add msp, msp, 29*4 ; + popsr Q, tav, msp ; + + popsr IPC, tav, msp ; + popsr IPB, tav, msp ; + popsr IPA, tav, msp ; + pop FPStat3, msp ; floating point regs + + pop FPStat2, msp ; floating point regs + pop FPStat1, msp ; floating point regs + pop FPStat0, msp ; floating point regs + + add msp, msp, 3*4 ; R-stack repaired + .endm + +; +;*HIF related... +; + + + + +; send the message in bufaddr to Montip. + .macro SendMessageToMontip, bufaddr + const lr2, bufaddr +$1: + call lr0, _msg_send + consth lr2, bufaddr + cpeq gr96, gr96, 0 + jmpf gr96, $1 + const lr2, bufaddr + .endm + +; build a HIF_CALL message in bufaddr to send to montip. + .macro BuildHIFCALLMsg, bufaddr, tmp1, tmp2 + const tmp1, bufaddr + consth tmp1, bufaddr + const tmp2, HIF_CALL_MSGCODE + store 0, 0, tmp2, tmp1 ; msg code + add tmp1, tmp1, 4 + const tmp2, HIF_CALL_MSGLEN + store 0, 0, tmp2, tmp1 ; msg len + add tmp1, tmp1, 4 + store 0, 0, gr121, tmp1 ; service number + add tmp1, tmp1, 4 + store 0, 0, lr2, tmp1 ; lr2 + add tmp1, tmp1, 4 + store 0, 0, lr3, tmp1 ; lr3 + add tmp1, tmp1, 4 + store 0, 0, lr4, tmp1 ; lr4 + .endm + +; +;* +;* All the funky AMD style macros go in here...simply for +;* compatility +; +; + .macro IMPORT, symbol + .extern symbol + .endm + + .macro GLOBAL, symbol + .global symbol + .endm + + .macro USESECT, name, type + .sect name, type + .use name + .endm + + .macro SECTION, name, type + .sect name, type + .endm + + .macro FUNC, fname, lineno + .global fname +fname: + .endm + + .macro ENDFUNC, fname, lineno + .endm + +;*************************************LONG + .macro LONG, varname +varname: + .block 4 + .endm + +;*************************************UNSIGNED LONG + .macro ULONG, varname +varname: + .block 4 + .endm + +;*************************************SHORT + .macro SHORT, varname +varname: + .block 2 + .endm + +;*************************************CHAR + .macro CHAR, varname +varname: + .block 1 + .endm + +;*************************************LONGARRAY + .macro LONGARRAY, name, count +name: + .block count*4 + .endm + +;*************************************SHORTARRAY + + .macro SHORTARRAY, name, count +name: + .block count*2 + .endm + +;*************************************CHARARRAY + + .macro CHARARRAY, name, count +name: + .block count + .endm + + +;*************************************VOID_FPTR + + .macro VOID_FPTR, name +name: + .block 4 + .endm diff --git a/c/src/lib/libbsp/a29k/portsw/start/register.ah b/c/src/lib/libbsp/a29k/portsw/start/register.ah new file mode 100644 index 0000000000..1dced5b043 --- /dev/null +++ b/c/src/lib/libbsp/a29k/portsw/start/register.ah @@ -0,0 +1,214 @@ +; /* @(#)register.ah 1.1 96/05/23 08:56:57, TEI */ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; naming of various registers +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; /* $Id$ */ + +;* File information and includes. + + .file "register.ah" + .ident "@(#)register.ah 1.1 96/05/23 08:56:57, TEI\n" + +;* Register Stack pointer and frame pointer registers. + + .extern Rrsp, Rfp + + .reg regsp, %%Rrsp + .reg fp, %%Rfp + + + .extern RTrapReg + .extern Rtrapreg + + .reg TrapReg, %%RTrapReg + .reg trapreg, %%Rtrapreg + + +;* Operating system Interrupt handler registers (gr64-gr67) + + .extern ROSint0, ROSint1, ROSint2, ROSint3 + + .reg OSint0, %%ROSint0 + .reg OSint1, %%ROSint1 + .reg OSint2, %%ROSint2 + .reg OSint3, %%ROSint3 + + .reg it0, %%ROSint0 + .reg it1, %%ROSint1 + .reg it2, %%ROSint2 + .reg it3, %%ROSint3 + + + +;* Operating system temporary (or scratch) registers (gr68-gr79) + + .extern ROStmp0, ROStmp1, ROStmp2, ROStmp3 + .extern ROStmp4, ROStmp5, ROStmp6, ROStmp7 + .extern ROStmp8, ROStmp9, ROStmp10, ROStmp11 + + .reg OStmp0, %%ROStmp0 + .reg OStmp1, %%ROStmp1 + .reg OStmp2, %%ROStmp2 + .reg OStmp3, %%ROStmp3 + + .reg OStmp4, %%ROStmp4 + .reg OStmp5, %%ROStmp5 + .reg OStmp6, %%ROStmp6 + .reg OStmp7, %%ROStmp7 + + .reg OStmp8, %%ROStmp8 + .reg OStmp9, %%ROStmp9 + .reg OStmp10, %%ROStmp10 + .reg OStmp11, %%ROStmp11 + + + .reg kt0, %%ROStmp0 + .reg kt1, %%ROStmp1 + .reg kt2, %%ROStmp2 + .reg kt3, %%ROStmp3 + + .reg kt4, %%ROStmp4 + .reg kt5, %%ROStmp5 + .reg kt6, %%ROStmp6 + .reg kt7, %%ROStmp7 + + .reg kt8, %%ROStmp8 + .reg kt9, %%ROStmp9 + .reg kt10, %%ROStmp10 + .reg kt11, %%ROStmp11 + + + .reg TempReg0, %%ROSint0 + .reg TempReg1, %%ROSint1 + .reg TempReg2, %%ROSint2 + .reg TempReg3, %%ROSint3 + + .reg TempReg4, %%ROStmp0 + .reg TempReg5, %%ROStmp1 + .reg TempReg6, %%ROStmp2 + .reg TempReg7, %%ROStmp3 + + .reg TempReg8, %%ROStmp4 + .reg TempReg9, %%ROStmp5 + .reg TempReg10, %%ROStmp6 + .reg TempReg11, %%ROStmp7 + + .reg TempReg12, %%ROStmp8 + .reg TempReg13, %%ROStmp9 + .reg TempReg14, %%ROStmp10 + .reg TempReg15, %%ROStmp11 + + +;* Assigned static registers + + .extern RSpillAddrReg, RFillAddrReg, RSignalAddrReg + .extern Rpcb, Retc + .extern RTimerExt, RTimerUtil, RLEDReg, RERRReg + .extern Ret0, Ret1, Ret2, Ret3, Ret4, Ret5, Ret6, Ret7, Reta, Retb + .extern Retx, Rety, Retz + + + .reg SpillAddrReg, %%RSpillAddrReg + .reg FillAddrReg, %%RFillAddrReg + .reg SignalAddrReg, %%RSignalAddrReg + .reg pcb, %%Rpcb + + .reg etx, %%Retx + .reg ety, %%Rety + .reg etz, %%Retz + .reg eta, %%Reta + + .reg etb, %%Retb + .reg etc, %%Retc + .reg TimerExt, %%RTimerExt + .reg TimerUtil, %%RTimerUtil + + .reg LEDReg, %%RLEDReg + .reg ERRReg, %%RERRReg + + + .reg et0, %%Ret0 + .reg et1, %%Ret1 + .reg et2, %%Ret2 + .reg et3, %%Ret3 + + .reg et4, %%Ret4 + .reg et5, %%Ret5 + .reg et6, %%Ret6 + .reg et7, %%Ret7 + +; + .equ SCB1REG_NUM, 88 + .reg SCB1REG_PTR, %%Ret0 + +; The floating point trap handlers need a few static registers + + .extern RFPStat0, RFPStat1, RFPStat2, RFPStat3 + .extern Rheapptr, RHeapPtr, RArgvPtr + + .reg FPStat0, %%RFPStat0 + .reg FPStat1, %%RFPStat1 + .reg FPStat2, %%RFPStat2 + .reg FPStat3, %%RFPStat3 + + .reg heapptr, %%Rheapptr + .reg HeapPtr, %%RHeapPtr + .reg ArgvPtr, %%RArgvPtr + + .extern RXLINXReg, RVMBCReg, RUARTReg, RETHERReg + + .reg XLINXReg, %%RXLINXReg + .reg VMBCReg, %%RVMBCReg + .reg UARTReg, %%RUARTReg + .reg ETHERReg, %%RXLINXReg + +;* Compiler and programmer registers. (gr96-gr127) + + .extern Rv0, Rv1, Rv2, Rv3, Rv4, Rv5, Rv6, Rv7, Rv8, Rv9 + .extern Rv10, Rv11, Rv12, Rv13, Rv14, Rv15 + + .reg v0, %%Rv0 + .reg v1, %%Rv1 + .reg v2, %%Rv2 + .reg v3, %%Rv3 + + .reg v4, %%Rv4 + .reg v5, %%Rv5 + .reg v6, %%Rv6 + .reg v7, %%Rv7 + + .reg v8, %%Rv8 + .reg v9, %%Rv9 + .reg v10, %%Rv10 + .reg v11, %%Rv11 + + .reg v12, %%Rv12 + .reg v13, %%Rv13 + .reg v14, %%Rv14 + .reg v15, %%Rv15 + + .extern Rtv0, Rtv1, Rtv2, Rtv3, Rtv4 + + .reg tv0, %%Rtv0 + .reg tv1, %%Rtv1 + .reg tv2, %%Rtv2 + .reg tv3, %%Rtv3 + .reg tv4, %%Rtv4 + +; **************************************************************************** +; For uatrap +; register definitions -- since this trap handler must allow for +; nested traps and interrupts such as TLB miss, protection violation, +; or Data Access Exception, and these trap handlers use the shared +; Temp registers, we must maintain our own that are safe over user- +; mode loads and stores. The following must be assigned global +; registers which are not used in INTR[0-3], TRAP[0-1], TLB miss, +; TLB protection violation, or data exception trap handlers. + +; .reg cha_cpy, OStmp4 ; copy of CHA +; .reg chd_cpy, OStmp5 ; copy of CHD +; .reg chc_cpy, OStmp6 ; copy of CHC +; .reg LTemp0, OStmp7 ; local temp 0 +; .reg LTemp1, OStmp8 ; local temp 1 + +; **************************************************************************** -- cgit v1.2.3