From 50cf94da7e57a9e83d7c0753dd55eae5fd55455a Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Fri, 20 Mar 1998 17:16:31 +0000 Subject: SH port submitted from Ralf Corsepius . --- c/src/exec/score/cpu/sh/Makefile.in | 88 ++++ c/src/exec/score/cpu/sh/asm.h | 137 ++++++ c/src/exec/score/cpu/sh/cpu.c | 232 ++++++++++ c/src/exec/score/cpu/sh/cpu.h | 849 ++++++++++++++++++++++++++++++++++++ c/src/exec/score/cpu/sh/cpu_asm.c | 311 +++++++++++++ c/src/exec/score/cpu/sh/cpu_isps.c | 252 +++++++++++ c/src/exec/score/cpu/sh/cpu_isps.h | 165 +++++++ c/src/exec/score/cpu/sh/iosh7030.h | 223 ++++++++++ c/src/exec/score/cpu/sh/ispsh7032.c | 252 +++++++++++ c/src/exec/score/cpu/sh/rtems.c | 71 +++ c/src/exec/score/cpu/sh/sh.h | 174 ++++++++ c/src/exec/score/cpu/sh/sh_io.h | 48 ++ c/src/exec/score/cpu/sh/shtypes.h | 67 +++ 13 files changed, 2869 insertions(+) create mode 100644 c/src/exec/score/cpu/sh/Makefile.in create mode 100644 c/src/exec/score/cpu/sh/asm.h create mode 100644 c/src/exec/score/cpu/sh/cpu.c create mode 100644 c/src/exec/score/cpu/sh/cpu.h create mode 100644 c/src/exec/score/cpu/sh/cpu_asm.c create mode 100644 c/src/exec/score/cpu/sh/cpu_isps.c create mode 100644 c/src/exec/score/cpu/sh/cpu_isps.h create mode 100644 c/src/exec/score/cpu/sh/iosh7030.h create mode 100644 c/src/exec/score/cpu/sh/ispsh7032.c create mode 100644 c/src/exec/score/cpu/sh/rtems.c create mode 100644 c/src/exec/score/cpu/sh/sh.h create mode 100644 c/src/exec/score/cpu/sh/sh_io.h create mode 100644 c/src/exec/score/cpu/sh/shtypes.h (limited to 'c/src/exec/score') diff --git a/c/src/exec/score/cpu/sh/Makefile.in b/c/src/exec/score/cpu/sh/Makefile.in new file mode 100644 index 0000000000..b99f03b393 --- /dev/null +++ b/c/src/exec/score/cpu/sh/Makefile.in @@ -0,0 +1,88 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH=@srcdir@ +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +RELS=$(ARCH)/rtems-cpu.rel + +# C source names, if any, go here -- minus the .c +C_PIECES=cpu cpu_asm cpu_isps rtems +C_FILES=$(C_PIECES:%=%.c) +C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) + +H_FILES= \ + $(srcdir)/cpu.h \ + $(srcdir)/shtypes.h \ + $(srcdir)/sh.h \ + $(srcdir)/sh_io.h \ + $(srcdir)/cpu_isps.h \ + $(srcdir)/iosh7030.h + +# H_FILES that get installed externally +# sh.h is handled separately +EXTERNAL_H_FILES = \ + $(srcdir)/asm.h + +# Assembly source names, if any, go here -- minus the .s +# Normally cpu_asm and rtems are assembly files +S_PIECES= +S_FILES=$(S_PIECES:%=%.s) +S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) + +SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) $(EXTERNAL_H_FILES) +OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += +CPPFLAGS += +CFLAGS += $(CFLAGS_OS_V) + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +all: ${ARCH} $(SRCS) preinstall $(OBJS) $(RELS) + +$(ARCH)/rtems-cpu.rel: $(OBJS) + $(make-rel) + +# Install the program(s), appending _g or _p as appropriate. +# for include files, just use $(INSTALL) +install: all + +preinstall: $(PROJECT_INCLUDE)/rtems/score/targopts.h \ + ${PROJECT_RELEASE}/lib/bsp_specs + $(INSTALL) -m 444 ${H_FILES} $(PROJECT_INCLUDE)/rtems/score +# we will share the basic cpu file + $(INSTALL) -m 444 ${EXTERNAL_H_FILES} $(PROJECT_INCLUDE) + +$(PROJECT_INCLUDE)/rtems/score/targopts.h: $(ARCH)/targopts.h-tmp + $(INSTALL) -m 444 $(ARCH)/targopts.h-tmp $@ + +# $(ARCH)/targopts.h-tmp rule is in leaf.cfg + +${PROJECT_RELEASE}/lib/bsp_specs: $(ARCH)/bsp_specs.tmp + $(INSTALL) -m 444 $(ARCH)/bsp_specs.tmp $@ + +# $(ARCH)/bsp_specs.tmp rule is in leaf.cfg diff --git a/c/src/exec/score/cpu/sh/asm.h b/c/src/exec/score/cpu/sh/asm.h new file mode 100644 index 0000000000..f6fff9f40e --- /dev/null +++ b/c/src/exec/score/cpu/sh/asm.h @@ -0,0 +1,137 @@ +/* asm.h + * + * This include file attempts to address the problems + * caused by incompatible flavors of assemblers and + * toolsets. It primarily addresses variations in the + * use of leading underscores on symbols and the requirement + * that register names be preceded by a %. + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * NOTE: The spacing in the use of these macros + * is critical to them working as advertised. + * + * COPYRIGHT: + * + * This file is based on similar code found in newlib available + * from ftp.cygnus.com. The file which was used had no copyright + * notice. This file is freely distributable as long as the source + * of the file is noted. This file is: + * + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#ifndef __CPU_SH_ASM_h +#define __CPU_SH_ASM_h + +/* + * Indicate we are in an assembly file and get the basic CPU definitions. + */ + +#ifndef ASM +#define ASM +#endif + +#include +#include + +/* + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + */ + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ _ +#endif + +#ifndef __REGISTER_PREFIX__ +#define __REGISTER_PREFIX__ +#endif + +/* ANSI concatenation macros. */ + +#define CONCAT1(a, b) CONCAT2(a, b) +#define CONCAT2(a, b) a ## b + +/* Use the right prefix for global labels. */ + +#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) + +/* Use the right prefix for registers. */ + +#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) + +/* + * define macros for all of the registers on this CPU + * + * EXAMPLE: #define d0 REG (d0) + */ +#define r0 REG (r0) +#define r1 REG (r1) +#define r2 REG (r2) +#define r3 REG (r3) +#define r4 REG (r4) +#define r5 REG (r5) +#define r6 REG (r6) +#define r7 REG (r7) +#define r8 REG (r8) +#define r9 REG (r9) +#define r10 REG (r10) +#define r11 REG (r11) +#define r12 REG (r12) +#define r13 REG (r13) +#define r14 REG (r14) +#define r15 REG (r15) +#define vbr REG (vbr) +#define gbr REG (gbr) +#define pr REG (pr) +#define mach REG (mach) +#define macl REG (macl) +#define sr REG (sr) +#define pc REG (pc) + +/* + * Define macros to handle section beginning and ends. + */ + + +#define BEGIN_CODE_DCL .text +#define END_CODE_DCL +#define BEGIN_DATA_DCL .data +#define END_DATA_DCL +#define BEGIN_CODE .text +#define END_CODE +#define BEGIN_DATA +#define END_DATA +#define BEGIN_BSS +#define END_BSS +#define END + +/* + * Following must be tailor for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ + +#define PUBLIC(sym) .global SYM (sym) +#define EXTERN(sym) .global SYM (sym) + +#endif diff --git a/c/src/exec/score/cpu/sh/cpu.c b/c/src/exec/score/cpu/sh/cpu.c new file mode 100644 index 0000000000..cc07552cf0 --- /dev/null +++ b/c/src/exec/score/cpu/sh/cpu.c @@ -0,0 +1,232 @@ +/* + * This file contains information pertaining to the Hitachi SH + * processor. + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include +#include +#include +#include +#include + + +/* referenced in start.s */ +extern proc_ptr vectab[] ; + +proc_ptr vectab[256] ; + +extern proc_ptr _Hardware_isr_Table[]; + +/* _CPU_Initialize + * + * This routine performs processor dependent initialization. + * + * INPUT PARAMETERS: + * cpu_table - CPU table to initialize + * thread_dispatch - address of disptaching routine + */ + + +void _CPU_Initialize( + rtems_cpu_table *cpu_table, + void (*thread_dispatch) /* ignored on this CPU */ +) +{ + register unsigned32 level = 0; + + /* + * The thread_dispatch argument is the address of the entry point + * for the routine called at the end of an ISR once it has been + * decided a context switch is necessary. On some compilation + * systems it is difficult to call a high-level language routine + * from assembly. This allows us to trick these systems. + * + * If you encounter this problem save the entry point in a CPU + * dependent variable. + */ + + _CPU_Thread_dispatch_pointer = thread_dispatch; + + /* + * If there is not an easy way to initialize the FP context + * during Context_Initialize, then it is usually easier to + * save an "uninitialized" FP context here and copy it to + * the task's during Context_Initialize. + */ + + /* FP context initialization support goes here */ + + _CPU_Table = *cpu_table; + + /* enable interrupts */ + _CPU_ISR_Set_level( level); +} + +/*PAGE + * + * _CPU_ISR_Get_level + */ + +unsigned32 _CPU_ISR_Get_level( void ) +{ + /* + * This routine returns the current interrupt level. + */ + + register unsigned32 _mask ; + + sh_get_interrupt_level( _mask ); + + return ( _mask); +} + +/*PAGE + * + * _CPU_ISR_install_raw_handler + */ + +void _CPU_ISR_install_raw_handler( + unsigned32 vector, + proc_ptr new_handler, + proc_ptr *old_handler +) +{ + /* + * This is where we install the interrupt handler into the "raw" interrupt + * table used by the CPU to dispatch interrupt handlers. + */ + volatile proc_ptr *vbr ; + +#if SH_PARANOID_ISR + unsigned32 level ; + + sh_disable_interrupts( level ); +#endif + + /* get vbr */ + asm ( "stc vbr,%0" : "=r" (vbr) ); + + *old_handler = vbr[vector] ; + vbr[vector] = new_handler ; + +#if SH_PARANOID_ISR + sh_enable_interrupts( level ); +#endif +} + + +/*PAGE + * + * _CPU_ISR_install_vector + * + * This kernel routine installs the RTEMS handler for the + * specified vector. + * + * Input parameters: + * vector - interrupt vector number + * old_handler - former ISR for this vector number + * new_handler - replacement ISR for this vector number + * + * Output parameters: NONE + * + */ + +void _CPU_ISR_install_vector( + unsigned32 vector, + proc_ptr new_handler, + proc_ptr *old_handler +) +{ + proc_ptr ignored ; + + if(( vector <= 113) && ( vector >= 11)) + { + *old_handler = _ISR_Vector_table[ vector ]; + + /* + * If the interrupt vector table is a table of pointer to isr entry + * points, then we need to install the appropriate RTEMS interrupt + * handler for this vector number. + */ + _CPU_ISR_install_raw_handler(vector, + _Hardware_isr_Table[vector], + &ignored ); + + /* + * We put the actual user ISR address in '_ISR_Vector_table'. + * This will be used by __ISR_Handler so the user gets control. + */ + + _ISR_Vector_table[ vector ] = new_handler; + } +} + +/*PAGE + * + * _CPU_Thread_Idle_body + * + * NOTES: + * + * 1. This is the same as the regular CPU independent algorithm. + * + * 2. If you implement this using a "halt", "idle", or "shutdown" + * instruction, then don't forget to put it in an infinite loop. + * + * 3. Be warned. Some processors with onboard DMA have been known + * to stop the DMA if the CPU were put in IDLE mode. This might + * also be a problem with other on-chip peripherals. So use this + * hook with caution. + */ + +#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE) +void _CPU_Thread_Idle_body( void ) +{ + + for( ; ; ) + { + asm volatile("nop"); + } + /* insert your "halt" instruction here */ ; +} +#endif + +#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) + +unsigned8 _bit_set_table[16] = + { 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 1,0}; + + +#endif + +void _CPU_Context_Initialize( + Context_Control *_the_context, + void *_stack_base, + unsigned32 _size, + unsigned32 _isr, + void (*_entry_point)(void), + int _is_fp ) +{ + _the_context->r15 = (unsigned32*) ((unsigned32) (_stack_base) + (_size) ); + _the_context->sr = (_isr << 4) & 0x00f0 ; + _the_context->pr = (unsigned32*) _entry_point ; +} diff --git a/c/src/exec/score/cpu/sh/cpu.h b/c/src/exec/score/cpu/sh/cpu.h new file mode 100644 index 0000000000..310e3271f6 --- /dev/null +++ b/c/src/exec/score/cpu/sh/cpu.h @@ -0,0 +1,849 @@ +/* + * This include file contains information pertaining to the Hitachi SH + * processor. + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#ifndef _SH_CPU_h +#define _SH_CPU_h + +#ifdef __cplusplus +extern "C" { +#endif + +#include /* pick up machine definitions */ +#ifndef ASM +#include +#endif + +/* conditional compilation parameters */ + +/* + * Should the calls to _Thread_Enable_dispatch be inlined? + * + * If TRUE, then they are inlined. + * If FALSE, then a subroutine call is made. + * + * Basically this is an example of the classic trade-off of size + * versus speed. Inlining the call (TRUE) typically increases the + * size of RTEMS while speeding up the enabling of dispatching. + * [NOTE: In general, the _Thread_Dispatch_disable_level will + * only be 0 or 1 unless you are in an interrupt handler and that + * interrupt handler invokes the executive.] When not inlined + * something calls _Thread_Enable_dispatch which in turns calls + * _Thread_Dispatch. If the enable dispatch is inlined, then + * one subroutine call is avoided entirely.] + */ + +#define CPU_INLINE_ENABLE_DISPATCH FALSE + +/* + * Should the body of the search loops in _Thread_queue_Enqueue_priority + * be unrolled one time? In unrolled each iteration of the loop examines + * two "nodes" on the chain being searched. Otherwise, only one node + * is examined per iteration. + * + * If TRUE, then the loops are unrolled. + * If FALSE, then the loops are not unrolled. + * + * The primary factor in making this decision is the cost of disabling + * and enabling interrupts (_ISR_Flash) versus the cost of rest of the + * body of the loop. On some CPUs, the flash is more expensive than + * one iteration of the loop body. In this case, it might be desirable + * to unroll the loop. It is important to note that on some CPUs, this + * code is the longest interrupt disable period in RTEMS. So it is + * necessary to strike a balance when setting this parameter. + */ + +#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE + +/* + * Does RTEMS manage a dedicated interrupt stack in software? + * + * If TRUE, then a stack is allocated in _Interrupt_Manager_initialization. + * If FALSE, nothing is done. + * + * If the CPU supports a dedicated interrupt stack in hardware, + * then it is generally the responsibility of the BSP to allocate it + * and set it up. + * + * If the CPU does not support a dedicated interrupt stack, then + * the porter has two options: (1) execute interrupts on the + * stack of the interrupted task, and (2) have RTEMS manage a dedicated + * interrupt stack. + * + * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. + * + * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and + * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is + * possible that both are FALSE for a particular CPU. Although it + * is unclear what that would imply about the interrupt processing + * procedure on that CPU. + */ + +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE +#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE + +/* + * We define the interrupt stack in the linker script + */ +#define CPU_ALLOCATE_INTERRUPT_STACK FALSE + + +/* + * Does the CPU have hardware floating point? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. + * + * We currently support sh1 only, which has no FPU, other SHes have an FPU + * + * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. + * It indicates whether or not this CPU model has FP support. For + * example, it would be possible to have an i386_nofp CPU model + * which set this to false to indicate that you have an i386 without + * an i387 and wish to leave floating point support out of RTEMS. + */ + +#define CPU_HARDWARE_FP FALSE + +/* + * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? + * + * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. + * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. + * + * So far, the only CPU in which this option has been used is the + * HP PA-RISC. The HP C compiler and gcc both implicitly use the + * floating point registers to perform integer multiplies. If + * a function which you would not think utilize the FP unit DOES, + * then one can not easily predict which tasks will use the FP hardware. + * In this case, this option should be TRUE. + * + * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. + */ + +#define CPU_ALL_TASKS_ARE_FP FALSE + +/* + * Should the IDLE task have a floating point context? + * + * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task + * and it has a floating point context which is switched in and out. + * If FALSE, then the IDLE task does not have a floating point context. + * + * Setting this to TRUE negatively impacts the time required to preempt + * the IDLE task from an interrupt because the floating point context + * must be saved as part of the preemption. + */ + +#define CPU_IDLE_TASK_IS_FP FALSE + +/* + * Should the saving of the floating point registers be deferred + * until a context switch is made to another different floating point + * task? + * + * If TRUE, then the floating point context will not be stored until + * necessary. It will remain in the floating point registers and not + * disturned until another floating point task is switched to. + * + * If FALSE, then the floating point context is saved when a floating + * point task is switched out and restored when the next floating point + * task is restored. The state of the floating point registers between + * those two operations is not specified. + * + * If the floating point context does NOT have to be saved as part of + * interrupt dispatching, then it should be safe to set this to TRUE. + * + * Setting this flag to TRUE results in using a different algorithm + * for deciding when to save and restore the floating point context. + * The deferred FP switch algorithm minimizes the number of times + * the FP context is saved and restored. The FP context is not saved + * until a context switch is made to another, different FP task. + * Thus in a system with only one FP task, the FP context will never + * be saved or restored. + */ + +#define CPU_USE_DEFERRED_FP_SWITCH TRUE + +/* + * Does this port provide a CPU dependent IDLE task implementation? + * + * If TRUE, then the routine _CPU_Thread_Idle_body + * must be provided and is the default IDLE thread body instead of + * _CPU_Thread_Idle_body. + * + * If FALSE, then use the generic IDLE thread body if the BSP does + * not provide one. + * + * This is intended to allow for supporting processors which have + * a low power or idle mode. When the IDLE thread is executed, then + * the CPU can be powered down. + * + * The order of precedence for selecting the IDLE thread body is: + * + * 1. BSP provided + * 2. CPU dependent (if provided) + * 3. generic (if no BSP and no CPU dependent) + */ + +#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE + +/* + * Does the stack grow up (toward higher addresses) or down + * (toward lower addresses)? + * + * If TRUE, then the grows upward. + * If FALSE, then the grows toward smaller addresses. + */ + +#define CPU_STACK_GROWS_UP FALSE + +/* + * The following is the variable attribute used to force alignment + * of critical RTEMS structures. On some processors it may make + * sense to have these aligned on tighter boundaries than + * the minimum requirements of the compiler in order to have as + * much of the critical data area as possible in a cache line. + * + * The placement of this macro in the declaration of the variables + * is based on the syntactically requirements of the GNU C + * "__attribute__" extension. For example with GNU C, use + * the following to force a structures to a 32 byte boundary. + * + * __attribute__ ((aligned (32))) + * + * NOTE: Currently only the Priority Bit Map table uses this feature. + * To benefit from using this, the data must be heavily + * used so it will stay in the cache and used frequently enough + * in the executive to justify turning this on. + */ + +#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned(16))) + +/* + * The following defines the number of bits actually used in the + * interrupt field of the task mode. How those bits map to the + * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). + */ + +#define CPU_MODES_INTERRUPT_MASK 0x0000000f + +/* + * Processor defined structures + * + * Examples structures include the descriptor tables from the i386 + * and the processor control structure on the i960ca. + */ + +/* may need to put some structures here. */ + +/* + * Contexts + * + * Generally there are 2 types of context to save. + * 1. Interrupt registers to save + * 2. Task level registers to save + * + * This means we have the following 3 context items: + * 1. task level context stuff:: Context_Control + * 2. floating point task stuff:: Context_Control_fp + * 3. special interrupt level context :: Context_Control_interrupt + * + * On some processors, it is cost-effective to save only the callee + * preserved registers during a task context switch. This means + * that the ISR code needs to save those registers which do not + * persist across function calls. It is not mandatory to make this + * distinctions between the caller/callee saves registers for the + * purpose of minimizing context saved during task switch and on interrupts. + * If the cost of saving extra registers is minimal, simplicity is the + * choice. Save the same context on interrupt entry as for tasks in + * this case. + * + * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then + * care should be used in designing the context area. + * + * On some CPUs with hardware floating point support, the Context_Control_fp + * structure will not be used or it simply consist of an array of a + * fixed number of bytes. This is done when the floating point context + * is dumped by a "FP save context" type instruction and the format + * is not really defined by the CPU. In this case, there is no need + * to figure out the exact format -- only the size. Of course, although + * this is enough information for RTEMS, it is probably not enough for + * a debugger such as gdb. But that is another problem. + */ + +typedef struct { + unsigned32 *r15; /* stack pointer */ + + unsigned32 macl; + unsigned32 mach; + unsigned32 *pr; + + unsigned32 *r14; /* frame pointer/call saved */ + + unsigned32 r13; /* call saved */ + unsigned32 r12; /* call saved */ + unsigned32 r11; /* call saved */ + unsigned32 r10; /* call saved */ + unsigned32 r9; /* call saved */ + unsigned32 r8; /* call saved */ + + unsigned32 *r7; /* arg in */ + unsigned32 *r6; /* arg in */ + +#if 0 + unsigned32 *r5; /* arg in */ + unsigned32 *r4; /* arg in */ +#endif + + unsigned32 *r3; /* scratch */ + unsigned32 *r2; /* scratch */ + unsigned32 *r1; /* scratch */ + + unsigned32 *r0; /* arg return */ + + unsigned32 gbr; + unsigned32 sr; + +} Context_Control; + +typedef struct { +} Context_Control_fp; + +typedef struct { +} CPU_Interrupt_frame; + + +/* + * The following table contains the information required to configure + * the SH processor specific parameters. + */ + +typedef struct { + void (*pretasking_hook)( void ); + void (*predriver_hook)( void ); + void (*postdriver_hook)( void ); + void (*idle_task)( void ); + boolean do_zero_of_workspace; + unsigned32 interrupt_stack_size; + unsigned32 extra_mpci_receive_server_stack; + void * (*stack_allocate_hook)( unsigned32 ); + void (*stack_free_hook)( void* ); + /* end of fields required on all CPUs */ +} rtems_cpu_table; + +/* + * This variable is optional. It is used on CPUs on which it is difficult + * to generate an "uninitialized" FP context. It is filled in by + * _CPU_Initialize and copied into the task's FP context area during + * _CPU_Context_Initialize. + */ + +/* +SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; +*/ + +/* + * On some CPUs, RTEMS supports a software managed interrupt stack. + * This stack is allocated by the Interrupt Manager and the switch + * is performed in _ISR_Handler. These variables contain pointers + * to the lowest and highest addresses in the chunk of memory allocated + * for the interrupt stack. Since it is unknown whether the stack + * grows up or down (in general), this give the CPU dependent + * code the option of picking the version it wants to use. + * + * NOTE: These two variables are required if the macro + * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. + */ + +SCORE_EXTERN void *_CPU_Interrupt_stack_low; +SCORE_EXTERN void *_CPU_Interrupt_stack_high; + +/* + * With some compilation systems, it is difficult if not impossible to + * call a high-level language routine from assembly language. This + * is especially true of commercial Ada compilers and name mangling + * C++ ones. This variable can be optionally defined by the CPU porter + * and contains the address of the routine _Thread_Dispatch. This + * can make it easier to invoke that routine at the end of the interrupt + * sequence (if a dispatch is necessary). + */ + +SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); + +/* + * Nothing prevents the porter from declaring more CPU specific variables. + */ + +/* XXX: if needed, put more variables here */ + +/* + * The size of the floating point context area. On some CPUs this + * will not be a "sizeof" because the format of the floating point + * area is not defined -- only the size is. This is usually on + * CPUs with a "floating point save context" instruction. + */ + +#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) + +/* + * Amount of extra stack (above minimum stack size) required by + * MPCI receive server thread. Remember that in a multiprocessor + * system this thread must exist and be able to process all directives. + */ + +#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 + +/* + * This defines the number of entries in the ISR_Vector_table managed + * by RTEMS. + */ + +#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 +#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) + +/* + * Should be large enough to run all RTEMS tests. This insures + * that a "reasonable" small application should not have any problems. + * + * We have been able to run the sptests with this value, but have not + * been able to run the tmtest suite. + */ + +#define CPU_STACK_MINIMUM_SIZE 4096 + +/* + * CPU's worst alignment requirement for data types on a byte boundary. This + * alignment does not take into account the requirements for the stack. + */ + +#define CPU_ALIGNMENT 4 + +/* + * This number corresponds to the byte alignment requirement for the + * heap handler. This alignment requirement may be stricter than that + * for the data types alignment specified by CPU_ALIGNMENT. It is + * common for the heap to follow the same alignment requirement as + * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, + * then this should be set to CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2. It does have to + * be greater or equal to than CPU_ALIGNMENT. + */ + +#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT + +/* + * This number corresponds to the byte alignment requirement for memory + * buffers allocated by the partition manager. This alignment requirement + * may be stricter than that for the data types alignment specified by + * CPU_ALIGNMENT. It is common for the partition to follow the same + * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict + * enough for the partition, then this should be set to CPU_ALIGNMENT. + * + * NOTE: This does not have to be a power of 2. It does have to + * be greater or equal to than CPU_ALIGNMENT. + */ + +#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT + +/* + * This number corresponds to the byte alignment requirement for the + * stack. This alignment requirement may be stricter than that for the + * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT + * is strict enough for the stack, then this should be set to 0. + * + * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. + */ + +#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT + +/* ISR handler macros */ + +/* + * Disable all interrupts for an RTEMS critical section. The previous + * level is returned in _level. + */ + +#define _CPU_ISR_Disable( _level) \ + sh_disable_interrupts( _level ) + +/* + * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). + * This indicates the end of an RTEMS critical section. The parameter + * _level is not modified. + */ + +#define _CPU_ISR_Enable( _level) \ + sh_enable_interrupts( _level) + +/* + * This temporarily restores the interrupt to _level before immediately + * disabling them again. This is used to divide long RTEMS critical + * sections into two or more parts. The parameter _level is not + * modified. + */ + +#define _CPU_ISR_Flash( _level) \ + sh_flash_interrupts( _level) + +/* + * Map interrupt level in task mode onto the hardware that the CPU + * actually provides. Currently, interrupt levels which do not + * map onto the CPU in a generic fashion are undefined. Someday, + * it would be nice if these were "mapped" by the application + * via a callout. For example, m68k has 8 levels 0 - 7, levels + * 8 - 255 would be available for bsp/application specific meaning. + * This could be used to manage a programmable interrupt controller + * via the rtems_task_mode directive. + */ + +#define _CPU_ISR_Set_level( _newlevel) \ + sh_set_interrupt_level(_newlevel) + +unsigned32 _CPU_ISR_Get_level( void ); + +/* end of ISR handler macros */ + +/* Context handler macros */ + +/* + * Initialize the context to a state suitable for starting a + * task after a context restore operation. Generally, this + * involves: + * + * - setting a starting address + * - preparing the stack + * - preparing the stack and frame pointers + * - setting the proper interrupt level in the context + * - initializing the floating point context + * + * This routine generally does not set any unnecessary register + * in the context. The state of the "general data" registers is + * undefined at task start time. + * + * NOTE: This is_fp parameter is TRUE if the thread is to be a floating + * point thread. This is typically only used on CPUs where the + * FPU may be easily disabled by software such as on the SPARC + * where the PSR contains an enable FPU bit. + */ + +/* + * FIXME: defined as a function for debugging - should be a macro + */ +SCORE_EXTERN void _CPU_Context_Initialize( + Context_Control *_the_context, + void *_stack_base, + unsigned32 _size, + unsigned32 _isr, + void (*_entry_point)(void), + int _is_fp ); + +/* + * This routine is responsible for somehow restarting the currently + * executing task. If you are lucky, then all that is necessary + * is restoring the context. Otherwise, there will need to be + * a special assembly routine which does something special in this + * case. Context_Restore should work most of the time. It will + * not work if restarting self conflicts with the stack frame + * assumptions of restoring a context. + */ + +#define _CPU_Context_Restart_self( _the_context ) \ + _CPU_Context_restore( (_the_context) ); + +/* + * The purpose of this macro is to allow the initial pointer into + * a floating point context area (used to save the floating point + * context) to be at an arbitrary place in the floating point + * context area. + * + * This is necessary because some FP units are designed to have + * their context saved as a stack which grows into lower addresses. + * Other FP units can be saved by simply moving registers into offsets + * from the base of the context area. Finally some FP units provide + * a "dump context" instruction which could fill in from high to low + * or low to high based on the whim of the CPU designers. + */ + +#define _CPU_Context_Fp_start( _base, _offset ) \ + ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) + +/* + * This routine initializes the FP context area passed to it to. + * There are a few standard ways in which to initialize the + * floating point context. The code included for this macro assumes + * that this is a CPU in which a "initial" FP context was saved into + * _CPU_Null_fp_context and it simply copies it to the destination + * context passed to it. + * + * Other models include (1) not doing anything, and (2) putting + * a "null FP status word" in the correct place in the FP context. + * SH has no FPU !!!!!!!!!!!! + */ + +#define _CPU_Context_Initialize_fp( _destination ) \ + { } + +/* end of Context handler macros */ + +/* Fatal Error manager macros */ + +/* + * FIXME: Trap32 ??? + * + * This routine copies _error into a known place -- typically a stack + * location or a register, optionally disables interrupts, and + * invokes a Trap32 Instruction which returns to the breakpoint + * routine of cmon. + */ + +#ifdef BSP_FATAL_HALT + /* we manage the fatal error in the board support package */ + void bsp_fatal_halt( unsigned32 _error); +#define _CPU_Fatal_halt( _error ) bsp_fatal_halt( _error) +#else +#define _CPU_Fatal_halt( _error)\ +{ \ + asm volatile("mov.l %0,r0"::"m" (_error)); \ + asm volatile("trapa #34"); \ +} +#endif + +/* end of Fatal Error manager macros */ + +/* Bitfield handler macros */ + +/* + * This routine sets _output to the bit number of the first bit + * set in _value. _value is of CPU dependent type Priority_Bit_map_control. + * This type may be either 16 or 32 bits wide although only the 16 + * least significant bits will be used. + * + * There are a number of variables in using a "find first bit" type + * instruction. + * + * (1) What happens when run on a value of zero? + * (2) Bits may be numbered from MSB to LSB or vice-versa. + * (3) The numbering may be zero or one based. + * (4) The "find first bit" instruction may search from MSB or LSB. + * + * RTEMS guarantees that (1) will never happen so it is not a concern. + * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and + * _CPU_Priority_bits_index(). These three form a set of routines + * which must logically operate together. Bits in the _value are + * set and cleared based on masks built by _CPU_Priority_mask(). + * The basic major and minor values calculated by _Priority_Major() + * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() + * to properly range between the values returned by the "find first bit" + * instruction. This makes it possible for _Priority_Get_highest() to + * calculate the major and directly index into the minor table. + * This mapping is necessary to ensure that 0 (a high priority major/minor) + * is the first bit found. + * + * This entire "find first bit" and mapping process depends heavily + * on the manner in which a priority is broken into a major and minor + * components with the major being the 4 MSB of a priority and minor + * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest + * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next + * to the lowest priority. + * + * If your CPU does not have a "find first bit" instruction, then + * there are ways to make do without it. Here are a handful of ways + * to implement this in software: + * + * - a series of 16 bit test instructions + * - a "binary search using if's" + * - _number = 0 + * if _value > 0x00ff + * _value >>=8 + * _number = 8; + * + * if _value > 0x0000f + * _value >=8 + * _number += 4 + * + * _number += bit_set_table[ _value ] + * + * where bit_set_table[ 16 ] has values which indicate the first + * bit set + */ + +#define CPU_USE_GENERIC_BITFIELD_CODE TRUE +#define CPU_USE_GENERIC_BITFIELD_DATA TRUE + +#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) + +extern unsigned8 _bit_set_table[]; + +#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ + { \ + _output = 0;\ + if(_value > 0x00ff) \ + { _value >>= 8; _output = 8; } \ + if(_value > 0x000f) \ + { _output += 4; _value >>= 4; } \ + _output += _bit_set_table[ _value]; } + +#endif + +/* end of Bitfield handler macros */ + +/* + * This routine builds the mask which corresponds to the bit fields + * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion + * for that routine. + */ + +#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) + +#define _CPU_Priority_Mask( _bit_number ) \ + ( 1 << (_bit_number) ) + +#endif + +/* + * This routine translates the bit numbers returned by + * _CPU_Bitfield_Find_first_bit() into something suitable for use as + * a major or minor component of a priority. See the discussion + * for that routine. + */ + +#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) + +#define _CPU_Priority_bits_index( _priority ) \ + (_priority) + +#endif + +/* end of Priority handler macros */ + +/* functions */ + +/* + * _CPU_Initialize + * + * This routine performs CPU dependent initialization. + */ + +void _CPU_Initialize( + rtems_cpu_table *cpu_table, + void (*thread_dispatch) +); + +/* + * _CPU_ISR_install_raw_handler + * + * This routine installs a "raw" interrupt handler directly into the + * processor's vector table. + */ + +void _CPU_ISR_install_raw_handler( + unsigned32 vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/* + * _CPU_ISR_install_vector + * + * This routine installs an interrupt vector. + */ + +void _CPU_ISR_install_vector( + unsigned32 vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +/* + * _CPU_Install_interrupt_stack + * + * This routine installs the hardware interrupt stack pointer. + * + * NOTE: It needs only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK + * is TRUE. + */ + +void _CPU_Install_interrupt_stack( void ); + +/* + * _CPU_Thread_Idle_body + * + * This routine is the CPU dependent IDLE thread body. + * + * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY + * is TRUE. + */ + +void _CPU_Thread_Idle_body( void ); + +/* + * _CPU_Context_switch + * + * This routine switches from the run context to the heir context. + */ + +void _CPU_Context_switch( + Context_Control *run, + Context_Control *heir +); + +/* + * _CPU_Context_restore + * + * This routine is generally used only to restart self in an + * efficient manner. It may simply be a label in _CPU_Context_switch. + */ + +void _CPU_Context_restore( + Context_Control *new_context +); + +/* + * _CPU_Context_save_fp + * + * This routine saves the floating point context passed to it. + */ + +void _CPU_Context_save_fp( + void **fp_context_ptr +); + +/* + * _CPU_Context_restore_fp + * + * This routine restores the floating point context passed to it. + */ + +void _CPU_Context_restore_fp( + void **fp_context_ptr +); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/c/src/exec/score/cpu/sh/cpu_asm.c b/c/src/exec/score/cpu/sh/cpu_asm.c new file mode 100644 index 0000000000..42764f6eb1 --- /dev/null +++ b/c/src/exec/score/cpu/sh/cpu_asm.c @@ -0,0 +1,311 @@ +/* + * This file contains the basic algorithms for all assembly code used + * in an specific CPU port of RTEMS. These algorithms must be implemented + * in assembly language + * + * NOTE: This port uses a C file with inline assembler instructions + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + */ + +/* + * This is supposed to be an assembly file. This means that system.h + * and cpu.h should not be included in a "real" cpu_asm file. An + * implementation in assembly should include "cpu_asm.h" + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* from cpu_isps.c */ +extern proc_ptr _Hardware_isr_Table[]; + +#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) + unsigned long *_old_stack_ptr; +#endif + +register unsigned long *stack_ptr asm("r15"); + +/* + * sh_set_irq_priority + * + * this function sets the interrupt level of the specified interrupt + * + * parameters: + * - irq : interrupt number + * - prio: priority to set for this interrupt number + * + * returns: 0 if ok + * -1 on error + */ + +unsigned int sh_set_irq_priority( + unsigned int irq, + unsigned int prio ) +{ + unsigned32 shiftcount; + unsigned32 prioreg; + unsigned16 temp16; + unsigned32 level; + + /* + * first check for valid interrupt + */ + if(( irq > 113) || (_Hardware_isr_Table[irq] == _dummy_isp)) + return -1; + /* + * check for valid irq priority + */ + if( prio > 15 ) + return -1; + + /* + * look up appropriate interrupt priority register + */ + if( irq > 71) + { + irq = irq - 72; + shiftcount = 12 - ((irq & ~0x03) % 16); + + switch( irq / 16) + { + case 0: { prioreg = INTC_IPRC; break;} + case 1: { prioreg = INTC_IPRD; break;} + case 2: { prioreg = INTC_IPRE; break;} + default: return -1; + } + } + else + { + shiftcount = 12 - 4 * ( irq % 4); + if( irq > 67) + prioreg = INTC_IPRB; + else + prioreg = INTC_IPRA; + } + + /* + * Set the interrupt priority register + */ + _CPU_ISR_Disable( level ); + + temp16 = read16( prioreg); + temp16 &= ~( 15 << shiftcount); + temp16 |= prio << shiftcount; + write16( temp16, prioreg); + + _CPU_ISR_Enable( level ); + + return 0; +} + +/* + * _CPU_Context_save_fp_context + * + * This routine is responsible for saving the FP context + * at *fp_context_ptr. If the point to load the FP context + * from is changed then the pointer is modified by this routine. + * + * Sometimes a macro implementation of this is in cpu.h which dereferences + * the ** and a similarly named routine in this file is passed something + * like a (Context_Control_fp *). The general rule on making this decision + * is to avoid writing assembly language. + */ + +void _CPU_Context_save_fp( + void **fp_context_ptr +) +{ +} + +/* + * _CPU_Context_restore_fp_context + * + * This routine is responsible for restoring the FP context + * at *fp_context_ptr. If the point to load the FP context + * from is changed then the pointer is modified by this routine. + * + * Sometimes a macro implementation of this is in cpu.h which dereferences + * the ** and a similarly named routine in this file is passed something + * like a (Context_Control_fp *). The general rule on making this decision + * is to avoid writing assembly language. + */ + +void _CPU_Context_restore_fp( + void **fp_context_ptr +) +{ +} + +/* _CPU_Context_switch + * + * This routine performs a normal non-FP context switch. + */ + +/* within __CPU_Context_switch: + * _CPU_Context_switch + * _CPU_Context_restore + * + * This routine is generally used only to restart self in an + * efficient manner. It may simply be a label in _CPU_Context_switch. + * + * NOTE: It should be safe not to store r4, r5 + * + * NOTE: It is doubtful if r0 is really needed to be stored + * + * NOTE: gbr is added, but should not be necessary, as it is + * only used globally in this port. + */ + +/* + * FIXME: This is an ugly hack, but we wanted to avoid recalculating + * the offset each time Context_Control is changed + */ +void __CPU_Context_switch( + Context_Control *run, /* r4 */ + Context_Control *heir /* r5 */ +) +{ + +asm volatile(" + .global __CPU_Context_switch +__CPU_Context_switch: + + add %0,r4 + + stc.l sr,@-r4 + stc.l gbr,@-r4 + mov.l r0,@-r4 + mov.l r1,@-r4 + mov.l r2,@-r4 + mov.l r3,@-r4 + + mov.l r6,@-r4 + mov.l r7,@-r4 + mov.l r8,@-r4 + mov.l r9,@-r4 + mov.l r10,@-r4 + mov.l r11,@-r4 + mov.l r12,@-r4 + mov.l r13,@-r4 + mov.l r14,@-r4 + sts.l pr,@-r4 + sts.l mach,@-r4 + sts.l macl,@-r4 + mov.l r15,@-r4 + + mov r5, r4" + :: "I" (sizeof(Context_Control)) + ); + + asm volatile(" + .global __CPU_Context_restore +__CPU_Context_restore: + mov.l @r4+,r15 + lds.l @r4+,macl + lds.l @r4+,mach + lds.l @r4+,pr + mov.l @r4+,r14 + mov.l @r4+,r13 + mov.l @r4+,r12 + mov.l @r4+,r11 + mov.l @r4+,r10 + mov.l @r4+,r9 + mov.l @r4+,r8 + mov.l @r4+,r7 + mov.l @r4+,r6 + + mov.l @r4+,r3 + mov.l @r4+,r2 + mov.l @r4+,r1 + mov.l @r4+,r0 + ldc.l @r4+,gbr + ldc.l @r4+,sr + + rts + nop" ); +} + +/* + * This routine provides the RTEMS interrupt management. + */ + +void __ISR_Handler( unsigned32 vector) +{ + register unsigned32 level; + + _CPU_ISR_Disable( level ); + + _Thread_Dispatch_disable_level++; + +#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) + if( _ISR_Nest_level == 0 ) + { + /* Install irq stack */ + _old_stack_ptr = stack_ptr; + stack_ptr = _CPU_Interrupt_stack_high; + } + +#endif + + _ISR_Nest_level++; + + _CPU_ISR_Enable( level ); + + /* call isp */ + if( _ISR_Vector_table[ vector]) + (*_ISR_Vector_table[ vector ])( vector ); + + _CPU_ISR_Disable( level ); + + _ISR_Nest_level--; + +#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) + + if( _ISR_Nest_level == 0 ) + /* restore old stack pointer */ + stack_ptr = _old_stack_ptr; +#endif + + _Thread_Dispatch_disable_level--; + + _CPU_ISR_Enable( level ); + + if ( _Thread_Dispatch_disable_level == 0 ) + { + if(( _Context_Switch_necessary) || (! _ISR_Signals_to_thread_executing)) + { + _ISR_Signals_to_thread_executing = FALSE; + _Thread_Dispatch(); + } + } +} diff --git a/c/src/exec/score/cpu/sh/cpu_isps.c b/c/src/exec/score/cpu/sh/cpu_isps.c new file mode 100644 index 0000000000..1643785810 --- /dev/null +++ b/c/src/exec/score/cpu/sh/cpu_isps.c @@ -0,0 +1,252 @@ +/* + * This file contains the isp frames for the user interrupts. + * From these procedures __ISR_Handler is called with the vector number + * as argument. + * + * __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in + * some releases of gcc doesn't properly handle #pragma interrupt, if a + * file contains both isrs and normal functions. + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include +#include +#include + +/* + * This is a exception vector table + * + * It has the same structure like the actual vector table (vectab) + */ +proc_ptr _Hardware_isr_Table[256]={ +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, +_nmi_isp, _usb_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, +/* trapa 0 -31 */ +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +/* irq 64 ... */ +_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp, +_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp, +_dma0_isp, _dummy_isp, _dma1_isp, _dummy_isp, +_dma2_isp, _dummy_isp, _dma3_isp, _dummy_isp, +_imia0_isp, _imib0_isp, _ovi0_isp, _dummy_isp, +_imia1_isp, _imib1_isp, _ovi1_isp, _dummy_isp, +_imia2_isp, _imib2_isp, _ovi2_isp, _dummy_isp, +_imia3_isp, _imib3_isp, _ovi3_isp, _dummy_isp, +_imia4_isp, _imib4_isp, _ovi4_isp, _dummy_isp, +_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp, +_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp, +_prt_isp, _adu_isp, _dummy_isp, _dummy_isp, +_wdt_isp, +/* 113 */ _dref_isp +}; + +#define Str(a)#a + +/* + * Some versions of gcc and all version of egcs at least until egcs-1.0.2 + * are not able to handle #praga interrupt correctly if more than 1 isr is + * contained in a file and when optimizing. + * We try to work around this problem by using the macro below. + */ +#define isp( name, number, func)\ +asm (".global _"Str(name)"\n\t" \ + "_"Str(name)": \n\t" \ + " mov.l r0,@-r15 \n\t" \ + " mov.l r1,@-r15 \n\t" \ + " mov.l r2,@-r15 \n\t" \ + " mov.l r3,@-r15 \n\t" \ + " mov.l r4,@-r15 \n\t" \ + " mov.l r5,@-r15 \n\t" \ + " mov.l r6,@-r15 \n\t" \ + " mov.l r7,@-r15 \n\t" \ + " mov.l r14,@-r15 \n\t" \ + " sts.l pr,@-r15 \n\t" \ + " sts.l mach,@-r15 \n\t" \ + " sts.l macl,@-r15 \n\t" \ + " mov r15,r14 \n\t" \ + " mov.l "Str(name)"_k, r1\n\t" \ + " jsr @r1 \n\t" \ + " mov #"Str(number)", r4\n\t" \ + " mov r14,r15 \n\t" \ + " lds.l @r15+,macl \n\t" \ + " lds.l @r15+,mach \n\t" \ + " lds.l @r15+,pr \n\t" \ + " mov.l @r15+,r14 \n\t" \ + " mov.l @r15+,r7 \n\t" \ + " mov.l @r15+,r6 \n\t" \ + " mov.l @r15+,r5 \n\t" \ + " mov.l @r15+,r4 \n\t" \ + " mov.l @r15+,r3 \n\t" \ + " mov.l @r15+,r2 \n\t" \ + " mov.l @r15+,r1 \n\t" \ + " mov.l @r15+,r0 \n\t" \ + " rte \n\t" \ + " nop \n\t" \ + " .align 2 \n\t" \ + #name"_k: \n\t" \ + ".long "Str(func)); + +/************************************************ + * Dummy interrupt service procedure for + * interrupts being not allowed --> Trap 34 + ************************************************/ +asm(" .section .text +.global __dummy_isp +__dummy_isp: + mov.l r14,@-r15 + mov r15, r14 + trapa #34 + mov.l @r15+,r14 + rte + nop"); + +/***************************** + * Non maskable interrupt + *****************************/ +isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler); + +/***************************** + * User break controller + *****************************/ +isp( _usb_isp, USB_ISP_V, ___ISR_Handler); + +/***************************** + * External interrupts 0-7 + *****************************/ +isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler); +isp( _irq1_isp, IRQ1_ISP_V, ___ISR_Handler); +isp( _irq2_isp, IRQ2_ISP_V, ___ISR_Handler); +isp( _irq3_isp, IRQ3_ISP_V, ___ISR_Handler); +isp( _irq4_isp, IRQ4_ISP_V, ___ISR_Handler); +isp( _irq5_isp, IRQ5_ISP_V, ___ISR_Handler); +isp( _irq6_isp, IRQ6_ISP_V, ___ISR_Handler); +isp( _irq7_isp, IRQ7_ISP_V, ___ISR_Handler); + +/***************************** + * DMA - controller + *****************************/ +isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler); +isp( _dma1_isp, DMA1_ISP_V, ___ISR_Handler); +isp( _dma2_isp, DMA2_ISP_V, ___ISR_Handler); +isp( _dma3_isp, DMA3_ISP_V, ___ISR_Handler); + + +/***************************** + * Interrupt timer unit + *****************************/ + +/***************************** + * Timer 0 + *****************************/ +isp( _imia0_isp, IMIA0_ISP_V, ___ISR_Handler); +isp( _imib0_isp, IMIB0_ISP_V, ___ISR_Handler); +isp( _ovi0_isp, OVI0_ISP_V, ___ISR_Handler); + +/***************************** + * Timer 1 + *****************************/ +isp( _imia1_isp, IMIA1_ISP_V, ___ISR_Handler); +isp( _imib1_isp, IMIB1_ISP_V, ___ISR_Handler); +isp( _ovi1_isp, OVI1_ISP_V, ___ISR_Handler); + +/***************************** + * Timer 2 + *****************************/ +isp( _imia2_isp, IMIA2_ISP_V, ___ISR_Handler); +isp( _imib2_isp, IMIB2_ISP_V, ___ISR_Handler); +isp( _ovi2_isp, OVI2_ISP_V, ___ISR_Handler); + +/***************************** + * Timer 3 + *****************************/ +isp( _imia3_isp, IMIA3_ISP_V, ___ISR_Handler); +isp( _imib3_isp, IMIB3_ISP_V, ___ISR_Handler); +isp( _ovi3_isp, OVI3_ISP_V, ___ISR_Handler); + +/***************************** + * Timer 4 + *****************************/ +isp( _imia4_isp, IMIA4_ISP_V, ___ISR_Handler); +isp( _imib4_isp, IMIB4_ISP_V, ___ISR_Handler); +isp( _ovi4_isp, OVI4_ISP_V, ___ISR_Handler); + + +/***************************** + * Serial interfaces + *****************************/ + +/***************************** + * Serial interface 0 + *****************************/ +isp( _eri0_isp, ERI0_ISP_V, ___ISR_Handler); +isp( _rxi0_isp, RXI0_ISP_V, ___ISR_Handler); +isp( _txi0_isp, TXI0_ISP_V, ___ISR_Handler); +isp( _tei0_isp, TEI0_ISP_V, ___ISR_Handler); + +/***************************** + * Serial interface 1 + *****************************/ +isp( _eri1_isp, ERI1_ISP_V, ___ISR_Handler); +isp( _rxi1_isp, RXI1_ISP_V, ___ISR_Handler); +isp( _txi1_isp, TXI1_ISP_V, ___ISR_Handler); +isp( _tei1_isp, TEI1_ISP_V, ___ISR_Handler); + + +/***************************** + * Parity control unit of + * the bus state controller + *****************************/ +isp( _prt_isp, PRT_ISP_V, ___ISR_Handler); + + +/****************************** + * Analog digital converter + * ADC + ******************************/ +isp( _adu_isp, ADU_ISP_V, ___ISR_Handler); + + +/****************************** + * Watchdog timer + ******************************/ +isp( _wdt_isp, WDT_ISP_V, ___ISR_Handler); + + +/****************************** + * DRAM refresh control unit + * of bus state controller + ******************************/ +isp( _dref_isp, DREF_ISP_V, ___ISR_Handler); diff --git a/c/src/exec/score/cpu/sh/cpu_isps.h b/c/src/exec/score/cpu/sh/cpu_isps.h new file mode 100644 index 0000000000..3f9baf1ad2 --- /dev/null +++ b/c/src/exec/score/cpu/sh/cpu_isps.h @@ -0,0 +1,165 @@ +/* + * This include file contains information pertaining to the Hitachi SH + * processor. + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#ifndef __CPU_ISPS_H +#define __CPU_ISPS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern void __ISR_Handler( unsigned32 vector ); + + +/* + * interrupt vector table offsets + */ +#define NMI_ISP_V 11 +#define USB_ISP_V 12 +#define IRQ0_ISP_V 64 +#define IRQ1_ISP_V 65 +#define IRQ2_ISP_V 66 +#define IRQ3_ISP_V 67 +#define IRQ4_ISP_V 68 +#define IRQ5_ISP_V 69 +#define IRQ6_ISP_V 70 +#define IRQ7_ISP_V 71 +#define DMA0_ISP_V 72 +#define DMA1_ISP_V 74 +#define DMA2_ISP_V 76 +#define DMA3_ISP_V 78 + +#define IMIA0_ISP_V 80 +#define IMIB0_ISP_V 81 +#define OVI0_ISP_V 82 + +#define IMIA1_ISP_V 84 +#define IMIB1_ISP_V 85 +#define OVI1_ISP_V 86 + +#define IMIA2_ISP_V 88 +#define IMIB2_ISP_V 89 +#define OVI2_ISP_V 90 + +#define IMIA3_ISP_V 92 +#define IMIB3_ISP_V 93 +#define OVI3_ISP_V 94 + +#define IMIA4_ISP_V 96 +#define IMIB4_ISP_V 97 +#define OVI4_ISP_V 98 + +#define ERI0_ISP_V 100 +#define RXI0_ISP_V 101 +#define TXI0_ISP_V 102 +#define TEI0_ISP_V 103 + +#define ERI1_ISP_V 104 +#define RXI1_ISP_V 105 +#define TXI1_ISP_V 106 +#define TEI1_ISP_V 107 + +#define PRT_ISP_V 108 +#define ADU_ISP_V 109 +#define WDT_ISP_V 112 +#define DREF_ISP_V 113 + + +/* dummy ISP */ +extern void _dummy_isp( void ); + +/* Non Maskable Interrupt */ +extern void _nmi_isp( void ); + +/* User Break Controller */ +extern void _usb_isp( void ); + +/* External interrupts 0-7 */ +extern void _irq0_isp( void ); +extern void _irq1_isp( void ); +extern void _irq2_isp( void ); +extern void _irq3_isp( void ); +extern void _irq4_isp( void ); +extern void _irq5_isp( void ); +extern void _irq6_isp( void ); +extern void _irq7_isp( void ); + +/* DMA - Controller */ +extern void _dma0_isp( void ); +extern void _dma1_isp( void ); +extern void _dma2_isp( void ); +extern void _dma3_isp( void ); + +/* Interrupt Timer Unit */ +/* Timer 0 */ +extern void _imia0_isp( void ); +extern void _imib0_isp( void ); +extern void _ovi0_isp( void ); +/* Timer 1 */ +extern void _imia1_isp( void ); +extern void _imib1_isp( void ); +extern void _ovi1_isp( void ); +/* Timer 2 */ +extern void _imia2_isp( void ); +extern void _imib2_isp( void ); +extern void _ovi2_isp( void ); +/* Timer 3 */ +extern void _imia3_isp( void ); +extern void _imib3_isp( void ); +extern void _ovi3_isp( void ); +/* Timer 4 */ +extern void _imia4_isp( void ); +extern void _imib4_isp( void ); +extern void _ovi4_isp( void ); + +/* seriell interfaces */ +extern void _eri0_isp( void ); +extern void _rxi0_isp( void ); +extern void _txi0_isp( void ); +extern void _tei0_isp( void ); +extern void _eri1_isp( void ); +extern void _rxi1_isp( void ); +extern void _txi1_isp( void ); +extern void _tei1_isp( void ); + +/* Parity Control Unit of the Bus State Controllers */ +extern void _prt_isp( void ); + +/* ADC */ +extern void _adu_isp( void ); + +/* Watchdog Timer */ +extern void _wdt_isp( void ); + +/* DRAM refresh control unit of bus state controller */ +extern void _dref_isp( void ); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/c/src/exec/score/cpu/sh/iosh7030.h b/c/src/exec/score/cpu/sh/iosh7030.h new file mode 100644 index 0000000000..48463aed47 --- /dev/null +++ b/c/src/exec/score/cpu/sh/iosh7030.h @@ -0,0 +1,223 @@ +/* + * This include file contains information pertaining to the Hitachi SH + * processor. + * + * NOTE: NOT ALL VALUES HAVE BEEN CHECKED !! + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which + * contained no copyright notice. + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#ifndef __IOSH7030_H +#define __IOSH7030_H + +/* + * After each line is explained whether the access is char short or long. + * The functions read/writeb, w, l, 8, 16, 32 can be found + * in exec/score/cpu/sh/sh_io.h + * + * 8 bit == char ( readb, writeb, read8, write8) + * 16 bit == short ( readw, writew, read16, write16 ) + * 32 bit == long ( readl, writel, read32, write32 ) + */ + +#define SCI0_SMR 0x05fffec0 /* char */ +#define SCI0_BRR 0x05fffec1 /* char */ +#define SCI0_SCR 0x05fffec2 /* char */ +#define SCI0_TDR 0x05fffec3 /* char */ +#define SCI0_SSR 0x05fffec4 /* char */ +#define SCI0_RDR 0x05fffec5 /* char */ + +#define SCI1_SMR 0x05fffec8 /* char */ +#define SCI1_BRR 0x05fffec9 /* char */ +#define SCI1_SCR 0x05fffeca /* char */ +#define SCI1_TDR 0x05fffecb /* char */ +#define SCI1_SSR 0x05fffecc /* char */ +#define SCI1_RDR 0x05fffecd /* char */ + + +#define ADDRAH 0x05fffee0 /* char */ +#define ADDRAL 0x05fffee1 /* char */ +#define ADDRBH 0x05fffee2 /* char */ +#define ADDRBL 0x05fffee3 /* char */ +#define ADDRCH 0x05fffee4 /* char */ +#define ADDRCL 0x05fffee5 /* char */ +#define ADDRDH 0x05fffee6 /* char */ +#define ADDRDL 0x05fffee7 /* char */ +#define AD_DRA 0x05fffee0 /* short */ +#define AD_DRB 0x05fffee2 /* short */ +#define AD_DRC 0x05fffee4 /* short */ +#define AD_DRD 0x05fffee6 /* short */ +#define ADCSR 0x05fffee8 /* char */ +#define ADCR 0x05fffee9 /* char */ + +/*ITU SHARED*/ +#define ITU_TSTR 0x05ffff00 /* char */ +#define ITU_TSNC 0x05ffff01 /* char */ +#define ITU_TMDR 0x05ffff02 /* char */ +#define ITU_TFCR 0x05ffff03 /* char */ + +/*ITU CHANNEL 0*/ +#define ITU_TCR0 0x05ffff04 /* char */ +#define ITU_TIOR0 0x05ffff05 /* char */ +#define ITU_TIER0 0x05ffff06 /* char */ +#define ITU_TSR0 0x05ffff07 /* char */ +#define ITU_TCNT0 0x05ffff08 /* short */ +#define ITU_GRA0 0x05ffff0a /* short */ +#define ITU_GRB0 0x05ffff0c /* short */ + + /*ITU CHANNEL 1*/ +#define ITU_TCR1 0x05ffff0E /* char */ +#define ITU_TIOR1 0x05ffff0F /* char */ +#define ITU_TIER1 0x05ffff10 /* char */ +#define ITU_TSR1 0x05ffff11 /* char */ +#define ITU_TCNT1 0x05ffff12 /* short */ +#define ITU_GRA1 0x05ffff14 /* short */ +#define ITU_GRB1 0x05ffff16 /* short */ + + + /*ITU CHANNEL 2*/ +#define ITU_TCR2 0x05ffff18 /* char */ +#define ITU_TIOR2 0x05ffff19 /* char */ +#define ITU_TIER2 0x05ffff1A /* char */ +#define ITU_TSR2 0x05ffff1B /* char */ +#define ITU_TCNT2 0x05ffff1C /* short */ +#define ITU_GRA2 0x05ffff1E /* short */ +#define ITU_GRB2 0x05ffff20 /* short */ + + /*ITU CHANNEL 3*/ +#define ITU_TCR3 0x05ffff22 /* char */ +#define ITU_TIOR3 0x05ffff23 /* char */ +#define ITU_TIER3 0x05ffff24 /* char */ +#define ITU_TSR3 0x05ffff25 /* char */ +#define ITU_TCNT3 0x05ffff26 /* short */ +#define ITU_GRA3 0x05ffff28 /* short */ +#define ITU_GRB3 0x05ffff2A /* short */ +#define ITU_BRA3 0x05ffff2C /* short */ +#define ITU_BRB3 0x05ffff2E /* short */ + + /*ITU CHANNELS 0-4 SHARED*/ +#define ITU_TOCR 0x05ffff31 /* char */ + + /*ITU CHANNEL 4*/ +#define ITU_TCR4 0x05ffff32 /* char */ +#define ITU_TIOR4 0x05ffff33 /* char */ +#define ITU_TIER4 0x05ffff34 /* char */ +#define ITU_TSR4 0x05ffff35 /* char */ +#define ITU_TCNT4 0x05ffff36 /* short */ +#define ITU_GRA4 0x05ffff38 /* short */ +#define ITU_GRB4 0x05ffff3A /* short */ +#define ITU_BRA4 0x05ffff3C /* short */ +#define ITU_BRB4 0x05ffff3E /* short */ + + /*DMAC CHANNELS 0-3 SHARED*/ +#define DMAOR 0x05ffff48 /* short */ + + /*DMAC CHANNEL 0*/ +#define DMA_SAR0 0x05ffff40 /* long */ +#define DMA_DAR0 0x05ffff44 /* long */ +#define DMA_TCR0 0x05ffff4a /* short */ +#define DMA_CHCR0 0x05ffff4e /* short */ + + /*DMAC CHANNEL 1*/ +#define DMA_SAR1 0x05ffff50 /* long */ +#define DMA_DAR1 0x05ffff54 /* long */ +#define DMA_TCR1 0x05fffF5a /* short */ +#define DMA_CHCR1 0x05ffff5e /* short */ + + /*DMAC CHANNEL 3*/ +#define DMA_SAR3 0x05ffff60 /* long */ +#define DMA_DAR3 0x05ffff64 /* long */ +#define DMA_TCR3 0x05fffF6a /* short */ +#define DMA_CHCR3 0x05ffff6e /* short */ + +/*DMAC CHANNEL 4*/ +#define DMA_SAR4 0x05ffff70 /* long */ +#define DMA_DAR4 0x05ffff74 /* long */ +#define DMA_TCR4 0x05fffF7a /* short */ +#define DMA_CHCR4 0x05ffff7e /* short */ + +/*INTC*/ +#define INTC_IPRA 0x05ffff84 /* short */ +#define INTC_IPRB 0x05ffff86 /* short */ +#define INTC_IPRC 0x05ffff88 /* short */ +#define INTC_IPRD 0x05ffff8A /* short */ +#define INTC_IPRE 0x05ffff8C /* short */ +#define INTC_ICR 0x05ffff8E /* short */ + +/*UBC*/ +#define UBC_BARH 0x05ffff90 /* short */ +#define UBC_BARL 0x05ffff92 /* short */ +#define UBC_BAMRH 0x05ffff94 /* short */ +#define UBC_BAMRL 0x05ffff96 /* short */ +#define UBC_BBR 0x05ffff98 /* short */ + +/*BSC*/ +#define BSC_BCR 0x05ffffA0 /* short */ +#define BSC_WCR1 0x05ffffA2 /* short */ +#define BSC_WCR2 0x05ffffA4 /* short */ +#define BSC_WCR3 0x05ffffA6 /* short */ +#define BSC_DCR 0x05ffffA8 /* short */ +#define BSC_PCR 0x05ffffAA /* short */ +#define BSC_RCR 0x05ffffAC /* short */ +#define BSC_RTCSR 0x05ffffAE /* short */ +#define BSC_RTCNT 0x05ffffB0 /* short */ +#define BSC_RTCOR 0x05ffffB2 /* short */ + +/*WDT*/ +#define WDT_TCSR 0x05ffffB8 /* char */ +#define WDT_TCNT 0x05ffffB9 /* char */ +#define WDT_RSTCSR 0x05ffffBB /* char */ + +/*POWER DOWN STATE*/ +#define PDT_SBYCR 0x05ffffBC /* char */ + +/*PORT A*/ +#define PADR 0x05ffffC0 /* short */ + +/*PORT B*/ +#define PBDR 0x05ffffC2 /* short */ + + /*PORT C*/ +#define PCDR 0x05ffffD0 /* short */ + +/*PFC*/ +#define PFC_PAIOR 0x05ffffC4 /* short */ +#define PFC_PBIOR 0x05ffffC6 /* short */ +#define PFC_PACR1 0x05ffffC8 /* short */ +#define PFC_PACR2 0x05ffffCA /* short */ +#define PFC_PBCR1 0x05ffffCC /* short */ +#define PFC_PBCR2 0x05ffffCE /* short */ +#define PFC_CASCR 0x05ffffEE /* short */ + +/*TPC*/ +#define TPC_TPMR 0x05ffffF0 /* short */ +#define TPC_TPCR 0x05ffffF1 /* short */ +#define TPC_NDERH 0x05ffffF2 /* short */ +#define TPC_NDERL 0x05ffffF3 /* short */ +#define TPC_NDRB 0x05ffffF4 /* char */ +#define TPC_NDRA 0x05ffff5F /* char */ +#define TPC_NDRB1 0x05ffffF6 /* char */ +#define TPC_NDRA1 0x05ffffF7 /* char */ + +#endif diff --git a/c/src/exec/score/cpu/sh/ispsh7032.c b/c/src/exec/score/cpu/sh/ispsh7032.c new file mode 100644 index 0000000000..1643785810 --- /dev/null +++ b/c/src/exec/score/cpu/sh/ispsh7032.c @@ -0,0 +1,252 @@ +/* + * This file contains the isp frames for the user interrupts. + * From these procedures __ISR_Handler is called with the vector number + * as argument. + * + * __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in + * some releases of gcc doesn't properly handle #pragma interrupt, if a + * file contains both isrs and normal functions. + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include +#include +#include + +/* + * This is a exception vector table + * + * It has the same structure like the actual vector table (vectab) + */ +proc_ptr _Hardware_isr_Table[256]={ +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, +_nmi_isp, _usb_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, +/* trapa 0 -31 */ +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +/* irq 64 ... */ +_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp, +_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp, +_dma0_isp, _dummy_isp, _dma1_isp, _dummy_isp, +_dma2_isp, _dummy_isp, _dma3_isp, _dummy_isp, +_imia0_isp, _imib0_isp, _ovi0_isp, _dummy_isp, +_imia1_isp, _imib1_isp, _ovi1_isp, _dummy_isp, +_imia2_isp, _imib2_isp, _ovi2_isp, _dummy_isp, +_imia3_isp, _imib3_isp, _ovi3_isp, _dummy_isp, +_imia4_isp, _imib4_isp, _ovi4_isp, _dummy_isp, +_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp, +_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp, +_prt_isp, _adu_isp, _dummy_isp, _dummy_isp, +_wdt_isp, +/* 113 */ _dref_isp +}; + +#define Str(a)#a + +/* + * Some versions of gcc and all version of egcs at least until egcs-1.0.2 + * are not able to handle #praga interrupt correctly if more than 1 isr is + * contained in a file and when optimizing. + * We try to work around this problem by using the macro below. + */ +#define isp( name, number, func)\ +asm (".global _"Str(name)"\n\t" \ + "_"Str(name)": \n\t" \ + " mov.l r0,@-r15 \n\t" \ + " mov.l r1,@-r15 \n\t" \ + " mov.l r2,@-r15 \n\t" \ + " mov.l r3,@-r15 \n\t" \ + " mov.l r4,@-r15 \n\t" \ + " mov.l r5,@-r15 \n\t" \ + " mov.l r6,@-r15 \n\t" \ + " mov.l r7,@-r15 \n\t" \ + " mov.l r14,@-r15 \n\t" \ + " sts.l pr,@-r15 \n\t" \ + " sts.l mach,@-r15 \n\t" \ + " sts.l macl,@-r15 \n\t" \ + " mov r15,r14 \n\t" \ + " mov.l "Str(name)"_k, r1\n\t" \ + " jsr @r1 \n\t" \ + " mov #"Str(number)", r4\n\t" \ + " mov r14,r15 \n\t" \ + " lds.l @r15+,macl \n\t" \ + " lds.l @r15+,mach \n\t" \ + " lds.l @r15+,pr \n\t" \ + " mov.l @r15+,r14 \n\t" \ + " mov.l @r15+,r7 \n\t" \ + " mov.l @r15+,r6 \n\t" \ + " mov.l @r15+,r5 \n\t" \ + " mov.l @r15+,r4 \n\t" \ + " mov.l @r15+,r3 \n\t" \ + " mov.l @r15+,r2 \n\t" \ + " mov.l @r15+,r1 \n\t" \ + " mov.l @r15+,r0 \n\t" \ + " rte \n\t" \ + " nop \n\t" \ + " .align 2 \n\t" \ + #name"_k: \n\t" \ + ".long "Str(func)); + +/************************************************ + * Dummy interrupt service procedure for + * interrupts being not allowed --> Trap 34 + ************************************************/ +asm(" .section .text +.global __dummy_isp +__dummy_isp: + mov.l r14,@-r15 + mov r15, r14 + trapa #34 + mov.l @r15+,r14 + rte + nop"); + +/***************************** + * Non maskable interrupt + *****************************/ +isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler); + +/***************************** + * User break controller + *****************************/ +isp( _usb_isp, USB_ISP_V, ___ISR_Handler); + +/***************************** + * External interrupts 0-7 + *****************************/ +isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler); +isp( _irq1_isp, IRQ1_ISP_V, ___ISR_Handler); +isp( _irq2_isp, IRQ2_ISP_V, ___ISR_Handler); +isp( _irq3_isp, IRQ3_ISP_V, ___ISR_Handler); +isp( _irq4_isp, IRQ4_ISP_V, ___ISR_Handler); +isp( _irq5_isp, IRQ5_ISP_V, ___ISR_Handler); +isp( _irq6_isp, IRQ6_ISP_V, ___ISR_Handler); +isp( _irq7_isp, IRQ7_ISP_V, ___ISR_Handler); + +/***************************** + * DMA - controller + *****************************/ +isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler); +isp( _dma1_isp, DMA1_ISP_V, ___ISR_Handler); +isp( _dma2_isp, DMA2_ISP_V, ___ISR_Handler); +isp( _dma3_isp, DMA3_ISP_V, ___ISR_Handler); + + +/***************************** + * Interrupt timer unit + *****************************/ + +/***************************** + * Timer 0 + *****************************/ +isp( _imia0_isp, IMIA0_ISP_V, ___ISR_Handler); +isp( _imib0_isp, IMIB0_ISP_V, ___ISR_Handler); +isp( _ovi0_isp, OVI0_ISP_V, ___ISR_Handler); + +/***************************** + * Timer 1 + *****************************/ +isp( _imia1_isp, IMIA1_ISP_V, ___ISR_Handler); +isp( _imib1_isp, IMIB1_ISP_V, ___ISR_Handler); +isp( _ovi1_isp, OVI1_ISP_V, ___ISR_Handler); + +/***************************** + * Timer 2 + *****************************/ +isp( _imia2_isp, IMIA2_ISP_V, ___ISR_Handler); +isp( _imib2_isp, IMIB2_ISP_V, ___ISR_Handler); +isp( _ovi2_isp, OVI2_ISP_V, ___ISR_Handler); + +/***************************** + * Timer 3 + *****************************/ +isp( _imia3_isp, IMIA3_ISP_V, ___ISR_Handler); +isp( _imib3_isp, IMIB3_ISP_V, ___ISR_Handler); +isp( _ovi3_isp, OVI3_ISP_V, ___ISR_Handler); + +/***************************** + * Timer 4 + *****************************/ +isp( _imia4_isp, IMIA4_ISP_V, ___ISR_Handler); +isp( _imib4_isp, IMIB4_ISP_V, ___ISR_Handler); +isp( _ovi4_isp, OVI4_ISP_V, ___ISR_Handler); + + +/***************************** + * Serial interfaces + *****************************/ + +/***************************** + * Serial interface 0 + *****************************/ +isp( _eri0_isp, ERI0_ISP_V, ___ISR_Handler); +isp( _rxi0_isp, RXI0_ISP_V, ___ISR_Handler); +isp( _txi0_isp, TXI0_ISP_V, ___ISR_Handler); +isp( _tei0_isp, TEI0_ISP_V, ___ISR_Handler); + +/***************************** + * Serial interface 1 + *****************************/ +isp( _eri1_isp, ERI1_ISP_V, ___ISR_Handler); +isp( _rxi1_isp, RXI1_ISP_V, ___ISR_Handler); +isp( _txi1_isp, TXI1_ISP_V, ___ISR_Handler); +isp( _tei1_isp, TEI1_ISP_V, ___ISR_Handler); + + +/***************************** + * Parity control unit of + * the bus state controller + *****************************/ +isp( _prt_isp, PRT_ISP_V, ___ISR_Handler); + + +/****************************** + * Analog digital converter + * ADC + ******************************/ +isp( _adu_isp, ADU_ISP_V, ___ISR_Handler); + + +/****************************** + * Watchdog timer + ******************************/ +isp( _wdt_isp, WDT_ISP_V, ___ISR_Handler); + + +/****************************** + * DRAM refresh control unit + * of bus state controller + ******************************/ +isp( _dref_isp, DREF_ISP_V, ___ISR_Handler); diff --git a/c/src/exec/score/cpu/sh/rtems.c b/c/src/exec/score/cpu/sh/rtems.c new file mode 100644 index 0000000000..b0e0e22e02 --- /dev/null +++ b/c/src/exec/score/cpu/sh/rtems.c @@ -0,0 +1,71 @@ +/* + * This file contains the single entry point code for + * the SH implementation of RTEMS. + * + * NOTE: This is supposed to be a .S or .s file NOT a C file. + * + * NOTE: UNTESTED, very likely this does not not work. + * + * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +/* + * This is supposed to be an assembly file. This means that system.h + * and cpu.h should not be included in a "real" rtems file. + */ + +/* #include */ +/* #include */ +/* #include "asm.h" */ + +/* + * This should work but due to a bug in rtems building scheme it doesn't work + */ + +/* #include */ + +extern void* _Entry_points[] ; + +/* + * RTEMS + * + * This routine jumps to the directive indicated in the + * CPU defined register. This routine is used when RTEMS is + * linked by itself and placed in ROM. This routine is the + * first address in the ROM space for RTEMS. The user "calls" + * this address with the directive arguments in the normal place. + * This routine then jumps indirectly to the correct directive + * preserving the arguments. The directive should not realize + * it has been "wrapped" in this way. The table "_Entry_points" + * is used to look up the directive. + */ + +void __RTEMS() +{ + asm volatile ( + ".global _RTEMS +_RTEMS:" ); + + asm volatile ( + "jmp %0 + rts + nop" + :: "m" (_Entry_points) ); +} diff --git a/c/src/exec/score/cpu/sh/sh.h b/c/src/exec/score/cpu/sh/sh.h new file mode 100644 index 0000000000..1561732c33 --- /dev/null +++ b/c/src/exec/score/cpu/sh/sh.h @@ -0,0 +1,174 @@ +/* sh.h + * + * This include file contains information pertaining to the Hitachi SH + * processor. + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#ifndef _sh_h +#define _sh_h + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This file contains the information required to build + * RTEMS for a particular member of the "SH" family. + * + * It does this by setting variables to indicate which implementation + * dependent features are present in a particular member of the family. + */ + +#if defined(sh7032) + +#define CPU_MODEL_NAME "SH 7032" + +#define SH_HAS_FPU 0 + +/* + * If the following macro is set to 0 there will be no software irq stack + */ +#define SH_HAS_SEPARATE_STACKS 1 + +#else + +#error "Unsupported CPU Model" + +#endif + +/* + * Define the name of the CPU family. + */ + +#define CPU_NAME "Hitachi SH" + +#ifndef ASM + +/* + * Mask for disabling interrupts + */ +#define SH_IRQDIS_VALUE 0xf0 + +#define sh_disable_interrupts( _level ) \ + asm volatile ( \ + "stc sr,%0\n\t" \ + "ldc %1,sr\n\t"\ + : "=r" (_level ) \ + : "r" (SH_IRQDIS_VALUE) ); + +#define sh_enable_interrupts( _level ) \ + asm volatile( "ldc %0,sr\n\t" \ + "nop\n\t" \ + :: "r" (_level) ); + +/* + * This temporarily restores the interrupt to _level before immediately + * disabling them again. This is used to divide long RTEMS critical + * sections into two or more parts. The parameter _level is not + * modified. + */ + +#define sh_flash_interrupts( _level ) \ + asm volatile( \ + "ldc %1,sr\n\t" \ + "nop\n\t" \ + "ldc %0,sr\n\t" \ + "nop\n\t" \ + : : "r" (SH_IRQDIS_VALUE), "r" (_level) ); + +#define sh_get_interrupt_level( _level ) \ +{ \ + register unsigned32 _tmpsr ; \ + \ + asm volatile( "stc sr, %0" : "=r" (_tmpsr) ); \ + _level = (_tmpsr & 0xf0) >> 4 ; \ +} + +#define sh_set_interrupt_level( _newlevel ) \ +{ \ + register unsigned32 _tmpsr; \ + \ + asm volatile ( "stc sr, %0" : "=r" (_tmpsr) ); \ + _tmpsr = ( _tmpsr & ~0xf0 ) | ((_newlevel) << 4) ; \ + asm volatile( "ldc %0,sr" :: "r" (_tmpsr) ); \ +} + +/* + * The following routine swaps the endian format of an unsigned int. + * It must be static because it is referenced indirectly. + */ + +static inline unsigned int sh_swap_u32( + unsigned int value +) +{ + register unsigned int swapped ; + + asm volatile ( + "swap.b %1,%0 + swap.w %0,%0 + swap.b %0,%0" + : "=r" (swapped) + : "r" (value) ); + + return( swapped ); +} + +#define CPU_swap_u32( value ) sh_swap_u32( value ) + +/* + * Simple spin delay in microsecond units for device drivers. + * This is very dependent on the clock speed of the target. + * + * Since we don't have a real time clock, this is a very rough + * approximation, assuming that each cycle of the delay loop takes + * approx. 4 machine cycles. + * + * e.g.: MHZ = 20 => 5e-8 secs per instruction + * => 4 * 5e-8 secs per delay loop + */ + +#define sh_delay( microseconds ) \ +{ register unsigned int _delay = (microseconds) * (MHZ / 4 ); \ + asm volatile ( \ +"0: add #-1,%0\n \ + nop\n \ + cmp/pl %0\n \ + bt 0b\ + nop" \ + :: "r" (_delay) ); \ +} + +#define CPU_delay( microseconds ) sh_delay( microseconds ) + +extern unsigned int sh_set_irq_priority( + unsigned int irq, + unsigned int prio ); + +#endif /* !ASM */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/c/src/exec/score/cpu/sh/sh_io.h b/c/src/exec/score/cpu/sh/sh_io.h new file mode 100644 index 0000000000..2a9111e307 --- /dev/null +++ b/c/src/exec/score/cpu/sh/sh_io.h @@ -0,0 +1,48 @@ +/* + * These are some macros to access memory mapped devices + * on the SH7000-architecture. + * + * Inspired from the linux kernel's include/asm/io.h + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1996-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#ifndef _asm_io_h +#define _asm_io_h + +#define readb(addr) (*(volatile unsigned char *) (addr)) +#define readw(addr) (*(volatile unsigned short *) (addr)) +#define readl(addr) (*(volatile unsigned int *) (addr)) +#define read8(addr) (*(volatile unsigned8 *) (addr)) +#define read16(addr) (*(volatile unsigned16 *) (addr)) +#define read32(addr) (*(volatile unsigned32 *) (addr)) + +#define writeb(b,addr) ((*(volatile unsigned char *) (addr)) = (b)) +#define writew(b,addr) ((*(volatile unsigned short *) (addr)) = (b)) +#define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b)) +#define write8(b,addr) ((*(volatile unsigned8 *) (addr)) = (b)) +#define write16(b,addr) ((*(volatile unsigned16 *) (addr)) = (b)) +#define write32(b,addr) ((*(volatile unsigned32 *) (addr)) = (b)) + +#define inb(addr) readb(addr) +#define outb(b,addr) writeb(b,addr) + +#endif diff --git a/c/src/exec/score/cpu/sh/shtypes.h b/c/src/exec/score/cpu/sh/shtypes.h new file mode 100644 index 0000000000..853479c13b --- /dev/null +++ b/c/src/exec/score/cpu/sh/shtypes.h @@ -0,0 +1,67 @@ +/* + * This include file contains information pertaining to the Hitachi SH + * processor. + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#ifndef __CPU_SH_TYPES_h +#define __CPU_SH_TYPES_h + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This section defines the basic types for this processor. + */ + +typedef unsigned char unsigned8; /* unsigned 8-bit integer */ +typedef unsigned short unsigned16; /* unsigned 16-bit integer */ +typedef unsigned int unsigned32; /* unsigned 32-bit integer */ +typedef unsigned long long unsigned64; /* unsigned 64-bit integer */ + +typedef unsigned16 Priority_Bit_map_control; + +typedef signed char signed8; /* 8-bit signed integer */ +typedef signed short signed16; /* 16-bit signed integer */ +typedef signed int signed32; /* 32-bit signed integer */ +typedef signed long long signed64; /* 64 bit signed integer */ + +typedef unsigned16 boolean; /* Boolean value, external */ + /* data bus has 16 bits */ + +typedef float single_precision; /* single precision float */ +typedef double double_precision; /* double precision float */ + +typedef void sh_isr; +typedef void ( *sh_isr_entry )( void ); + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif + -- cgit v1.2.3