From bd1ecb00d955204b7c01daffe7e6e7cb8c8a765a Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Fri, 1 Mar 2002 16:21:12 +0000 Subject: 2002-02-27 Greg Menke * cpu_asm.S: Fixed exception return address, modified FP context switch so FPU is properly enabled and also doesn't screw up the exception FP handling. * idtcpu.h: Added C0_TAR, the MIPS target address register used for returning from exceptions. * iregdef.h: Added R_TAR to the stack frame so the target address can be saved on a per-exception basis. The new entry is past the end of the frame gdb cares about, so doesn't affect gdb or cpu.h stuff. * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it to obtain FPU defines without systax errors generated by the C defintions. * cpu.c: Improved interrupt level saves & restores. --- c/src/exec/score/cpu/mips/ChangeLog | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'c/src/exec/score/cpu/mips/ChangeLog') diff --git a/c/src/exec/score/cpu/mips/ChangeLog b/c/src/exec/score/cpu/mips/ChangeLog index ca93aa0d5c..ef4c51c39f 100644 --- a/c/src/exec/score/cpu/mips/ChangeLog +++ b/c/src/exec/score/cpu/mips/ChangeLog @@ -1,3 +1,19 @@ +2002-02-27 Greg Menke + + * cpu_asm.S: Fixed exception return address, modified FP context + switch so FPU is properly enabled and also doesn't screw up the + exception FP handling. + * idtcpu.h: Added C0_TAR, the MIPS target address register used for + returning from exceptions. + * iregdef.h: Added R_TAR to the stack frame so the target address + can be saved on a per-exception basis. The new entry is past the + end of the frame gdb cares about, so doesn't affect gdb or cpu.h + stuff. + * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it + to obtain FPU defines without systax errors generated by the C + defintions. + * cpu.c: Improved interrupt level saves & restores. + 2002-02-08 Joel Sherrill * iregdef.h, rtems/score/cpu.h: Reordered register in the -- cgit v1.2.3