From e54a7d33d25429ae2e0f3d2fb4a23459856545cf Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Tue, 26 Oct 1999 16:22:55 +0000 Subject: Patch from Gerwin Pfab to leave dispatching disabled on exit to ISR Thread dispatching. This allows a context switch to finish under high high interrupt rates. --- c/src/exec/score/cpu/i960/cpu_asm.S | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'c/src/exec/score/cpu/i960') diff --git a/c/src/exec/score/cpu/i960/cpu_asm.S b/c/src/exec/score/cpu/i960/cpu_asm.S index 2d92333af7..ee6e053259 100644 --- a/c/src/exec/score/cpu/i960/cpu_asm.S +++ b/c/src/exec/score/cpu/i960/cpu_asm.S @@ -152,7 +152,6 @@ __ISR_Handler: callx (g1) # invoke user ISR - st r4,__Thread_Dispatch_disable_level # unnest multitasking st r5,__ISR_Nest_level # one less ISR nest level cmpobne.f 0,r4,exit # If dispatch disabled, exit @@ -186,8 +185,10 @@ bframe: mov 0,g2 stt r4,(g3) # set _Isr_dispatch ret info st g1,16(g3) # set r4 = AC for ISR disp or 7,g3,pfp # pfp to _Isr_dispatch - -exit: mov r7,g14 # restore g14 + flushreg + b exit1 +exit: st r4,__Thread_Dispatch_disable_level +exit1: mov r7,g14 # restore g14 movq r8,g0 # restore g0-g3 movq r12,g4 # restore g4-g7 ldq _ISR_reg_save, g8 # restore g8-g11 -- cgit v1.2.3