From ae7325bdc85e1dd39f039b66ba20ca681712dcc3 Mon Sep 17 00:00:00 2001
From: Joel Sherrill <joel.sherrill@OARcorp.com>
Date: Wed, 27 Oct 1999 17:25:53 +0000
Subject: rxgen960 now compiles -- may not link.

---
 c/src/exec/score/cpu/i960/cpu.c    |  6 +++---
 c/src/exec/score/cpu/i960/i960RP.h | 14 +++++++-------
 2 files changed, 10 insertions(+), 10 deletions(-)

(limited to 'c/src/exec/score/cpu/i960')

diff --git a/c/src/exec/score/cpu/i960/cpu.c b/c/src/exec/score/cpu/i960/cpu.c
index 07ca05f69b..b1f29ff1bf 100644
--- a/c/src/exec/score/cpu/i960/cpu.c
+++ b/c/src/exec/score/cpu/i960/cpu.c
@@ -67,10 +67,10 @@ unsigned32 _CPU_ISR_Get_level( void )
  */
 
 #if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
-#define _Is_vector_caching_enabled( _prcb ) \
+#define i960_vector_caching_enabled( _prcb ) \
    ((_prcb)->control_tbl->icon & 0x2000)
 #elif defined(__i960RP__)
-#define _Is_vector_caching_enabled( _prcb ) \
+#define i960_vector_caching_enabled( _prcb ) \
    ((*((unsigned int *) ICON_ADDR)) & 0x2000)
 #endif
 
@@ -93,7 +93,7 @@ void _CPU_ISR_install_raw_handler(
 
   prcb->intr_tbl[ vector + 1 ] = new_handler;
 
-  if ( _Is_vector_caching_enabled( prcb ) )
+  if ( i960_vector_caching_enabled( prcb ) )
     if ( (vector & 0xf) == 0x2 )       /* cacheable? */
       cached_intr_tbl[ vector >> 4 ] = new_handler;
 }
diff --git a/c/src/exec/score/cpu/i960/i960RP.h b/c/src/exec/score/cpu/i960/i960RP.h
index 4cda73eff0..25ed29037a 100644
--- a/c/src/exec/score/cpu/i960/i960RP.h
+++ b/c/src/exec/score/cpu/i960/i960RP.h
@@ -270,13 +270,13 @@
 
 /* Byte order bit for region configuration */
 /* Set to Little Endian for the 80960RP*/
-#define BYTE_ORDER BIG_ENDIAN(0)
-#define BUS_WIDTH(bw)  ((bw==16)?(1<<22):(0)) | ((bw==32)?(2<<22):(0))
-#define BIG_ENDIAN(on) ((on)?(0x1<<31):0)
-#define BYTE_N(n,data)  (((unsigned)(data) >> (n*8)) & 0xFF)
-#define BUS_WIDTH_8 0
-#define BUS_WIDTH_16 (1<<22)
-#define BUS_WIDTH_32 (1<<23)
+#define I960RP_BYTE_ORDER I960RP_BIG_ENDIAN(0)
+#define I960RP_BUS_WIDTH(bw)  ((bw==16)?(1<<22):(0)) | ((bw==32)?(2<<22):(0))
+#define I960RP_BIG_ENDIAN(on) ((on)?(0x1<<31):0)
+#define I960RP_BYTE_N(n,data)  (((unsigned)(data) >> (n*8)) & 0xFF)
+#define I960RP_BUS_WIDTH_8 0
+#define I960RP_BUS_WIDTH_16 (1<<22)
+#define I960RP_BUS_WIDTH_32 (1<<23)
 
 
 /* ATU Register Definitions */
-- 
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