From a324355fb87d556edac0fee0138eb393767c5f98 Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Fri, 12 Apr 2002 15:08:13 +0000 Subject: 2002-03-29 Ralf Corsepius * rtems/score/idtr.h: New file, extracted from libcpu/cpu.h. * rtems/score/interrupts.h: New file, extracted from libcpu/cpu.h. * rtems/score/registers.h: New file, moved from libcpu. * Makefile.am: Reflect changes above. * cpu.c: Don't include cpuModel.h, #include , #include , #include . * rtems/score/cpu.h: Don't include libcpu/cpu.h. #include , #include . --- c/src/exec/score/cpu/i386/ChangeLog | 14 ++ c/src/exec/score/cpu/i386/Makefile.am | 6 +- c/src/exec/score/cpu/i386/cpu.c | 6 +- c/src/exec/score/cpu/i386/rtems/score/cpu.h | 3 +- c/src/exec/score/cpu/i386/rtems/score/idtr.h | 62 +++++++ c/src/exec/score/cpu/i386/rtems/score/interrupts.h | 75 +++++++++ c/src/exec/score/cpu/i386/rtems/score/registers.h | 184 +++++++++++++++++++++ 7 files changed, 346 insertions(+), 4 deletions(-) create mode 100644 c/src/exec/score/cpu/i386/rtems/score/idtr.h create mode 100644 c/src/exec/score/cpu/i386/rtems/score/interrupts.h create mode 100644 c/src/exec/score/cpu/i386/rtems/score/registers.h (limited to 'c/src/exec/score/cpu/i386') diff --git a/c/src/exec/score/cpu/i386/ChangeLog b/c/src/exec/score/cpu/i386/ChangeLog index 96bf0ec9e9..980a97e8f3 100644 --- a/c/src/exec/score/cpu/i386/ChangeLog +++ b/c/src/exec/score/cpu/i386/ChangeLog @@ -1,3 +1,17 @@ +2002-03-29 Ralf Corsepius + + * rtems/score/idtr.h: New file, extracted from libcpu/cpu.h. + * rtems/score/interrupts.h: New file, extracted from libcpu/cpu.h. + * rtems/score/registers.h: New file, moved from libcpu. + * Makefile.am: Reflect changes above. + * cpu.c: Don't include cpuModel.h, + #include , + #include , + #include . + * rtems/score/cpu.h: Don't include libcpu/cpu.h. + #include , + #include . + 2001-04-03 Joel Sherrill * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. diff --git a/c/src/exec/score/cpu/i386/Makefile.am b/c/src/exec/score/cpu/i386/Makefile.am index f26300f0f9..20fca0d9f9 100644 --- a/c/src/exec/score/cpu/i386/Makefile.am +++ b/c/src/exec/score/cpu/i386/Makefile.am @@ -27,7 +27,11 @@ include_rtems_scoredir = $(includedir)/rtems/score include_rtems_score_HEADERS = \ rtems/score/cpu.h \ rtems/score/i386.h \ - rtems/score/types.h + rtems/score/types.h \ + rtems/score/interrupts.h \ + rtems/score/registers.h \ + rtems/score/idtr.h + PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \ $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h) diff --git a/c/src/exec/score/cpu/i386/cpu.c b/c/src/exec/score/cpu/i386/cpu.c index f59a5f6673..b55be879ab 100644 --- a/c/src/exec/score/cpu/i386/cpu.c +++ b/c/src/exec/score/cpu/i386/cpu.c @@ -12,12 +12,14 @@ * $Id$ */ +#include #include +#include #include +#include + #include #include -#include - /* _CPU_Initialize * diff --git a/c/src/exec/score/cpu/i386/rtems/score/cpu.h b/c/src/exec/score/cpu/i386/rtems/score/cpu.h index b601bcf7ea..a6ea2c7628 100644 --- a/c/src/exec/score/cpu/i386/rtems/score/cpu.h +++ b/c/src/exec/score/cpu/i386/rtems/score/cpu.h @@ -21,10 +21,11 @@ extern "C" { #endif #include /* pick up machine definitions */ -#include #ifndef ASM #include +#include /* formerly in libcpu/cpu.h> */ +#include /* formerly part of libcpu */ #endif /* conditional compilation parameters */ diff --git a/c/src/exec/score/cpu/i386/rtems/score/idtr.h b/c/src/exec/score/cpu/i386/rtems/score/idtr.h new file mode 100644 index 0000000000..7c4f95214f --- /dev/null +++ b/c/src/exec/score/cpu/i386/rtems/score/idtr.h @@ -0,0 +1,62 @@ +/* + * This file contains definitions for data structure related + * to Intel system programming. More information can be found + * on Intel site and more precisely in the following book : + * + * Pentium Processor familly + * Developper's Manual + * + * Volume 3 : Architecture and Programming Manual + * + * Formerly contained in and extracted from libcpu/i386/cpu.h. + * + * Copyright (C) 1998 Eric Valette (valette@crf.canon.fr) + * Canon Centre Recherche France. + * + * The license and distribution terms for this file may be + * found in found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + * + * Applications must not include this file directly. + */ + +#ifndef _rtems_score_idtr_h +#define _rtems_score_idtr_h + +/* + * See page 14.9 Figure 14-2. + * + */ +typedef struct +{ + unsigned int low_offsets_bits:16; + unsigned int segment_selector:16; + unsigned int fixed_value_bits:8; + unsigned int gate_type:5; + unsigned int privilege:2; + unsigned int present:1; + unsigned int high_offsets_bits:16; +} interrupt_gate_descriptor; + +/* + * C callable function enabling to create a interrupt_gate_descriptor + */ +extern void create_interrupt_gate_descriptor (interrupt_gate_descriptor*, rtems_raw_irq_hdl); + +/* + * C callable function enabling to get easily usable info from + * the actual value of IDT register. + */ +extern void i386_get_info_from_IDTR (interrupt_gate_descriptor** table, + unsigned* limit); + +/* + * C callable function enabling to change the value of IDT register. Must be called + * with interrupts masked at processor level!!!. + */ +extern void i386_set_IDTR (interrupt_gate_descriptor* table, + unsigned limit); + +#endif diff --git a/c/src/exec/score/cpu/i386/rtems/score/interrupts.h b/c/src/exec/score/cpu/i386/rtems/score/interrupts.h new file mode 100644 index 0000000000..bcc1dfb85a --- /dev/null +++ b/c/src/exec/score/cpu/i386/rtems/score/interrupts.h @@ -0,0 +1,75 @@ +/* + * i386 interrupt macros. + * + * Formerly contained in and extracted from libcpu/i386/cpu.h + * + * COPYRIGHT (c) 1998 valette@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + * + * Applications must not include this file directly. + */ + +#ifndef _rtems_score_interrupts_h +#define _rtems_score_interrupts_h + +#ifndef ASM + +struct __rtems_raw_irq_connect_data__; + +typedef void (*rtems_raw_irq_hdl) (void); +typedef void (*rtems_raw_irq_enable) (const struct __rtems_raw_irq_connect_data__*); +typedef void (*rtems_raw_irq_disable) (const struct __rtems_raw_irq_connect_data__*); +typedef int (*rtems_raw_irq_is_enabled) (const struct __rtems_raw_irq_connect_data__*); + +/* + * Interrupt Level Macros + */ + +#define i386_disable_interrupts( _level ) \ + { \ + asm volatile ( "pushf ; \ + cli ; \ + pop %0" \ + : "=rm" ((_level)) \ + ); \ + } + +#define i386_enable_interrupts( _level ) \ + { \ + asm volatile ( "push %0 ; \ + popf" \ + : : "rm" ((_level)) : "cc" \ + ); \ + } + +#define i386_flash_interrupts( _level ) \ + { \ + asm volatile ( "push %0 ; \ + popf ; \ + cli" \ + : : "rm" ((_level)) : "cc" \ + ); \ + } + +#define i386_get_interrupt_level( _level ) \ + do { \ + register unsigned32 _eflags; \ + \ + asm volatile ( "pushf ; \ + pop %0" \ + : "=rm" ((_eflags)) \ + ); \ + \ + _level = (_eflags & EFLAGS_INTR_ENABLE) ? 0 : 1; \ + } while (0) + +#define _CPU_ISR_Disable( _level ) i386_disable_interrupts( _level ) +#define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level ) + +#endif +#endif diff --git a/c/src/exec/score/cpu/i386/rtems/score/registers.h b/c/src/exec/score/cpu/i386/rtems/score/registers.h new file mode 100644 index 0000000000..993b7fb834 --- /dev/null +++ b/c/src/exec/score/cpu/i386/rtems/score/registers.h @@ -0,0 +1,184 @@ +/* registers.h + * + * This file contains definition and constants related to Intel Cpu + * + * COPYRIGHT (c) 1998 valette@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#ifndef _rtems_score_registers_h +#define _rtems_score_registers_h + +/* + * definition related to EFLAGS + */ +#define EFLAGS_CARRY 0x1 +#define EFLAGS_PARITY 0x4 + +#define EFLAGS_AUX_CARRY 0x10 +#define EFLAGS_ZERO 0x40 +#define EFLAGS_SIGN 0x80 + +#define EFLAGS_TRAP 0x100 +#define EFLAGS_INTR_ENABLE 0x200 +#define EFLAGS_DIRECTION 0x400 +#define EFLAGS_OVERFLOW 0x800 + +#define EFLAGS_IOPL_MASK 0x3000 +#define EFLAGS_NESTED_TASK 0x8000 + +#define EFLAGS_RESUME 0x10000 +#define EFLAGS_VIRTUAL_MODE 0x20000 +#define EFLAGS_ALIGN_CHECK 0x40000 +#define EFLAGS_VIRTUAL_INTR 0x80000 + +#define EFLAGS_VIRTUAL_INTR_PEND 0x100000 +#define EFLAGS_ID 0x200000 + +/* + * definitions related to CR0 + */ +#define CR0_PROTECTION_ENABLE 0x1 +#define CR0_MONITOR_COPROC 0x2 +#define CR0_COPROC_SOFT_EMUL 0x4 +#define CR0_FLOATING_INSTR_EXCEPTION 0x8 + +#define CR0_EXTENSION_TYPE 0x10 +#define CR0_NUMERIC_ERROR 0x20 + +#define CR0_WRITE_PROTECT 0x10000 +#define CR0_ALIGMENT_MASK 0x40000 + +#define CR0_NO_WRITE_THROUGH 0x20000000 +#define CR0_PAGE_LEVEL_CACHE_DISABLE 0x40000000 +#define CR0_PAGING 0x80000000 + +/* + * definitions related to CR3 + */ + +#define CR3_PAGE_CACHE_DISABLE 0x10 +#define CR3_PAGE_WRITE_THROUGH 0x8 + + +#ifndef ASM + +/* + * definition of eflags registers has a bit field structure + */ +typedef struct { + /* + * fist byte : bits 0->7 + */ + unsigned int carry : 1; + unsigned int : 1; + unsigned int parity : 1; + unsigned int : 1; + + unsigned int auxiliary_carry : 1; + unsigned int : 1; + unsigned int zero : 1; /* result is zero */ + unsigned int sign : 1; /* result is less than zero */ + /* + * Second byte : bits 7->15 + */ + unsigned int trap : 1; + unsigned int intr_enable : 1; /* set => intr on */ + unsigned int direction : 1; /* set => autodecrement */ + unsigned int overflow : 1; + + unsigned int IO_privilege : 2; + unsigned int nested_task : 1; + unsigned int : 1; + /* + * Third byte : bits 15->23 + */ + unsigned int resume : 1; + unsigned int virtual_mode : 1; + unsigned int aligment_check : 1; + unsigned int virtual_intr : 1; + + unsigned int virtual_intr_pending : 1; + unsigned int id : 1; + unsigned int : 2; + + /* + * fourth byte : bits 24->31 : UNUSED + */ + unsigned int : 8; +}eflags_bits; + +typedef union { + eflags_bits eflags; + unsigned int i; +}eflags; +/* + * definition of eflags registers has a bit field structure + */ +typedef struct { + /* + * fist byte : bits 0->7 + */ + unsigned int protection_enable : 1; + unsigned int monitor_coproc : 1; + unsigned int coproc_soft_emul : 1; + unsigned int floating_instr_except : 1; + + unsigned int extension_type : 1; + unsigned int numeric_error : 1; + unsigned int : 2; + /* + * second byte 8->15 : UNUSED + */ + unsigned int : 8; + /* + * third byte 16->23 + */ + unsigned int write_protect : 1; + unsigned int : 1; + unsigned int aligment_mask : 1; + unsigned int : 1; + + unsigned int : 4; + /* + * fourth byte 24->31 + */ + unsigned int : 4; + + unsigned int : 1; + unsigned int no_write_through : 1; + unsigned int page_level_cache_disable : 1; + unsigned int paging : 1; +}cr0_bits; + +typedef union { + cr0_bits cr0; + unsigned int i; +}cr0; + +/* + * definition of cr3 registers has a bit field structure + */ +typedef struct { + + unsigned int : 3; + unsigned int page_write_transparent : 1; + unsigned int page_cache_disable : 1; + unsigned int : 7; + unsigned int page_directory_base :20; +}cr3_bits; + +typedef union { + cr3_bits cr3; + unsigned int i; +}cr3; + +#endif + +#endif + -- cgit v1.2.3