From e80ac7f6c253169db44455b883783b134a469a51 Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Thu, 18 Apr 2002 13:18:11 +0000 Subject: 2002-04-18 Jay Monkman * rtems/score/cpu.h (CPU_ISR_Disable and CPU_ISR_Enable): Correct them where they correctly inform the compiler about the register they are modifying. --- c/src/exec/score/cpu/arm/rtems/score/cpu.h | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'c/src/exec/score/cpu/arm/rtems/score/cpu.h') diff --git a/c/src/exec/score/cpu/arm/rtems/score/cpu.h b/c/src/exec/score/cpu/arm/rtems/score/cpu.h index ebe494504b..a626068e2c 100644 --- a/c/src/exec/score/cpu/arm/rtems/score/cpu.h +++ b/c/src/exec/score/cpu/arm/rtems/score/cpu.h @@ -540,9 +540,10 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); #define _CPU_ISR_Disable( _level ) \ { \ (_level) = 0; \ - asm volatile ("MRS r0, cpsr \n" ); \ - asm volatile ("ORR r0, r0, #0xc0 \n" ); \ - asm volatile ("MSR cpsr, r0 \n" ); \ + asm volatile ("MRS r0, cpsr \n" \ + "ORR r0, r0, #0xc0 \n" \ + "MSR cpsr, r0 \n" \ + : : : "r0"); \ } /* @@ -553,9 +554,10 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); #define _CPU_ISR_Enable( _level ) \ { \ - asm volatile ("MRS r0, cpsr \n" ); \ - asm volatile ("AND r0, r0, #0xFFFFFF3F \n" ); \ - asm volatile ("MSR cpsr, r0 \n" ); \ + asm volatile ("MRS r0, cpsr \n" \ + "AND r0, r0, #0xFFFFFF3F \n" \ + "MSR cpsr, r0 \n" \ + : : : "r0" ); \ } /* -- cgit v1.2.3