From fd790b3431ca265c4d207893c8250f0588b43e4b Mon Sep 17 00:00:00 2001 From: Kinsey Moore Date: Tue, 5 Mar 2024 14:07:35 -0600 Subject: bsps/shared/xqspipsu: Read correct status bits When resetting the QSPI FIFOs, the driver was reading write-only bits of a register for status information when it was actually in a different register. This corrects the driver so that it reads the correct status bits. --- bsps/shared/dev/spi/xqspipsu.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'bsps') diff --git a/bsps/shared/dev/spi/xqspipsu.c b/bsps/shared/dev/spi/xqspipsu.c index c77407bdf4..93d3fa4c98 100644 --- a/bsps/shared/dev/spi/xqspipsu.c +++ b/bsps/shared/dev/spi/xqspipsu.c @@ -278,6 +278,12 @@ void XQspiPsu_Abort(XQspiPsu *InstancePtr) u32 IntrStatus, ConfigReg, FifoStatus; u32 DelayCount = 0U; +#ifdef __rtems__ + u32 FifoStatusMask = XQSPIPSU_ISR_RXEMPTY_MASK; + FifoStatusMask |= XQSPIPSU_ISR_TXEMPTY_MASK; + FifoStatusMask |= XQSPIPSU_ISR_GENFIFOEMPTY_MASK; +#endif + Xil_AssertVoid(InstancePtr != NULL); #ifdef DEBUG xil_printf("\nXQspiPsu_Abort\r\n"); @@ -329,8 +335,13 @@ void XQspiPsu_Abort(XQspiPsu *InstancePtr) */ FifoStatus = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress, +#ifdef __rtems__ + XQSPIPSU_ISR_OFFSET) & FifoStatusMask; + while(FifoStatus != FifoStatusMask) { +#else XQSPIPSU_FIFO_CTRL_OFFSET); while(FifoStatus != 0U) { +#endif if (DelayCount == MAX_DELAY_CNT) { #ifdef DEBUG xil_printf("Timeout error, FIFO reset failed.\r\n"); @@ -340,7 +351,11 @@ void XQspiPsu_Abort(XQspiPsu *InstancePtr) usleep(1); DelayCount++; FifoStatus = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress, +#ifdef __rtems__ + XQSPIPSU_ISR_OFFSET) & FifoStatusMask; +#else XQSPIPSU_FIFO_CTRL_OFFSET); +#endif } } -- cgit v1.2.3