From f8ad5bb2a442b73536cc3cecfb65a2fc796bec70 Mon Sep 17 00:00:00 2001 From: Kinsey Moore Date: Thu, 27 Aug 2020 22:13:47 -0500 Subject: bsps: Break out AArch32 GICv3 support This breaks out AArch32-specific code so that the shared GICv3 code can be reused by other architectures. --- bsps/arm/altera-cyclone-v/include/bsp/irq.h | 2 +- bsps/arm/altera-cyclone-v/include/tm27.h | 2 +- bsps/arm/headers.am | 4 - bsps/arm/imx/include/bsp/irq.h | 2 +- bsps/arm/imx/include/tm27.h | 2 +- bsps/arm/include/bsp/arm-a9mpcore-start.h | 2 +- bsps/arm/include/bsp/arm-gic-irq.h | 124 ---------- bsps/arm/include/bsp/arm-gic-regs.h | 217 ----------------- bsps/arm/include/bsp/arm-gic-tm27.h | 103 -------- bsps/arm/include/bsp/arm-gic.h | 242 ------------------- bsps/arm/realview-pbx-a9/include/bsp/irq.h | 2 +- bsps/arm/realview-pbx-a9/include/tm27.h | 2 +- bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c | 61 +++++ bsps/arm/shared/irq/irq-gic.c | 2 +- bsps/arm/shared/irq/irq-gicv3.c | 329 -------------------------- bsps/arm/xen/include/bsp/irq.h | 2 +- bsps/arm/xen/include/tm27.h | 2 +- bsps/arm/xilinx-zynq/include/bsp/irq.h | 2 +- bsps/arm/xilinx-zynq/include/tm27.h | 2 +- bsps/arm/xilinx-zynqmp/include/bsp/irq.h | 2 +- bsps/arm/xilinx-zynqmp/include/tm27.h | 2 +- bsps/headers.am | 7 + bsps/include/dev/irq/arm-gic-irq.h | 143 +++++++++++ bsps/include/dev/irq/arm-gic-regs.h | 217 +++++++++++++++++ bsps/include/dev/irq/arm-gic-tm27.h | 103 ++++++++ bsps/include/dev/irq/arm-gic.h | 242 +++++++++++++++++++ bsps/shared/dev/irq/arm-gicv3.c | 354 ++++++++++++++++++++++++++++ 27 files changed, 1141 insertions(+), 1033 deletions(-) delete mode 100644 bsps/arm/include/bsp/arm-gic-irq.h delete mode 100644 bsps/arm/include/bsp/arm-gic-regs.h delete mode 100644 bsps/arm/include/bsp/arm-gic-tm27.h delete mode 100644 bsps/arm/include/bsp/arm-gic.h create mode 100644 bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c delete mode 100644 bsps/arm/shared/irq/irq-gicv3.c create mode 100644 bsps/include/dev/irq/arm-gic-irq.h create mode 100644 bsps/include/dev/irq/arm-gic-regs.h create mode 100644 bsps/include/dev/irq/arm-gic-tm27.h create mode 100644 bsps/include/dev/irq/arm-gic.h create mode 100644 bsps/shared/dev/irq/arm-gicv3.c (limited to 'bsps') diff --git a/bsps/arm/altera-cyclone-v/include/bsp/irq.h b/bsps/arm/altera-cyclone-v/include/bsp/irq.h index 4247d01747..bd2bba4caa 100644 --- a/bsps/arm/altera-cyclone-v/include/bsp/irq.h +++ b/bsps/arm/altera-cyclone-v/include/bsp/irq.h @@ -27,7 +27,7 @@ #include #include -#include +#include #include #ifdef __cplusplus diff --git a/bsps/arm/altera-cyclone-v/include/tm27.h b/bsps/arm/altera-cyclone-v/include/tm27.h index 23019a539a..00d7883f38 100644 --- a/bsps/arm/altera-cyclone-v/include/tm27.h +++ b/bsps/arm/altera-cyclone-v/include/tm27.h @@ -33,7 +33,7 @@ * @brief Intel Cyclone V TM27 Support. */ -#include +#include /** @} */ diff --git a/bsps/arm/headers.am b/bsps/arm/headers.am index f0d498c8f4..bff9a16fc8 100644 --- a/bsps/arm/headers.am +++ b/bsps/arm/headers.am @@ -17,10 +17,6 @@ include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-a9mpcore-regs.h include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-a9mpcore-start.h include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-cp15-start.h include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-errata.h -include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-irq.h -include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-regs.h -include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-tm27.h -include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic.h include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl050-regs.h include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl050.h include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl111-fb.h diff --git a/bsps/arm/imx/include/bsp/irq.h b/bsps/arm/imx/include/bsp/irq.h index 78b48e1613..1eea075bdc 100644 --- a/bsps/arm/imx/include/bsp/irq.h +++ b/bsps/arm/imx/include/bsp/irq.h @@ -20,7 +20,7 @@ #include #include -#include +#include #ifdef __cplusplus extern "C" { diff --git a/bsps/arm/imx/include/tm27.h b/bsps/arm/imx/include/tm27.h index c17c0107b4..982ea594be 100644 --- a/bsps/arm/imx/include/tm27.h +++ b/bsps/arm/imx/include/tm27.h @@ -19,6 +19,6 @@ #ifndef __tm27_h #define __tm27_h -#include +#include #endif /* __tm27_h */ diff --git a/bsps/arm/include/bsp/arm-a9mpcore-start.h b/bsps/arm/include/bsp/arm-a9mpcore-start.h index 8423e64e9d..a03bc8fb33 100644 --- a/bsps/arm/include/bsp/arm-a9mpcore-start.h +++ b/bsps/arm/include/bsp/arm-a9mpcore-start.h @@ -31,7 +31,7 @@ #include #include #include -#include +#include #ifdef __cplusplus extern "C" { diff --git a/bsps/arm/include/bsp/arm-gic-irq.h b/bsps/arm/include/bsp/arm-gic-irq.h deleted file mode 100644 index 219c3c7189..0000000000 --- a/bsps/arm/include/bsp/arm-gic-irq.h +++ /dev/null @@ -1,124 +0,0 @@ -/** - * @file - * - * @ingroup arm_gic - * - * @brief ARM GIC IRQ - */ - -/* - * Copyright (c) 2013, 2019 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H -#define LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H - -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define ARM_GIC_IRQ_SGI_0 0 -#define ARM_GIC_IRQ_SGI_1 1 -#define ARM_GIC_IRQ_SGI_2 2 -#define ARM_GIC_IRQ_SGI_3 3 -#define ARM_GIC_IRQ_SGI_5 5 -#define ARM_GIC_IRQ_SGI_6 6 -#define ARM_GIC_IRQ_SGI_7 7 -#define ARM_GIC_IRQ_SGI_8 8 -#define ARM_GIC_IRQ_SGI_9 9 -#define ARM_GIC_IRQ_SGI_10 10 -#define ARM_GIC_IRQ_SGI_11 11 -#define ARM_GIC_IRQ_SGI_12 12 -#define ARM_GIC_IRQ_SGI_13 13 -#define ARM_GIC_IRQ_SGI_14 14 -#define ARM_GIC_IRQ_SGI_15 15 - -#define ARM_GIC_DIST ((volatile gic_dist *) BSP_ARM_GIC_DIST_BASE) - -rtems_status_code arm_gic_irq_set_priority( - rtems_vector_number vector, - uint8_t priority -); - -rtems_status_code arm_gic_irq_get_priority( - rtems_vector_number vector, - uint8_t *priority -); - -rtems_status_code arm_gic_irq_set_group( - rtems_vector_number vector, - gic_group group -); - -rtems_status_code arm_gic_irq_get_group( - rtems_vector_number vector, - gic_group *group -); - -void bsp_interrupt_set_affinity( - rtems_vector_number vector, - const Processor_mask *affinity -); - -void bsp_interrupt_get_affinity( - rtems_vector_number vector, - Processor_mask *affinity -); - -typedef enum { - ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST, - ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_EXCEPT_SELF, - ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF -} arm_gic_irq_software_irq_target_filter; - -void arm_gic_trigger_sgi( - rtems_vector_number vector, - arm_gic_irq_software_irq_target_filter filter, - uint8_t targets -); - -static inline rtems_status_code arm_gic_irq_generate_software_irq( - rtems_vector_number vector, - arm_gic_irq_software_irq_target_filter filter, - uint8_t targets -) -{ - rtems_status_code sc = RTEMS_SUCCESSFUL; - - if (vector <= ARM_GIC_IRQ_SGI_15) { - arm_gic_trigger_sgi(vector, filter, targets); - } else { - sc = RTEMS_INVALID_ID; - } - - return sc; -} - -static inline uint32_t arm_gic_irq_processor_count(void) -{ - volatile gic_dist *dist = ARM_GIC_DIST; - - return GIC_DIST_ICDICTR_CPU_NUMBER_GET(dist->icdictr) + 1; -} - -void arm_gic_irq_initialize_secondary_cpu(void); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H */ diff --git a/bsps/arm/include/bsp/arm-gic-regs.h b/bsps/arm/include/bsp/arm-gic-regs.h deleted file mode 100644 index 8a65294b6f..0000000000 --- a/bsps/arm/include/bsp/arm-gic-regs.h +++ /dev/null @@ -1,217 +0,0 @@ -/** - * @file - * - * @ingroup arm_gic - * - * @brief ARM GIC Register definitions - */ - -/* - * Copyright (c) 2013, 2019 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_SHARED_ARM_GIC_REGS_H -#define LIBBSP_ARM_SHARED_ARM_GIC_REGS_H - -#include - -typedef struct { - uint32_t iccicr; -#define GIC_CPUIF_ICCICR_CBPR BSP_BIT32(4) -#define GIC_CPUIF_ICCICR_FIQ_EN BSP_BIT32(3) -#define GIC_CPUIF_ICCICR_ACK_CTL BSP_BIT32(2) -#define GIC_CPUIF_ICCICR_ENABLE_GRP_1 BSP_BIT32(1) -#define GIC_CPUIF_ICCICR_ENABLE BSP_BIT32(0) - uint32_t iccpmr; -#define GIC_CPUIF_ICCPMR_PRIORITY(val) BSP_FLD32(val, 0, 7) -#define GIC_CPUIF_ICCPMR_PRIORITY_GET(reg) BSP_FLD32GET(reg, 0, 7) -#define GIC_CPUIF_ICCPMR_PRIORITY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) - uint32_t iccbpr; -#define GIC_CPUIF_ICCBPR_BINARY_POINT(val) BSP_FLD32(val, 0, 2) -#define GIC_CPUIF_ICCBPR_BINARY_POINT_GET(reg) BSP_FLD32GET(reg, 0, 2) -#define GIC_CPUIF_ICCBPR_BINARY_POINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) - uint32_t icciar; -#define GIC_CPUIF_ICCIAR_CPUID(val) BSP_FLD32(val, 10, 12) -#define GIC_CPUIF_ICCIAR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12) -#define GIC_CPUIF_ICCIAR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12) -#define GIC_CPUIF_ICCIAR_ACKINTID(val) BSP_FLD32(val, 0, 9) -#define GIC_CPUIF_ICCIAR_ACKINTID_GET(reg) BSP_FLD32GET(reg, 0, 9) -#define GIC_CPUIF_ICCIAR_ACKINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9) - uint32_t icceoir; -#define GIC_CPUIF_ICCEOIR_CPUID(val) BSP_FLD32(val, 10, 12) -#define GIC_CPUIF_ICCEOIR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12) -#define GIC_CPUIF_ICCEOIR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12) -#define GIC_CPUIF_ICCEOIR_EOIINTID(val) BSP_FLD32(val, 0, 9) -#define GIC_CPUIF_ICCEOIR_EOIINTID_GET(reg) BSP_FLD32GET(reg, 0, 9) -#define GIC_CPUIF_ICCEOIR_EOIINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9) - uint32_t iccrpr; -#define GIC_CPUIF_ICCRPR_PRIORITY(val) BSP_FLD32(val, 0, 7) -#define GIC_CPUIF_ICCRPR_PRIORITY_GET(reg) BSP_FLD32GET(reg, 0, 7) -#define GIC_CPUIF_ICCRPR_PRIORITY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) - uint32_t icchpir; -#define GIC_CPUIF_ICCHPIR_CPUID(val) BSP_FLD32(val, 10, 12) -#define GIC_CPUIF_ICCHPIR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12) -#define GIC_CPUIF_ICCHPIR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12) -#define GIC_CPUIF_ICCHPIR_PENDINTID(val) BSP_FLD32(val, 0, 9) -#define GIC_CPUIF_ICCHPIR_PENDINTID_GET(reg) BSP_FLD32GET(reg, 0, 9) -#define GIC_CPUIF_ICCHPIR_PENDINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9) - uint32_t iccabpr; -#define GIC_CPUIF_ICCABPR_BINARY_POINT(val) BSP_FLD32(val, 0, 2) -#define GIC_CPUIF_ICCABPR_BINARY_POINT_GET(reg) BSP_FLD32GET(reg, 0, 2) -#define GIC_CPUIF_ICCABPR_BINARY_POINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) - uint32_t reserved_20[55]; - uint32_t icciidr; -#define GIC_CPUIF_ICCIIDR_PRODUCT_ID(val) BSP_FLD32(val, 24, 31) -#define GIC_CPUIF_ICCIIDR_PRODUCT_ID_GET(reg) BSP_FLD32GET(reg, 24, 31) -#define GIC_CPUIF_ICCIIDR_PRODUCT_ID_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31) -#define GIC_CPUIF_ICCIIDR_ARCH_VERSION(val) BSP_FLD32(val, 16, 19) -#define GIC_CPUIF_ICCIIDR_ARCH_VERSION_GET(reg) BSP_FLD32GET(reg, 16, 19) -#define GIC_CPUIF_ICCIIDR_ARCH_VERSION_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19) -#define GIC_CPUIF_ICCIIDR_REVISION(val) BSP_FLD32(val, 12, 15) -#define GIC_CPUIF_ICCIIDR_REVISION_GET(reg) BSP_FLD32GET(reg, 12, 15) -#define GIC_CPUIF_ICCIIDR_REVISION_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) -#define GIC_CPUIF_ICCIIDR_IMPLEMENTER(val) BSP_FLD32(val, 0, 11) -#define GIC_CPUIF_ICCIIDR_IMPLEMENTER_GET(reg) BSP_FLD32GET(reg, 0, 11) -#define GIC_CPUIF_ICCIIDR_IMPLEMENTER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11) -} gic_cpuif; - -typedef struct { - /* GICD_CTLR */ - uint32_t icddcr; -/* GICv3 only */ -#define GIC_DIST_ICDDCR_RWP BSP_BIT32(31) -#define GIC_DIST_ICDDCR_E1NWF BSP_BIT32(7) -#define GIC_DIST_ICDDCR_DS BSP_BIT32(6) -#define GIC_DIST_ICDDCR_ARE_NS BSP_BIT32(5) -#define GIC_DIST_ICDDCR_ARE_S BSP_BIT32(4) -#define GIC_DIST_ICDDCR_ENABLE_GRP1S BSP_BIT32(2) -#define GIC_DIST_ICDDCR_ENABLE_GRP1NS BSP_BIT32(1) -#define GIC_DIST_ICDDCR_ENABLE_GRP0 BSP_BIT32(0) -/* GICv1/GICv2 */ -#define GIC_DIST_ICDDCR_ENABLE_GRP_1 BSP_BIT32(1) -#define GIC_DIST_ICDDCR_ENABLE BSP_BIT32(0) - uint32_t icdictr; -#define GIC_DIST_ICDICTR_LSPI(val) BSP_FLD32(val, 11, 15) -#define GIC_DIST_ICDICTR_LSPI_GET(reg) BSP_FLD32GET(reg, 11, 15) -#define GIC_DIST_ICDICTR_LSPI_SET(reg, val) BSP_FLD32SET(reg, val, 11, 15) -#define GIC_DIST_ICDICTR_SECURITY_EXTN BSP_BIT32(10) -#define GIC_DIST_ICDICTR_CPU_NUMBER(val) BSP_FLD32(val, 5, 7) -#define GIC_DIST_ICDICTR_CPU_NUMBER_GET(reg) BSP_FLD32GET(reg, 5, 7) -#define GIC_DIST_ICDICTR_CPU_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 5, 7) -#define GIC_DIST_ICDICTR_IT_LINES_NUMBER(val) BSP_FLD32(val, 0, 4) -#define GIC_DIST_ICDICTR_IT_LINES_NUMBER_GET(reg) BSP_FLD32GET(reg, 0, 4) -#define GIC_DIST_ICDICTR_IT_LINES_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) - uint32_t icdiidr; -#define GIC_DIST_ICDIIDR_PRODUCT_ID(val) BSP_FLD32(val, 24, 31) -#define GIC_DIST_ICDIIDR_PRODUCT_ID_GET(reg) BSP_FLD32GET(reg, 24, 31) -#define GIC_DIST_ICDIIDR_PRODUCT_ID_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31) -#define GIC_DIST_ICDIIDR_VARIANT(val) BSP_FLD32(val, 16, 19) -#define GIC_DIST_ICDIIDR_VARIANT_GET(reg) BSP_FLD32GET(reg, 16, 19) -#define GIC_DIST_ICDIIDR_VARIANT_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19) -#define GIC_DIST_ICDIIDR_REVISION(val) BSP_FLD32(val, 12, 15) -#define GIC_DIST_ICDIIDR_REVISION_GET(reg) BSP_FLD32GET(reg, 12, 15) -#define GIC_DIST_ICDIIDR_REVISION_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) -#define GIC_DIST_ICDIIDR_IMPLEMENTER(val) BSP_FLD32(val, 0, 11) -#define GIC_DIST_ICDIIDR_IMPLEMENTER_GET(reg) BSP_FLD32GET(reg, 0, 11) -#define GIC_DIST_ICDIIDR_IMPLEMENTER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11) - uint32_t reserved_0c[29]; - uint32_t icdigr[32]; - uint32_t icdiser[32]; - uint32_t icdicer[32]; - uint32_t icdispr[32]; - uint32_t icdicpr[32]; - uint32_t icdabr[32]; - uint32_t reserved_380[32]; - uint8_t icdipr[256]; - uint32_t reserved_500[192]; - uint8_t icdiptr[256]; - uint32_t reserved_900[192]; - uint32_t icdicfr[64]; - /* GICD_IGRPMODR GICv3 only, reserved in GICv1/GICv2 */ - uint32_t icdigmr[32]; - uint32_t reserved_d80[96]; - uint32_t icdsgir; -#define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(val) BSP_FLD32(val, 24, 25) -#define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER_GET(reg) BSP_FLD32GET(reg, 24, 25) -#define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER_SET(reg, val) BSP_FLD32SET(reg, val, 24, 25) -#define GIC_DIST_ICDSGIR_CPU_TARGET_LIST(val) BSP_FLD32(val, 16, 23) -#define GIC_DIST_ICDSGIR_CPU_TARGET_LIST_GET(reg) BSP_FLD32GET(reg, 16, 23) -#define GIC_DIST_ICDSGIR_CPU_TARGET_LIST_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23) -#define GIC_DIST_ICDSGIR_NSATT BSP_BIT32(15) -#define GIC_DIST_ICDSGIR_SGIINTID(val) BSP_FLD32(val, 0, 3) -#define GIC_DIST_ICDSGIR_SGIINTID_GET(reg) BSP_FLD32GET(reg, 0, 3) -#define GIC_DIST_ICDSGIR_SGIINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) -} gic_dist; - -/* GICv3 only */ -typedef struct { - /* GICR_CTLR */ - uint32_t icrrcr; -#define GIC_REDIST_ICRRCR_UWP BSP_BIT32(31) -#define GIC_REDIST_ICRRCR_DPG1S BSP_BIT32(26) -#define GIC_REDIST_ICRRCR_DPG1NS BSP_BIT32(25) -#define GIC_REDIST_ICRRCR_DPG0 BSP_BIT32(24) -#define GIC_REDIST_ICRRCR_RWP BSP_BIT32(4) -#define GIC_REDIST_ICRRCR_ENABLE_LPI BSP_BIT32(0) - uint32_t icriidr; - uint64_t icrtyper; -#define GIC_REDIST_ICRTYPER_AFFINITY_VALUE(val) BSP_FLD64(val, 32, 63) -#define GIC_REDIST_ICRTYPER_AFFINITY_VALUE_GET(reg) BSP_FLD64GET(reg, 32, 63) -#define GIC_REDIST_ICRTYPER_AFFINITY_VALUE_SET(reg, val) BSP_FLD64SET(reg, val, 32, 63) -#define GIC_REDIST_ICRTYPER_COMMON_LPI_AFFINITY(val) BSP_FLD64(val, 24, 25) -#define GIC_REDIST_ICRTYPER_COMMON_LPI_AFFINITY_GET(reg) BSP_FLD64GET(reg, 24, 25) -#define GIC_REDIST_ICRTYPER_COMMON_LPI_AFFINITY_SET(reg, val) BSP_FLD64SET(reg, val, 24, 25) -#define GIC_REDIST_ICRTYPER_CPU_NUMBER(val) BSP_FLD64(val, 8, 23) -#define GIC_REDIST_ICRTYPER_CPU_NUMBER_GET(reg) BSP_FLD64GET(reg, 8, 23) -#define GIC_REDIST_ICRTYPER_CPU_NUMBER_SET(reg, val) BSP_FLD64SET(reg, val, 8, 23) -#define GIC_REDIST_ICRTYPER_DPGS BSP_BIT64(5) -#define GIC_REDIST_ICRTYPER_LAST BSP_BIT64(4) -#define GIC_REDIST_ICRTYPER_DIRECT_LPI BSP_BIT64(3) -#define GIC_REDIST_ICRTYPER_VLPIS BSP_BIT64(1) -#define GIC_REDIST_ICRTYPER_PLPIS BSP_BIT64(0) - uint32_t unused_10; - uint32_t icrwaker; -#define GIC_REDIST_ICRWAKER_CHILDREN_ASLEEP BSP_BIT32(2) -#define GIC_REDIST_ICRWAKER_PROCESSOR_SLEEP BSP_BIT32(1) -} gic_redist; - -/* GICv3 only */ -typedef struct { - uint32_t reserved_0_80[32]; - /* GICR_IGROUPR0 */ - uint32_t icspigrpr[32]; - /* GICR_ISENABLER0 */ - uint32_t icspiser[32]; - /* GICR_ICENABLER0 */ - uint32_t icspicer[32]; - /* GICR_ISPENDR0 */ - uint32_t icspispendr[32]; - /* GICR_ICPENDR0 */ - uint32_t icspicpendr[32]; - /* GICR_ISACTIVER0 */ - uint32_t icspisar[32]; - /* GICR_ICACTIVER0 */ - uint32_t icspicar[32]; - /* GICR_IPRIORITYR */ - uint8_t icspiprior[32]; - uint32_t reserved_420_bfc[504]; - /* GICR_ICFGR0 */ - uint32_t icspicfgr0; - /* GICR_ICFGR1 */ - uint32_t icspicfgr1; - uint32_t reserved_c08_cfc[62]; - /* GICR_IGRPMODR0 */ - uint32_t icspigrpmodr[64]; -} gic_sgi_ppi; - -#endif /* LIBBSP_ARM_SHARED_ARM_GIC_REGS_H */ diff --git a/bsps/arm/include/bsp/arm-gic-tm27.h b/bsps/arm/include/bsp/arm-gic-tm27.h deleted file mode 100644 index 95f3077716..0000000000 --- a/bsps/arm/include/bsp/arm-gic-tm27.h +++ /dev/null @@ -1,103 +0,0 @@ -/** - * @file - * - * @ingroup arm_gic - * - * @brief ARM GIC TM27 Support - */ - -/* - * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef LIBBSP_ARM_SHARED_ARM_GIC_TM27_H -#define LIBBSP_ARM_SHARED_ARM_GIC_TM27_H - -#include - -#include -#include - -#define MUST_WAIT_FOR_INTERRUPT 1 - -#define ARM_GIC_TM27_IRQ_LOW ARM_GIC_IRQ_SGI_12 - -#define ARM_GIC_TM27_IRQ_HIGH ARM_GIC_IRQ_SGI_13 - -#define ARM_GIC_TM27_PRIO_LOW 0x80 - -#define ARM_GIC_TM27_PRIO_HIGH 0x00 - -static inline void Install_tm27_vector(void (*handler)(rtems_vector_number)) -{ - rtems_status_code sc = rtems_interrupt_handler_install( - ARM_GIC_TM27_IRQ_LOW, - "tm27 low", - RTEMS_INTERRUPT_UNIQUE, - (rtems_interrupt_handler) handler, - NULL - ); - assert(sc == RTEMS_SUCCESSFUL); - - sc = arm_gic_irq_set_priority( - ARM_GIC_TM27_IRQ_LOW, - ARM_GIC_TM27_PRIO_LOW - ); - assert(sc == RTEMS_SUCCESSFUL); - - sc = rtems_interrupt_handler_install( - ARM_GIC_TM27_IRQ_HIGH, - "tm27 high", - RTEMS_INTERRUPT_UNIQUE, - (rtems_interrupt_handler) handler, - NULL - ); - assert(sc == RTEMS_SUCCESSFUL); - - sc = arm_gic_irq_set_priority( - ARM_GIC_TM27_IRQ_HIGH, - ARM_GIC_TM27_PRIO_HIGH - ); - assert(sc == RTEMS_SUCCESSFUL); -} - -static inline void Cause_tm27_intr(void) -{ - rtems_status_code sc = arm_gic_irq_generate_software_irq( - ARM_GIC_TM27_IRQ_LOW, - ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF, - 0 - ); - assert(sc == RTEMS_SUCCESSFUL); -} - -static inline void Clear_tm27_intr(void) -{ - /* Nothing to do */ -} - -static inline void Lower_tm27_intr(void) -{ - rtems_status_code sc = arm_gic_irq_generate_software_irq( - ARM_GIC_TM27_IRQ_HIGH, - ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF, - 0 - ); - assert(sc == RTEMS_SUCCESSFUL); -} - -#endif /* LIBBSP_ARM_SHARED_ARM_GIC_TM27_H */ diff --git a/bsps/arm/include/bsp/arm-gic.h b/bsps/arm/include/bsp/arm-gic.h deleted file mode 100644 index 42d53284c0..0000000000 --- a/bsps/arm/include/bsp/arm-gic.h +++ /dev/null @@ -1,242 +0,0 @@ -/** - * @file - * - * @ingroup arm_gic - * - * @brief ARM GIC Support - */ - -/* - * Copyright (c) 2013, 2019 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_SHARED_ARM_GIC_H -#define LIBBSP_ARM_SHARED_ARM_GIC_H - -#include - -#include - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @defgroup arm_gic ARM GIC - * - * @ingroup RTEMSBSPsARMShared - * - * @brief ARM_GIC Support Package - */ - -#define GIC_ID_TO_ONE_BIT_REG_INDEX(id) ((id) >> 5) -#define GIC_ID_TO_ONE_BIT_REG_BIT(id) (1U << ((id) & 0x1fU)) - -#define GIC_ID_TO_TWO_BITS_REG_INDEX(id) ((id) >> 4) -#define GIC_ID_TO_TWO_BITS_REG_OFFSET(id) (((id) & 0xfU) << 1) - -static inline bool gic_id_is_enabled(volatile gic_dist *dist, uint32_t id) -{ - uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); - uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); - - return (dist->icdiser[i] & bit) != 0; -} - -static inline void gic_id_enable(volatile gic_dist *dist, uint32_t id) -{ - uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); - uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); - - dist->icdiser[i] = bit; -} - -static inline void gic_id_disable(volatile gic_dist *dist, uint32_t id) -{ - uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); - uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); - - dist->icdicer[i] = bit; -} - -static inline bool gic_id_is_pending(volatile gic_dist *dist, uint32_t id) -{ - uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); - uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); - - return (dist->icdispr[i] & bit) != 0; -} - -static inline void gic_id_set_pending(volatile gic_dist *dist, uint32_t id) -{ - uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); - uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); - - dist->icdispr[i] = bit; -} - -static inline void gic_id_clear_pending(volatile gic_dist *dist, uint32_t id) -{ - uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); - uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); - - dist->icdicpr[i] = bit; -} - -static inline bool gic_id_is_active(volatile gic_dist *dist, uint32_t id) -{ - uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); - uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); - - return (dist->icdabr[i] & bit) != 0; -} - -typedef enum { - GIC_GROUP_0, - GIC_GROUP_1 -} gic_group; - -static inline gic_group gic_id_get_group( - volatile gic_dist *dist, - uint32_t id -) -{ - uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); - uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); - - return (dist->icdigr[i] & bit) != 0 ? GIC_GROUP_1 : GIC_GROUP_0; -} - -static inline void gic_id_set_group( - volatile gic_dist *dist, - uint32_t id, - gic_group group -) -{ - uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); - uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); - uint32_t icdigr = dist->icdigr[i]; - - icdigr &= ~bit; - - if (group == GIC_GROUP_1) { - icdigr |= bit; - } - - dist->icdigr[i] = icdigr; -} - -static inline void gic_id_set_priority( - volatile gic_dist *dist, - uint32_t id, - uint8_t priority -) -{ - dist->icdipr[id] = priority; -} - -static inline uint8_t gic_id_get_priority(volatile gic_dist *dist, uint32_t id) -{ - return dist->icdipr[id]; -} - -static inline void gic_id_set_targets( - volatile gic_dist *dist, - uint32_t id, - uint8_t targets -) -{ - dist->icdiptr[id] = targets; -} - -static inline uint8_t gic_id_get_targets(volatile gic_dist *dist, uint32_t id) -{ - return dist->icdiptr[id]; -} - -typedef enum { - GIC_LEVEL_SENSITIVE, - GIC_EDGE_TRIGGERED -} gic_trigger_mode; - -static inline gic_trigger_mode gic_id_get_trigger_mode( - volatile gic_dist *dist, - uint32_t id -) -{ - uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(id); - uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(id) + 1; - uint32_t bit = 1U << o; - - return (dist->icdicfr[i] & bit) != 0 ? - GIC_EDGE_TRIGGERED : GIC_LEVEL_SENSITIVE; -} - -static inline void gic_id_set_trigger_mode( - volatile gic_dist *dist, - uint32_t id, - gic_trigger_mode mode -) -{ - uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(id); - uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(id) + 1; - uint32_t bit = mode << o; - uint32_t mask = 1U << o; - uint32_t icdicfr = dist->icdicfr[i]; - - icdicfr &= ~mask; - icdicfr |= bit; - - dist->icdicfr[i] = icdicfr; -} - -typedef enum { - GIC_N_TO_N, - GIC_1_TO_N -} gic_handling_model; - -static inline gic_handling_model gic_id_get_handling_model( - volatile gic_dist *dist, - uint32_t id -) -{ - uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(id); - uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(id); - uint32_t bit = 1U << o; - - return (dist->icdicfr[i] & bit) != 0 ? GIC_1_TO_N : GIC_N_TO_N; -} - -static inline void gic_id_set_handling_model( - volatile gic_dist *dist, - uint32_t id, - gic_handling_model model -) -{ - uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(id); - uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(id); - uint32_t bit = model << o; - uint32_t mask = 1U << o; - uint32_t icdicfr = dist->icdicfr[i]; - - icdicfr &= ~mask; - icdicfr |= bit; - - dist->icdicfr[i] = icdicfr; -} - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_SHARED_ARM_GIC_H */ diff --git a/bsps/arm/realview-pbx-a9/include/bsp/irq.h b/bsps/arm/realview-pbx-a9/include/bsp/irq.h index e66bf41df4..270ecd33ae 100644 --- a/bsps/arm/realview-pbx-a9/include/bsp/irq.h +++ b/bsps/arm/realview-pbx-a9/include/bsp/irq.h @@ -29,7 +29,7 @@ #include #include -#include +#include /** * @defgroup realview-pbx-a9_interrupt Interrrupt Support diff --git a/bsps/arm/realview-pbx-a9/include/tm27.h b/bsps/arm/realview-pbx-a9/include/tm27.h index ae148aacdd..ecc0dc4c32 100644 --- a/bsps/arm/realview-pbx-a9/include/tm27.h +++ b/bsps/arm/realview-pbx-a9/include/tm27.h @@ -36,6 +36,6 @@ #ifndef __tm27_h #define __tm27_h -#include +#include #endif /* __tm27_h */ diff --git a/bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c b/bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c new file mode 100644 index 0000000000..b805199ba9 --- /dev/null +++ b/bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMShared + * + * @brief ARM-specific IRQ handlers. + */ + +/* + * Copyright (C) 2020 On-Line Applications Research Corporation (OAR) + * Written by Kinsey Moore + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +void arm_interrupt_handler_dispatch(rtems_vector_number vector) +{ + uint32_t psr = _ARMV4_Status_irq_enable(); + bsp_interrupt_handler_dispatch(vector); + + _ARMV4_Status_restore(psr); +} + +void arm_interrupt_facility_set_exception_handler(void) +{ + arm_cp15_set_exception_handler( + ARM_EXCEPTION_IRQ, + _ARMV4_Exception_interrupt + ); +} + +void bsp_interrupt_dispatch(void) +{ + gicv3_interrupt_dispatch(); +} diff --git a/bsps/arm/shared/irq/irq-gic.c b/bsps/arm/shared/irq/irq-gic.c index 42ae6c4d7d..1a401b67b6 100644 --- a/bsps/arm/shared/irq/irq-gic.c +++ b/bsps/arm/shared/irq/irq-gic.c @@ -12,7 +12,7 @@ * http://www.rtems.org/license/LICENSE. */ -#include +#include #include diff --git a/bsps/arm/shared/irq/irq-gicv3.c b/bsps/arm/shared/irq/irq-gicv3.c deleted file mode 100644 index 138b565b9b..0000000000 --- a/bsps/arm/shared/irq/irq-gicv3.c +++ /dev/null @@ -1,329 +0,0 @@ -/* - * SPDX-License-Identifier: BSD-2-Clause - * - * Copyright (C) 2019 On-Line Applications Research Corporation (OAR) - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include - -#include - -#include -#include -#include - -#define PRIORITY_DEFAULT 127 - -/* cpuif->iccicr */ -#define ICC_CTLR "p15, 0, %0, c12, c12, 4" - -/* cpuif->iccpmr */ -#define ICC_PMR "p15, 0, %0, c4, c6, 0" - -/* cpuif->iccbpr */ -#define ICC_BPR0 "p15, 0, %0, c12, c8, 3" -#define ICC_BPR1 "p15, 0, %0, c12, c12, 3" - -/* cpuif->icciar */ -#define ICC_IAR0 "p15, 0, %0, c12, c8, 0" -#define ICC_IAR1 "p15, 0, %0, c12, c12, 0" - -/* cpuif->icceoir */ -#define ICC_EOIR0 "p15, 0, %0, c12, c8, 1" -#define ICC_EOIR1 "p15, 0, %0, c12, c12, 1" - -#define ICC_SRE "p15, 0, %0, c12, c12, 5" - -#define ICC_IGRPEN0 "p15, 0, %0, c12, c12, 6" -#define ICC_IGRPEN1 "p15, 0, %0, c12, c12, 7" - -#define ICC_SGI1 "p15, 0, %Q0, %R0, c12" - -#define ICC_SGIR_AFFINITY3(val) BSP_FLD64(val, 48, 55) -#define ICC_SGIR_AFFINITY3_GET(reg) BSP_FLD64GET(reg, 48, 55) -#define ICC_SGIR_AFFINITY3_SET(reg, val) BSP_FLD64SET(reg, val, 48, 55) -#define ICC_SGIR_IRM BSP_BIT32(40) -#define ICC_SGIR_AFFINITY2(val) BSP_FLD64(val, 32, 39) -#define ICC_SGIR_AFFINITY2_GET(reg) BSP_FLD64GET(reg, 32, 39) -#define ICC_SGIR_AFFINITY2_SET(reg, val) BSP_FLD64SET(reg, val, 32, 39) -#define ICC_SGIR_INTID(val) BSP_FLD64(val, 24, 27) -#define ICC_SGIR_INTID_GET(reg) BSP_FLD64GET(reg, 24, 27) -#define ICC_SGIR_INTID_SET(reg, val) BSP_FLD64SET(reg, val, 24, 27) -#define ICC_SGIR_AFFINITY1(val) BSP_FLD64(val, 16, 23) -#define ICC_SGIR_AFFINITY1_GET(reg) BSP_FLD64GET(reg, 16, 23) -#define ICC_SGIR_AFFINITY1_SET(reg, val) BSP_FLD64SET(reg, val, 16, 23) -#define ICC_SGIR_CPU_TARGET_LIST(val) BSP_FLD64(val, 0, 15) -#define ICC_SGIR_CPU_TARGET_LIST_GET(reg) BSP_FLD64GET(reg, 0, 15) -#define ICC_SGIR_CPU_TARGET_LIST_SET(reg, val) BSP_FLD64SET(reg, val, 0, 15) - -#define MPIDR "p15, 0, %0, c0, c0, 5" - -#define MPIDR_AFFINITY3(val) BSP_FLD64(val, 25, 29) -#define MPIDR_AFFINITY3_GET(reg) BSP_FLD64GET(reg, 25, 29) -#define MPIDR_AFFINITY3_SET(reg, val) BSP_FLD64SET(reg, val, 25, 29) -#define MPIDR_AFFINITY2(val) BSP_FLD64(val, 16, 23) -#define MPIDR_AFFINITY2_GET(reg) BSP_FLD64GET(reg, 16, 23) -#define MPIDR_AFFINITY2_SET(reg, val) BSP_FLD64SET(reg, val, 16, 23) -#define MPIDR_AFFINITY1(val) BSP_FLD64(val, 8, 15) -#define MPIDR_AFFINITY1_GET(reg) BSP_FLD64GET(reg, 8, 15) -#define MPIDR_AFFINITY1_SET(reg, val) BSP_FLD64SET(reg, val, 8, 15) -#define MPIDR_AFFINITY0(val) BSP_FLD64(val, 0, 7) -#define MPIDR_AFFINITY0_GET(reg) BSP_FLD64GET(reg, 0, 7) -#define MPIDR_AFFINITY0_SET(reg, val) BSP_FLD64SET(reg, val, 0, 7) - -#define READ_SR(SR_NAME) \ -({ \ - uint32_t value; \ - __asm__ volatile("mrc " SR_NAME : "=r" (value) ); \ - value; \ -}) - -#define WRITE_SR(SR_NAME, VALUE) \ - __asm__ volatile("mcr " SR_NAME " \n" : : "r" (VALUE) ); - -#define WRITE64_SR(SR_NAME, VALUE) \ - __asm__ volatile("mcrr " SR_NAME " \n" : : "r" (VALUE) ); - -#define ARM_GIC_REDIST ((volatile gic_redist *) BSP_ARM_GIC_REDIST_BASE) -#define ARM_GIC_SGI_PPI (((volatile gic_sgi_ppi *) ((char*)BSP_ARM_GIC_REDIST_BASE + (1 << 16)))) - -void bsp_interrupt_dispatch(void) -{ - uint32_t icciar = READ_SR(ICC_IAR1); - rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar); - rtems_vector_number spurious = 1023; - - if (vector != spurious) { - uint32_t psr = _ARMV4_Status_irq_enable(); - bsp_interrupt_handler_dispatch(vector); - - _ARMV4_Status_restore(psr); - - WRITE_SR(ICC_EOIR1, icciar); - } -} - -void bsp_interrupt_vector_enable(rtems_vector_number vector) -{ - volatile gic_dist *dist = ARM_GIC_DIST; - volatile gic_sgi_ppi *sgi_ppi = ARM_GIC_SGI_PPI; - - bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); - - /* TODO(kmoore) This could use some cleanup and integration - * Vectors below 32 are currently routed through the redistributor */ - if (vector >= 32) { - gic_id_enable(dist, vector); - } else { - sgi_ppi->icspiser[0] = 1 << (vector % 32); - } -} - -void bsp_interrupt_vector_disable(rtems_vector_number vector) -{ - volatile gic_dist *dist = ARM_GIC_DIST; - volatile gic_sgi_ppi *sgi_ppi = ARM_GIC_SGI_PPI; - - bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); - - if (vector >= 32) { - gic_id_disable(dist, vector); - } else { - sgi_ppi->icspicer[0] = 1 << (vector % 32); - } -} - -static inline uint32_t get_id_count(volatile gic_dist *dist) -{ - uint32_t id_count = GIC_DIST_ICDICTR_IT_LINES_NUMBER_GET(dist->icdictr); - - id_count = 32 * (id_count + 1); - id_count = id_count <= 1020 ? id_count : 1020; - - return id_count; -} - -static void init_cpu_interface(void) -{ - uint32_t sre_value = 0x7; - WRITE_SR(ICC_SRE, sre_value); - WRITE_SR(ICC_PMR, GIC_CPUIF_ICCPMR_PRIORITY(0xff)); - WRITE_SR(ICC_BPR0, GIC_CPUIF_ICCBPR_BINARY_POINT(0x0)); - - volatile gic_redist *redist = ARM_GIC_REDIST; - uint32_t waker = redist->icrwaker; - uint32_t waker_mask = GIC_REDIST_ICRWAKER_PROCESSOR_SLEEP; - waker &= ~waker_mask; - redist->icrwaker = waker; - - /* Set interrupt group to 1NS for SGI/PPI interrupts routed through the redistributor */ - volatile gic_sgi_ppi *sgi_ppi = ARM_GIC_SGI_PPI; - sgi_ppi->icspigrpr[0] = 0xffffffff; - sgi_ppi->icspigrpmodr[0] = 0; - for (int id = 0; id < 32; id++) { - sgi_ppi->icspiprior[id] = PRIORITY_DEFAULT; - } - - /* Enable interrupt groups 0 and 1 */ - WRITE_SR(ICC_IGRPEN0, 0x1); - WRITE_SR(ICC_IGRPEN1, 0x1); - WRITE_SR(ICC_CTLR, 0x0); -} - -rtems_status_code bsp_interrupt_facility_initialize(void) -{ - volatile gic_dist *dist = ARM_GIC_DIST; - uint32_t id_count = get_id_count(dist); - uint32_t id; - - arm_cp15_set_exception_handler( - ARM_EXCEPTION_IRQ, - _ARMV4_Exception_interrupt - ); - - dist->icddcr = GIC_DIST_ICDDCR_ARE_NS | GIC_DIST_ICDDCR_ARE_S - | GIC_DIST_ICDDCR_ENABLE_GRP1S | GIC_DIST_ICDDCR_ENABLE_GRP1NS - | GIC_DIST_ICDDCR_ENABLE_GRP0; - - for (id = 0; id < id_count; id += 32) { - /* Disable all interrupts */ - dist->icdicer[id / 32] = 0xffffffff; - - /* Set interrupt group to 1NS for all interrupts */ - dist->icdigr[id / 32] = 0xffffffff; - dist->icdigmr[id / 32] = 0; - } - - for (id = 0; id < id_count; ++id) { - gic_id_set_priority(dist, id, PRIORITY_DEFAULT); - } - - for (id = 32; id < id_count; ++id) { - gic_id_set_targets(dist, id, 0x01); - } - - init_cpu_interface(); - return RTEMS_SUCCESSFUL; -} - -#ifdef RTEMS_SMP -BSP_START_TEXT_SECTION void arm_gic_irq_initialize_secondary_cpu(void) -{ - volatile gic_dist *dist = ARM_GIC_DIST; - - while ((dist->icddcr & GIC_DIST_ICDDCR_ENABLE) == 0) { - /* Wait */ - } - -#error modify init_cpu_interface to use correct offsets for each CPU - init_cpu_interface(); -} -#endif - -rtems_status_code arm_gic_irq_set_priority( - rtems_vector_number vector, - uint8_t priority -) -{ - rtems_status_code sc = RTEMS_SUCCESSFUL; - - if (bsp_interrupt_is_valid_vector(vector)) { - if (vector < 32) { - volatile gic_sgi_ppi *sgi_ppi = ARM_GIC_SGI_PPI; - sgi_ppi->icspiprior[vector] = priority; - } else { - volatile gic_dist *dist = ARM_GIC_DIST; - gic_id_set_priority(dist, vector, priority); - } - } else { - sc = RTEMS_INVALID_ID; - } - - return sc; -} - -rtems_status_code arm_gic_irq_get_priority( - rtems_vector_number vector, - uint8_t *priority -) -{ - rtems_status_code sc = RTEMS_SUCCESSFUL; - - if (bsp_interrupt_is_valid_vector(vector)) { - if (vector < 32) { - volatile gic_sgi_ppi *sgi_ppi = ARM_GIC_SGI_PPI; - *priority = sgi_ppi->icspiprior[vector]; - } else { - volatile gic_dist *dist = ARM_GIC_DIST; - *priority = gic_id_get_priority(dist, vector); - } - } else { - sc = RTEMS_INVALID_ID; - } - - return sc; -} - -void bsp_interrupt_set_affinity( - rtems_vector_number vector, - const Processor_mask *affinity -) -{ - volatile gic_dist *dist = ARM_GIC_DIST; - uint8_t targets = (uint8_t) _Processor_mask_To_uint32_t(affinity, 0); - - gic_id_set_targets(dist, vector, targets); -} - -void bsp_interrupt_get_affinity( - rtems_vector_number vector, - Processor_mask *affinity -) -{ - volatile gic_dist *dist = ARM_GIC_DIST; - uint8_t targets = gic_id_get_targets(dist, vector); - - _Processor_mask_From_uint32_t(affinity, targets, 0); -} - -void arm_gic_trigger_sgi( - rtems_vector_number vector, - arm_gic_irq_software_irq_target_filter filter, - uint8_t targets -) -{ - /* TODO(kmoore) Handle filter: - * ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST, - * ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_EXCEPT_SELF, - * ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF */ - uint32_t mpidr = READ_SR(MPIDR); - uint64_t value = ICC_SGIR_AFFINITY3(MPIDR_AFFINITY3_GET(mpidr)) - | ICC_SGIR_AFFINITY2(MPIDR_AFFINITY2_GET(mpidr)) - | ICC_SGIR_INTID(vector) - | ICC_SGIR_AFFINITY1(MPIDR_AFFINITY1_GET(mpidr)) - | ICC_SGIR_CPU_TARGET_LIST(1); - WRITE64_SR(ICC_SGI1, value); -} diff --git a/bsps/arm/xen/include/bsp/irq.h b/bsps/arm/xen/include/bsp/irq.h index dc09e52373..a147a1c079 100644 --- a/bsps/arm/xen/include/bsp/irq.h +++ b/bsps/arm/xen/include/bsp/irq.h @@ -34,7 +34,7 @@ #include #include -#include +#include #ifdef __cplusplus extern "C" { diff --git a/bsps/arm/xen/include/tm27.h b/bsps/arm/xen/include/tm27.h index 2fc4afa4f2..4c1dfaa213 100644 --- a/bsps/arm/xen/include/tm27.h +++ b/bsps/arm/xen/include/tm27.h @@ -33,6 +33,6 @@ #ifndef __tm27_h #define __tm27_h -#include +#include #endif /* __tm27_h */ diff --git a/bsps/arm/xilinx-zynq/include/bsp/irq.h b/bsps/arm/xilinx-zynq/include/bsp/irq.h index edea29b7df..e707337fa1 100644 --- a/bsps/arm/xilinx-zynq/include/bsp/irq.h +++ b/bsps/arm/xilinx-zynq/include/bsp/irq.h @@ -40,7 +40,7 @@ #include #include -#include +#include #ifdef __cplusplus extern "C" { diff --git a/bsps/arm/xilinx-zynq/include/tm27.h b/bsps/arm/xilinx-zynq/include/tm27.h index 885b97a30c..7fc8dd7edd 100644 --- a/bsps/arm/xilinx-zynq/include/tm27.h +++ b/bsps/arm/xilinx-zynq/include/tm27.h @@ -44,6 +44,6 @@ * @brief Interrupt Mechanisms for tm27 test */ -#include +#include #endif /* __tm27_h */ diff --git a/bsps/arm/xilinx-zynqmp/include/bsp/irq.h b/bsps/arm/xilinx-zynqmp/include/bsp/irq.h index 73567da011..6496d2312e 100644 --- a/bsps/arm/xilinx-zynqmp/include/bsp/irq.h +++ b/bsps/arm/xilinx-zynqmp/include/bsp/irq.h @@ -44,7 +44,7 @@ #include #include -#include +#include #ifdef __cplusplus extern "C" { diff --git a/bsps/arm/xilinx-zynqmp/include/tm27.h b/bsps/arm/xilinx-zynqmp/include/tm27.h index 0f02a3b195..14214fe151 100644 --- a/bsps/arm/xilinx-zynqmp/include/tm27.h +++ b/bsps/arm/xilinx-zynqmp/include/tm27.h @@ -49,6 +49,6 @@ * @brief Interrupt Mechanisms for tm27 test */ -#include +#include #endif /* __tm27_h */ diff --git a/bsps/headers.am b/bsps/headers.am index aaf13284bd..b433c2d8d4 100644 --- a/bsps/headers.am +++ b/bsps/headers.am @@ -21,6 +21,13 @@ include_bsp_HEADERS += ../../bsps/include/bsp/u-boot.h include_bsp_HEADERS += ../../bsps/include/bsp/uart-output-char.h include_bsp_HEADERS += ../../bsps/include/bsp/utility.h +include_dev_irqdir = $(includedir)/dev/irq +include_dev_irq_HEADERS = +include_dev_irq_HEADERS += ../../bsps/include/dev/irq/arm-gic-irq.h +include_dev_irq_HEADERS += ../../bsps/include/dev/irq/arm-gic-regs.h +include_dev_irq_HEADERS += ../../bsps/include/dev/irq/arm-gic-tm27.h +include_dev_irq_HEADERS += ../../bsps/include/dev/irq/arm-gic.h + include_dev_serialdir = $(includedir)/dev/serial include_dev_serial_HEADERS = include_dev_serial_HEADERS += ../../bsps/include/dev/serial/arm-pl011-regs.h diff --git a/bsps/include/dev/irq/arm-gic-irq.h b/bsps/include/dev/irq/arm-gic-irq.h new file mode 100644 index 0000000000..a97191faca --- /dev/null +++ b/bsps/include/dev/irq/arm-gic-irq.h @@ -0,0 +1,143 @@ +/** + * @file + * + * @ingroup arm_gic + * + * @brief ARM GIC IRQ + */ + +/* + * Copyright (c) 2013, 2019 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H +#define LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define ARM_GIC_IRQ_SGI_0 0 +#define ARM_GIC_IRQ_SGI_1 1 +#define ARM_GIC_IRQ_SGI_2 2 +#define ARM_GIC_IRQ_SGI_3 3 +#define ARM_GIC_IRQ_SGI_5 5 +#define ARM_GIC_IRQ_SGI_6 6 +#define ARM_GIC_IRQ_SGI_7 7 +#define ARM_GIC_IRQ_SGI_8 8 +#define ARM_GIC_IRQ_SGI_9 9 +#define ARM_GIC_IRQ_SGI_10 10 +#define ARM_GIC_IRQ_SGI_11 11 +#define ARM_GIC_IRQ_SGI_12 12 +#define ARM_GIC_IRQ_SGI_13 13 +#define ARM_GIC_IRQ_SGI_14 14 +#define ARM_GIC_IRQ_SGI_15 15 + +#define ARM_GIC_DIST ((volatile gic_dist *) BSP_ARM_GIC_DIST_BASE) + +rtems_status_code arm_gic_irq_set_priority( + rtems_vector_number vector, + uint8_t priority +); + +rtems_status_code arm_gic_irq_get_priority( + rtems_vector_number vector, + uint8_t *priority +); + +rtems_status_code arm_gic_irq_set_group( + rtems_vector_number vector, + gic_group group +); + +rtems_status_code arm_gic_irq_get_group( + rtems_vector_number vector, + gic_group *group +); + +void bsp_interrupt_set_affinity( + rtems_vector_number vector, + const Processor_mask *affinity +); + +void bsp_interrupt_get_affinity( + rtems_vector_number vector, + Processor_mask *affinity +); + +typedef enum { + ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST, + ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_EXCEPT_SELF, + ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF +} arm_gic_irq_software_irq_target_filter; + +void arm_gic_trigger_sgi( + rtems_vector_number vector, + arm_gic_irq_software_irq_target_filter filter, + uint8_t targets +); + +static inline rtems_status_code arm_gic_irq_generate_software_irq( + rtems_vector_number vector, + arm_gic_irq_software_irq_target_filter filter, + uint8_t targets +) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + + if (vector <= ARM_GIC_IRQ_SGI_15) { + arm_gic_trigger_sgi(vector, filter, targets); + } else { + sc = RTEMS_INVALID_ID; + } + + return sc; +} + +/** + * This architecture-specific function sets the exception vector for handling + * IRQs. + */ +void arm_interrupt_facility_set_exception_handler(void); + +/** + * This architecture-specific function dispatches a triggered IRQ. + * + * @param[in] vector The vector on which the IRQ occurred. + */ +void arm_interrupt_handler_dispatch(rtems_vector_number vector); + +/** + * This is the GICv3 interrupt dispatcher that is to be called from the + * architecture-specific implementation of the IRQ handler. + */ +void gicv3_interrupt_dispatch(void); + +static inline uint32_t arm_gic_irq_processor_count(void) +{ + volatile gic_dist *dist = ARM_GIC_DIST; + + return GIC_DIST_ICDICTR_CPU_NUMBER_GET(dist->icdictr) + 1; +} + +void arm_gic_irq_initialize_secondary_cpu(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H */ diff --git a/bsps/include/dev/irq/arm-gic-regs.h b/bsps/include/dev/irq/arm-gic-regs.h new file mode 100644 index 0000000000..8a65294b6f --- /dev/null +++ b/bsps/include/dev/irq/arm-gic-regs.h @@ -0,0 +1,217 @@ +/** + * @file + * + * @ingroup arm_gic + * + * @brief ARM GIC Register definitions + */ + +/* + * Copyright (c) 2013, 2019 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_GIC_REGS_H +#define LIBBSP_ARM_SHARED_ARM_GIC_REGS_H + +#include + +typedef struct { + uint32_t iccicr; +#define GIC_CPUIF_ICCICR_CBPR BSP_BIT32(4) +#define GIC_CPUIF_ICCICR_FIQ_EN BSP_BIT32(3) +#define GIC_CPUIF_ICCICR_ACK_CTL BSP_BIT32(2) +#define GIC_CPUIF_ICCICR_ENABLE_GRP_1 BSP_BIT32(1) +#define GIC_CPUIF_ICCICR_ENABLE BSP_BIT32(0) + uint32_t iccpmr; +#define GIC_CPUIF_ICCPMR_PRIORITY(val) BSP_FLD32(val, 0, 7) +#define GIC_CPUIF_ICCPMR_PRIORITY_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define GIC_CPUIF_ICCPMR_PRIORITY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t iccbpr; +#define GIC_CPUIF_ICCBPR_BINARY_POINT(val) BSP_FLD32(val, 0, 2) +#define GIC_CPUIF_ICCBPR_BINARY_POINT_GET(reg) BSP_FLD32GET(reg, 0, 2) +#define GIC_CPUIF_ICCBPR_BINARY_POINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) + uint32_t icciar; +#define GIC_CPUIF_ICCIAR_CPUID(val) BSP_FLD32(val, 10, 12) +#define GIC_CPUIF_ICCIAR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12) +#define GIC_CPUIF_ICCIAR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12) +#define GIC_CPUIF_ICCIAR_ACKINTID(val) BSP_FLD32(val, 0, 9) +#define GIC_CPUIF_ICCIAR_ACKINTID_GET(reg) BSP_FLD32GET(reg, 0, 9) +#define GIC_CPUIF_ICCIAR_ACKINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9) + uint32_t icceoir; +#define GIC_CPUIF_ICCEOIR_CPUID(val) BSP_FLD32(val, 10, 12) +#define GIC_CPUIF_ICCEOIR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12) +#define GIC_CPUIF_ICCEOIR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12) +#define GIC_CPUIF_ICCEOIR_EOIINTID(val) BSP_FLD32(val, 0, 9) +#define GIC_CPUIF_ICCEOIR_EOIINTID_GET(reg) BSP_FLD32GET(reg, 0, 9) +#define GIC_CPUIF_ICCEOIR_EOIINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9) + uint32_t iccrpr; +#define GIC_CPUIF_ICCRPR_PRIORITY(val) BSP_FLD32(val, 0, 7) +#define GIC_CPUIF_ICCRPR_PRIORITY_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define GIC_CPUIF_ICCRPR_PRIORITY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t icchpir; +#define GIC_CPUIF_ICCHPIR_CPUID(val) BSP_FLD32(val, 10, 12) +#define GIC_CPUIF_ICCHPIR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12) +#define GIC_CPUIF_ICCHPIR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12) +#define GIC_CPUIF_ICCHPIR_PENDINTID(val) BSP_FLD32(val, 0, 9) +#define GIC_CPUIF_ICCHPIR_PENDINTID_GET(reg) BSP_FLD32GET(reg, 0, 9) +#define GIC_CPUIF_ICCHPIR_PENDINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9) + uint32_t iccabpr; +#define GIC_CPUIF_ICCABPR_BINARY_POINT(val) BSP_FLD32(val, 0, 2) +#define GIC_CPUIF_ICCABPR_BINARY_POINT_GET(reg) BSP_FLD32GET(reg, 0, 2) +#define GIC_CPUIF_ICCABPR_BINARY_POINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) + uint32_t reserved_20[55]; + uint32_t icciidr; +#define GIC_CPUIF_ICCIIDR_PRODUCT_ID(val) BSP_FLD32(val, 24, 31) +#define GIC_CPUIF_ICCIIDR_PRODUCT_ID_GET(reg) BSP_FLD32GET(reg, 24, 31) +#define GIC_CPUIF_ICCIIDR_PRODUCT_ID_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31) +#define GIC_CPUIF_ICCIIDR_ARCH_VERSION(val) BSP_FLD32(val, 16, 19) +#define GIC_CPUIF_ICCIIDR_ARCH_VERSION_GET(reg) BSP_FLD32GET(reg, 16, 19) +#define GIC_CPUIF_ICCIIDR_ARCH_VERSION_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19) +#define GIC_CPUIF_ICCIIDR_REVISION(val) BSP_FLD32(val, 12, 15) +#define GIC_CPUIF_ICCIIDR_REVISION_GET(reg) BSP_FLD32GET(reg, 12, 15) +#define GIC_CPUIF_ICCIIDR_REVISION_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) +#define GIC_CPUIF_ICCIIDR_IMPLEMENTER(val) BSP_FLD32(val, 0, 11) +#define GIC_CPUIF_ICCIIDR_IMPLEMENTER_GET(reg) BSP_FLD32GET(reg, 0, 11) +#define GIC_CPUIF_ICCIIDR_IMPLEMENTER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11) +} gic_cpuif; + +typedef struct { + /* GICD_CTLR */ + uint32_t icddcr; +/* GICv3 only */ +#define GIC_DIST_ICDDCR_RWP BSP_BIT32(31) +#define GIC_DIST_ICDDCR_E1NWF BSP_BIT32(7) +#define GIC_DIST_ICDDCR_DS BSP_BIT32(6) +#define GIC_DIST_ICDDCR_ARE_NS BSP_BIT32(5) +#define GIC_DIST_ICDDCR_ARE_S BSP_BIT32(4) +#define GIC_DIST_ICDDCR_ENABLE_GRP1S BSP_BIT32(2) +#define GIC_DIST_ICDDCR_ENABLE_GRP1NS BSP_BIT32(1) +#define GIC_DIST_ICDDCR_ENABLE_GRP0 BSP_BIT32(0) +/* GICv1/GICv2 */ +#define GIC_DIST_ICDDCR_ENABLE_GRP_1 BSP_BIT32(1) +#define GIC_DIST_ICDDCR_ENABLE BSP_BIT32(0) + uint32_t icdictr; +#define GIC_DIST_ICDICTR_LSPI(val) BSP_FLD32(val, 11, 15) +#define GIC_DIST_ICDICTR_LSPI_GET(reg) BSP_FLD32GET(reg, 11, 15) +#define GIC_DIST_ICDICTR_LSPI_SET(reg, val) BSP_FLD32SET(reg, val, 11, 15) +#define GIC_DIST_ICDICTR_SECURITY_EXTN BSP_BIT32(10) +#define GIC_DIST_ICDICTR_CPU_NUMBER(val) BSP_FLD32(val, 5, 7) +#define GIC_DIST_ICDICTR_CPU_NUMBER_GET(reg) BSP_FLD32GET(reg, 5, 7) +#define GIC_DIST_ICDICTR_CPU_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 5, 7) +#define GIC_DIST_ICDICTR_IT_LINES_NUMBER(val) BSP_FLD32(val, 0, 4) +#define GIC_DIST_ICDICTR_IT_LINES_NUMBER_GET(reg) BSP_FLD32GET(reg, 0, 4) +#define GIC_DIST_ICDICTR_IT_LINES_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) + uint32_t icdiidr; +#define GIC_DIST_ICDIIDR_PRODUCT_ID(val) BSP_FLD32(val, 24, 31) +#define GIC_DIST_ICDIIDR_PRODUCT_ID_GET(reg) BSP_FLD32GET(reg, 24, 31) +#define GIC_DIST_ICDIIDR_PRODUCT_ID_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31) +#define GIC_DIST_ICDIIDR_VARIANT(val) BSP_FLD32(val, 16, 19) +#define GIC_DIST_ICDIIDR_VARIANT_GET(reg) BSP_FLD32GET(reg, 16, 19) +#define GIC_DIST_ICDIIDR_VARIANT_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19) +#define GIC_DIST_ICDIIDR_REVISION(val) BSP_FLD32(val, 12, 15) +#define GIC_DIST_ICDIIDR_REVISION_GET(reg) BSP_FLD32GET(reg, 12, 15) +#define GIC_DIST_ICDIIDR_REVISION_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) +#define GIC_DIST_ICDIIDR_IMPLEMENTER(val) BSP_FLD32(val, 0, 11) +#define GIC_DIST_ICDIIDR_IMPLEMENTER_GET(reg) BSP_FLD32GET(reg, 0, 11) +#define GIC_DIST_ICDIIDR_IMPLEMENTER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11) + uint32_t reserved_0c[29]; + uint32_t icdigr[32]; + uint32_t icdiser[32]; + uint32_t icdicer[32]; + uint32_t icdispr[32]; + uint32_t icdicpr[32]; + uint32_t icdabr[32]; + uint32_t reserved_380[32]; + uint8_t icdipr[256]; + uint32_t reserved_500[192]; + uint8_t icdiptr[256]; + uint32_t reserved_900[192]; + uint32_t icdicfr[64]; + /* GICD_IGRPMODR GICv3 only, reserved in GICv1/GICv2 */ + uint32_t icdigmr[32]; + uint32_t reserved_d80[96]; + uint32_t icdsgir; +#define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(val) BSP_FLD32(val, 24, 25) +#define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER_GET(reg) BSP_FLD32GET(reg, 24, 25) +#define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER_SET(reg, val) BSP_FLD32SET(reg, val, 24, 25) +#define GIC_DIST_ICDSGIR_CPU_TARGET_LIST(val) BSP_FLD32(val, 16, 23) +#define GIC_DIST_ICDSGIR_CPU_TARGET_LIST_GET(reg) BSP_FLD32GET(reg, 16, 23) +#define GIC_DIST_ICDSGIR_CPU_TARGET_LIST_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23) +#define GIC_DIST_ICDSGIR_NSATT BSP_BIT32(15) +#define GIC_DIST_ICDSGIR_SGIINTID(val) BSP_FLD32(val, 0, 3) +#define GIC_DIST_ICDSGIR_SGIINTID_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define GIC_DIST_ICDSGIR_SGIINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) +} gic_dist; + +/* GICv3 only */ +typedef struct { + /* GICR_CTLR */ + uint32_t icrrcr; +#define GIC_REDIST_ICRRCR_UWP BSP_BIT32(31) +#define GIC_REDIST_ICRRCR_DPG1S BSP_BIT32(26) +#define GIC_REDIST_ICRRCR_DPG1NS BSP_BIT32(25) +#define GIC_REDIST_ICRRCR_DPG0 BSP_BIT32(24) +#define GIC_REDIST_ICRRCR_RWP BSP_BIT32(4) +#define GIC_REDIST_ICRRCR_ENABLE_LPI BSP_BIT32(0) + uint32_t icriidr; + uint64_t icrtyper; +#define GIC_REDIST_ICRTYPER_AFFINITY_VALUE(val) BSP_FLD64(val, 32, 63) +#define GIC_REDIST_ICRTYPER_AFFINITY_VALUE_GET(reg) BSP_FLD64GET(reg, 32, 63) +#define GIC_REDIST_ICRTYPER_AFFINITY_VALUE_SET(reg, val) BSP_FLD64SET(reg, val, 32, 63) +#define GIC_REDIST_ICRTYPER_COMMON_LPI_AFFINITY(val) BSP_FLD64(val, 24, 25) +#define GIC_REDIST_ICRTYPER_COMMON_LPI_AFFINITY_GET(reg) BSP_FLD64GET(reg, 24, 25) +#define GIC_REDIST_ICRTYPER_COMMON_LPI_AFFINITY_SET(reg, val) BSP_FLD64SET(reg, val, 24, 25) +#define GIC_REDIST_ICRTYPER_CPU_NUMBER(val) BSP_FLD64(val, 8, 23) +#define GIC_REDIST_ICRTYPER_CPU_NUMBER_GET(reg) BSP_FLD64GET(reg, 8, 23) +#define GIC_REDIST_ICRTYPER_CPU_NUMBER_SET(reg, val) BSP_FLD64SET(reg, val, 8, 23) +#define GIC_REDIST_ICRTYPER_DPGS BSP_BIT64(5) +#define GIC_REDIST_ICRTYPER_LAST BSP_BIT64(4) +#define GIC_REDIST_ICRTYPER_DIRECT_LPI BSP_BIT64(3) +#define GIC_REDIST_ICRTYPER_VLPIS BSP_BIT64(1) +#define GIC_REDIST_ICRTYPER_PLPIS BSP_BIT64(0) + uint32_t unused_10; + uint32_t icrwaker; +#define GIC_REDIST_ICRWAKER_CHILDREN_ASLEEP BSP_BIT32(2) +#define GIC_REDIST_ICRWAKER_PROCESSOR_SLEEP BSP_BIT32(1) +} gic_redist; + +/* GICv3 only */ +typedef struct { + uint32_t reserved_0_80[32]; + /* GICR_IGROUPR0 */ + uint32_t icspigrpr[32]; + /* GICR_ISENABLER0 */ + uint32_t icspiser[32]; + /* GICR_ICENABLER0 */ + uint32_t icspicer[32]; + /* GICR_ISPENDR0 */ + uint32_t icspispendr[32]; + /* GICR_ICPENDR0 */ + uint32_t icspicpendr[32]; + /* GICR_ISACTIVER0 */ + uint32_t icspisar[32]; + /* GICR_ICACTIVER0 */ + uint32_t icspicar[32]; + /* GICR_IPRIORITYR */ + uint8_t icspiprior[32]; + uint32_t reserved_420_bfc[504]; + /* GICR_ICFGR0 */ + uint32_t icspicfgr0; + /* GICR_ICFGR1 */ + uint32_t icspicfgr1; + uint32_t reserved_c08_cfc[62]; + /* GICR_IGRPMODR0 */ + uint32_t icspigrpmodr[64]; +} gic_sgi_ppi; + +#endif /* LIBBSP_ARM_SHARED_ARM_GIC_REGS_H */ diff --git a/bsps/include/dev/irq/arm-gic-tm27.h b/bsps/include/dev/irq/arm-gic-tm27.h new file mode 100644 index 0000000000..95f3077716 --- /dev/null +++ b/bsps/include/dev/irq/arm-gic-tm27.h @@ -0,0 +1,103 @@ +/** + * @file + * + * @ingroup arm_gic + * + * @brief ARM GIC TM27 Support + */ + +/* + * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef LIBBSP_ARM_SHARED_ARM_GIC_TM27_H +#define LIBBSP_ARM_SHARED_ARM_GIC_TM27_H + +#include + +#include +#include + +#define MUST_WAIT_FOR_INTERRUPT 1 + +#define ARM_GIC_TM27_IRQ_LOW ARM_GIC_IRQ_SGI_12 + +#define ARM_GIC_TM27_IRQ_HIGH ARM_GIC_IRQ_SGI_13 + +#define ARM_GIC_TM27_PRIO_LOW 0x80 + +#define ARM_GIC_TM27_PRIO_HIGH 0x00 + +static inline void Install_tm27_vector(void (*handler)(rtems_vector_number)) +{ + rtems_status_code sc = rtems_interrupt_handler_install( + ARM_GIC_TM27_IRQ_LOW, + "tm27 low", + RTEMS_INTERRUPT_UNIQUE, + (rtems_interrupt_handler) handler, + NULL + ); + assert(sc == RTEMS_SUCCESSFUL); + + sc = arm_gic_irq_set_priority( + ARM_GIC_TM27_IRQ_LOW, + ARM_GIC_TM27_PRIO_LOW + ); + assert(sc == RTEMS_SUCCESSFUL); + + sc = rtems_interrupt_handler_install( + ARM_GIC_TM27_IRQ_HIGH, + "tm27 high", + RTEMS_INTERRUPT_UNIQUE, + (rtems_interrupt_handler) handler, + NULL + ); + assert(sc == RTEMS_SUCCESSFUL); + + sc = arm_gic_irq_set_priority( + ARM_GIC_TM27_IRQ_HIGH, + ARM_GIC_TM27_PRIO_HIGH + ); + assert(sc == RTEMS_SUCCESSFUL); +} + +static inline void Cause_tm27_intr(void) +{ + rtems_status_code sc = arm_gic_irq_generate_software_irq( + ARM_GIC_TM27_IRQ_LOW, + ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF, + 0 + ); + assert(sc == RTEMS_SUCCESSFUL); +} + +static inline void Clear_tm27_intr(void) +{ + /* Nothing to do */ +} + +static inline void Lower_tm27_intr(void) +{ + rtems_status_code sc = arm_gic_irq_generate_software_irq( + ARM_GIC_TM27_IRQ_HIGH, + ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF, + 0 + ); + assert(sc == RTEMS_SUCCESSFUL); +} + +#endif /* LIBBSP_ARM_SHARED_ARM_GIC_TM27_H */ diff --git a/bsps/include/dev/irq/arm-gic.h b/bsps/include/dev/irq/arm-gic.h new file mode 100644 index 0000000000..23c70e7b0e --- /dev/null +++ b/bsps/include/dev/irq/arm-gic.h @@ -0,0 +1,242 @@ +/** + * @file + * + * @ingroup arm_gic + * + * @brief ARM GIC Support + */ + +/* + * Copyright (c) 2013, 2019 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_SHARED_ARM_GIC_H +#define LIBBSP_ARM_SHARED_ARM_GIC_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup arm_gic ARM GIC + * + * @ingroup RTEMSBSPsARMShared + * + * @brief ARM_GIC Support Package + */ + +#define GIC_ID_TO_ONE_BIT_REG_INDEX(id) ((id) >> 5) +#define GIC_ID_TO_ONE_BIT_REG_BIT(id) (1U << ((id) & 0x1fU)) + +#define GIC_ID_TO_TWO_BITS_REG_INDEX(id) ((id) >> 4) +#define GIC_ID_TO_TWO_BITS_REG_OFFSET(id) (((id) & 0xfU) << 1) + +static inline bool gic_id_is_enabled(volatile gic_dist *dist, uint32_t id) +{ + uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); + uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); + + return (dist->icdiser[i] & bit) != 0; +} + +static inline void gic_id_enable(volatile gic_dist *dist, uint32_t id) +{ + uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); + uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); + + dist->icdiser[i] = bit; +} + +static inline void gic_id_disable(volatile gic_dist *dist, uint32_t id) +{ + uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); + uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); + + dist->icdicer[i] = bit; +} + +static inline bool gic_id_is_pending(volatile gic_dist *dist, uint32_t id) +{ + uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); + uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); + + return (dist->icdispr[i] & bit) != 0; +} + +static inline void gic_id_set_pending(volatile gic_dist *dist, uint32_t id) +{ + uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); + uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); + + dist->icdispr[i] = bit; +} + +static inline void gic_id_clear_pending(volatile gic_dist *dist, uint32_t id) +{ + uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); + uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); + + dist->icdicpr[i] = bit; +} + +static inline bool gic_id_is_active(volatile gic_dist *dist, uint32_t id) +{ + uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); + uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); + + return (dist->icdabr[i] & bit) != 0; +} + +typedef enum { + GIC_GROUP_0, + GIC_GROUP_1 +} gic_group; + +static inline gic_group gic_id_get_group( + volatile gic_dist *dist, + uint32_t id +) +{ + uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); + uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); + + return (dist->icdigr[i] & bit) != 0 ? GIC_GROUP_1 : GIC_GROUP_0; +} + +static inline void gic_id_set_group( + volatile gic_dist *dist, + uint32_t id, + gic_group group +) +{ + uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); + uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); + uint32_t icdigr = dist->icdigr[i]; + + icdigr &= ~bit; + + if (group == GIC_GROUP_1) { + icdigr |= bit; + } + + dist->icdigr[i] = icdigr; +} + +static inline void gic_id_set_priority( + volatile gic_dist *dist, + uint32_t id, + uint8_t priority +) +{ + dist->icdipr[id] = priority; +} + +static inline uint8_t gic_id_get_priority(volatile gic_dist *dist, uint32_t id) +{ + return dist->icdipr[id]; +} + +static inline void gic_id_set_targets( + volatile gic_dist *dist, + uint32_t id, + uint8_t targets +) +{ + dist->icdiptr[id] = targets; +} + +static inline uint8_t gic_id_get_targets(volatile gic_dist *dist, uint32_t id) +{ + return dist->icdiptr[id]; +} + +typedef enum { + GIC_LEVEL_SENSITIVE, + GIC_EDGE_TRIGGERED +} gic_trigger_mode; + +static inline gic_trigger_mode gic_id_get_trigger_mode( + volatile gic_dist *dist, + uint32_t id +) +{ + uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(id); + uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(id) + 1; + uint32_t bit = 1U << o; + + return (dist->icdicfr[i] & bit) != 0 ? + GIC_EDGE_TRIGGERED : GIC_LEVEL_SENSITIVE; +} + +static inline void gic_id_set_trigger_mode( + volatile gic_dist *dist, + uint32_t id, + gic_trigger_mode mode +) +{ + uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(id); + uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(id) + 1; + uint32_t bit = mode << o; + uint32_t mask = 1U << o; + uint32_t icdicfr = dist->icdicfr[i]; + + icdicfr &= ~mask; + icdicfr |= bit; + + dist->icdicfr[i] = icdicfr; +} + +typedef enum { + GIC_N_TO_N, + GIC_1_TO_N +} gic_handling_model; + +static inline gic_handling_model gic_id_get_handling_model( + volatile gic_dist *dist, + uint32_t id +) +{ + uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(id); + uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(id); + uint32_t bit = 1U << o; + + return (dist->icdicfr[i] & bit) != 0 ? GIC_1_TO_N : GIC_N_TO_N; +} + +static inline void gic_id_set_handling_model( + volatile gic_dist *dist, + uint32_t id, + gic_handling_model model +) +{ + uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(id); + uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(id); + uint32_t bit = model << o; + uint32_t mask = 1U << o; + uint32_t icdicfr = dist->icdicfr[i]; + + icdicfr &= ~mask; + icdicfr |= bit; + + dist->icdicfr[i] = icdicfr; +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_ARM_SHARED_ARM_GIC_H */ diff --git a/bsps/shared/dev/irq/arm-gicv3.c b/bsps/shared/dev/irq/arm-gicv3.c new file mode 100644 index 0000000000..ad39872eb0 --- /dev/null +++ b/bsps/shared/dev/irq/arm-gicv3.c @@ -0,0 +1,354 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (C) 2019 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include +#include +#include + +#define PRIORITY_DEFAULT 127 + +#define MPIDR_AFFINITY2(val) BSP_FLD64(val, 16, 23) +#define MPIDR_AFFINITY2_GET(reg) BSP_FLD64GET(reg, 16, 23) +#define MPIDR_AFFINITY2_SET(reg, val) BSP_FLD64SET(reg, val, 16, 23) +#define MPIDR_AFFINITY1(val) BSP_FLD64(val, 8, 15) +#define MPIDR_AFFINITY1_GET(reg) BSP_FLD64GET(reg, 8, 15) +#define MPIDR_AFFINITY1_SET(reg, val) BSP_FLD64SET(reg, val, 8, 15) +#define MPIDR_AFFINITY0(val) BSP_FLD64(val, 0, 7) +#define MPIDR_AFFINITY0_GET(reg) BSP_FLD64GET(reg, 0, 7) +#define MPIDR_AFFINITY0_SET(reg, val) BSP_FLD64SET(reg, val, 0, 7) + +#define ICC_SGIR_AFFINITY3(val) BSP_FLD64(val, 48, 55) +#define ICC_SGIR_AFFINITY3_GET(reg) BSP_FLD64GET(reg, 48, 55) +#define ICC_SGIR_AFFINITY3_SET(reg, val) BSP_FLD64SET(reg, val, 48, 55) +#define ICC_SGIR_IRM BSP_BIT32(40) +#define ICC_SGIR_AFFINITY2(val) BSP_FLD64(val, 32, 39) +#define ICC_SGIR_AFFINITY2_GET(reg) BSP_FLD64GET(reg, 32, 39) +#define ICC_SGIR_AFFINITY2_SET(reg, val) BSP_FLD64SET(reg, val, 32, 39) +#define ICC_SGIR_INTID(val) BSP_FLD64(val, 24, 27) +#define ICC_SGIR_INTID_GET(reg) BSP_FLD64GET(reg, 24, 27) +#define ICC_SGIR_INTID_SET(reg, val) BSP_FLD64SET(reg, val, 24, 27) +#define ICC_SGIR_AFFINITY1(val) BSP_FLD64(val, 16, 23) +#define ICC_SGIR_AFFINITY1_GET(reg) BSP_FLD64GET(reg, 16, 23) +#define ICC_SGIR_AFFINITY1_SET(reg, val) BSP_FLD64SET(reg, val, 16, 23) +#define ICC_SGIR_CPU_TARGET_LIST(val) BSP_FLD64(val, 0, 15) +#define ICC_SGIR_CPU_TARGET_LIST_GET(reg) BSP_FLD64GET(reg, 0, 15) +#define ICC_SGIR_CPU_TARGET_LIST_SET(reg, val) BSP_FLD64SET(reg, val, 0, 15) + +#ifdef ARM_MULTILIB_ARCH_V4 +/* cpuif->iccicr */ +#define ICC_CTLR "p15, 0, %0, c12, c12, 4" + +/* cpuif->iccpmr */ +#define ICC_PMR "p15, 0, %0, c4, c6, 0" + +/* cpuif->iccbpr */ +#define ICC_BPR0 "p15, 0, %0, c12, c8, 3" +#define ICC_BPR1 "p15, 0, %0, c12, c12, 3" + +/* cpuif->icciar */ +#define ICC_IAR0 "p15, 0, %0, c12, c8, 0" +#define ICC_IAR1 "p15, 0, %0, c12, c12, 0" + +/* cpuif->icceoir */ +#define ICC_EOIR0 "p15, 0, %0, c12, c8, 1" +#define ICC_EOIR1 "p15, 0, %0, c12, c12, 1" + +#define ICC_SRE "p15, 0, %0, c12, c12, 5" + +#define ICC_IGRPEN0 "p15, 0, %0, c12, c12, 6" +#define ICC_IGRPEN1 "p15, 0, %0, c12, c12, 7" + +#define MPIDR "p15, 0, %0, c0, c0, 5" + +#define READ_SR(SR_NAME) \ +({ \ + uint32_t value; \ + __asm__ volatile("mrc " SR_NAME : "=r" (value) ); \ + value; \ +}) + +#define WRITE_SR(SR_NAME, VALUE) \ + __asm__ volatile("mcr " SR_NAME " \n" : : "r" (VALUE) ); + +#define ICC_SGI1 "p15, 0, %Q0, %R0, c12" +#define WRITE64_SR(SR_NAME, VALUE) \ + __asm__ volatile("mcrr " SR_NAME " \n" : : "r" (VALUE) ); + +#else /* ARM_MULTILIB_ARCH_V4 */ + +/* AArch64 GICv3 registers are not named in GCC */ +#define ICC_IGRPEN0 "S3_0_C12_C12_6, %0" +#define ICC_IGRPEN1 "S3_0_C12_C12_7, %0" +#define ICC_PMR "S3_0_C4_C6_0, %0" +#define ICC_EOIR1 "S3_0_C12_C12_1, %0" +#define ICC_SRE "S3_0_C12_C12_5, %0" +#define ICC_BPR0 "S3_0_C12_C8_3, %0" +#define ICC_CTLR "S3_0_C12_C12_4, %0" +#define ICC_IAR1 "%0, S3_0_C12_C12_0" +#define MPIDR "%0, mpidr_el1" +#define MPIDR_AFFINITY3(val) BSP_FLD64(val, 32, 39) +#define MPIDR_AFFINITY3_GET(reg) BSP_FLD64GET(reg, 32, 39) +#define MPIDR_AFFINITY3_SET(reg, val) BSP_FLD64SET(reg, val, 32, 39) + +#define ICC_SGI1 "S3_0_C12_C11_5, %0" +#define WRITE64_SR(SR_NAME, VALUE) \ + __asm__ volatile("msr " SR_NAME " \n" : : "r" (VALUE) ); +#define WRITE_SR(SR_NAME, VALUE) WRITE64_SR(SR_NAME, VALUE) + +#define READ_SR(SR_NAME) \ +({ \ + uint64_t value; \ + __asm__ volatile("mrs " SR_NAME : "=&r" (value) ); \ + value; \ +}) + + +#endif /* ARM_MULTILIB_ARCH_V4 */ + +#define ARM_GIC_REDIST ((volatile gic_redist *) BSP_ARM_GIC_REDIST_BASE) +#define ARM_GIC_SGI_PPI (((volatile gic_sgi_ppi *) ((char*)BSP_ARM_GIC_REDIST_BASE + (1 << 16)))) + +void gicv3_interrupt_dispatch(void) +{ + uint32_t icciar = READ_SR(ICC_IAR1); + rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar); + rtems_vector_number spurious = 1023; + + if (vector != spurious) { + arm_interrupt_handler_dispatch(vector); + + WRITE_SR(ICC_EOIR1, icciar); + } +} + +void bsp_interrupt_vector_enable(rtems_vector_number vector) +{ + volatile gic_dist *dist = ARM_GIC_DIST; + volatile gic_sgi_ppi *sgi_ppi = ARM_GIC_SGI_PPI; + + bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); + + /* TODO(kmoore) This could use some cleanup and integration + * Vectors below 32 are currently routed through the redistributor */ + if (vector >= 32) { + gic_id_enable(dist, vector); + } else { + sgi_ppi->icspiser[0] = 1 << (vector % 32); + } +} + +void bsp_interrupt_vector_disable(rtems_vector_number vector) +{ + volatile gic_dist *dist = ARM_GIC_DIST; + volatile gic_sgi_ppi *sgi_ppi = ARM_GIC_SGI_PPI; + + bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); + + if (vector >= 32) { + gic_id_disable(dist, vector); + } else { + sgi_ppi->icspicer[0] = 1 << (vector % 32); + } +} + +static inline uint32_t get_id_count(volatile gic_dist *dist) +{ + uint32_t id_count = GIC_DIST_ICDICTR_IT_LINES_NUMBER_GET(dist->icdictr); + + id_count = 32 * (id_count + 1); + id_count = id_count <= 1020 ? id_count : 1020; + + return id_count; +} + +static void init_cpu_interface(void) +{ + uint32_t sre_value = 0x7; + WRITE_SR(ICC_SRE, sre_value); + WRITE_SR(ICC_PMR, GIC_CPUIF_ICCPMR_PRIORITY(0xff)); + WRITE_SR(ICC_BPR0, GIC_CPUIF_ICCBPR_BINARY_POINT(0x0)); + + volatile gic_redist *redist = ARM_GIC_REDIST; + uint32_t waker = redist->icrwaker; + uint32_t waker_mask = GIC_REDIST_ICRWAKER_PROCESSOR_SLEEP; + waker &= ~waker_mask; + redist->icrwaker = waker; + + /* Set interrupt group to 1NS for SGI/PPI interrupts routed through the redistributor */ + volatile gic_sgi_ppi *sgi_ppi = ARM_GIC_SGI_PPI; + sgi_ppi->icspigrpr[0] = 0xffffffff; + sgi_ppi->icspigrpmodr[0] = 0; + for (int id = 0; id < 32; id++) { + sgi_ppi->icspiprior[id] = PRIORITY_DEFAULT; + } + + /* Enable interrupt groups 0 and 1 */ + WRITE_SR(ICC_IGRPEN0, 0x1); + WRITE_SR(ICC_IGRPEN1, 0x1); + WRITE_SR(ICC_CTLR, 0x0); +} + +rtems_status_code bsp_interrupt_facility_initialize(void) +{ + volatile gic_dist *dist = ARM_GIC_DIST; + uint32_t id_count = get_id_count(dist); + uint32_t id; + + arm_interrupt_facility_set_exception_handler(); + + dist->icddcr = GIC_DIST_ICDDCR_ARE_NS | GIC_DIST_ICDDCR_ARE_S + | GIC_DIST_ICDDCR_ENABLE_GRP1S | GIC_DIST_ICDDCR_ENABLE_GRP1NS + | GIC_DIST_ICDDCR_ENABLE_GRP0; + + for (id = 0; id < id_count; id += 32) { + /* Disable all interrupts */ + dist->icdicer[id / 32] = 0xffffffff; + + /* Set interrupt group to 1NS for all interrupts */ + dist->icdigr[id / 32] = 0xffffffff; + dist->icdigmr[id / 32] = 0; + } + + for (id = 0; id < id_count; ++id) { + gic_id_set_priority(dist, id, PRIORITY_DEFAULT); + } + + for (id = 32; id < id_count; ++id) { + gic_id_set_targets(dist, id, 0x01); + } + + init_cpu_interface(); + return RTEMS_SUCCESSFUL; +} + +#ifdef RTEMS_SMP +BSP_START_TEXT_SECTION void arm_gic_irq_initialize_secondary_cpu(void) +{ + volatile gic_dist *dist = ARM_GIC_DIST; + + while ((dist->icddcr & GIC_DIST_ICDDCR_ENABLE) == 0) { + /* Wait */ + } + +#error modify init_cpu_interface to use correct offsets for each CPU + init_cpu_interface(); +} +#endif + +rtems_status_code arm_gic_irq_set_priority( + rtems_vector_number vector, + uint8_t priority +) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + + if (bsp_interrupt_is_valid_vector(vector)) { + if (vector < 32) { + volatile gic_sgi_ppi *sgi_ppi = ARM_GIC_SGI_PPI; + sgi_ppi->icspiprior[vector] = priority; + } else { + volatile gic_dist *dist = ARM_GIC_DIST; + gic_id_set_priority(dist, vector, priority); + } + } else { + sc = RTEMS_INVALID_ID; + } + + return sc; +} + +rtems_status_code arm_gic_irq_get_priority( + rtems_vector_number vector, + uint8_t *priority +) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + + if (bsp_interrupt_is_valid_vector(vector)) { + if (vector < 32) { + volatile gic_sgi_ppi *sgi_ppi = ARM_GIC_SGI_PPI; + *priority = sgi_ppi->icspiprior[vector]; + } else { + volatile gic_dist *dist = ARM_GIC_DIST; + *priority = gic_id_get_priority(dist, vector); + } + } else { + sc = RTEMS_INVALID_ID; + } + + return sc; +} + +void bsp_interrupt_set_affinity( + rtems_vector_number vector, + const Processor_mask *affinity +) +{ + volatile gic_dist *dist = ARM_GIC_DIST; + uint8_t targets = (uint8_t) _Processor_mask_To_uint32_t(affinity, 0); + + gic_id_set_targets(dist, vector, targets); +} + +void bsp_interrupt_get_affinity( + rtems_vector_number vector, + Processor_mask *affinity +) +{ + volatile gic_dist *dist = ARM_GIC_DIST; + uint8_t targets = gic_id_get_targets(dist, vector); + + _Processor_mask_From_uint32_t(affinity, targets, 0); +} + +void arm_gic_trigger_sgi( + rtems_vector_number vector, + arm_gic_irq_software_irq_target_filter filter, + uint8_t targets +) +{ + /* TODO(kmoore) Handle filter: + * ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST, + * ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_EXCEPT_SELF, + * ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF */ +#ifndef ARM_MULTILIB_ARCH_V4 + uint64_t mpidr; +#else + uint32_t mpidr; +#endif + mpidr = READ_SR(MPIDR); + uint64_t value = ICC_SGIR_AFFINITY2(MPIDR_AFFINITY2_GET(mpidr)) + | ICC_SGIR_INTID(vector) + | ICC_SGIR_AFFINITY1(MPIDR_AFFINITY1_GET(mpidr)) + | ICC_SGIR_CPU_TARGET_LIST(1); +#ifndef ARM_MULTILIB_ARCH_V4 + value |= ICC_SGIR_AFFINITY3(MPIDR_AFFINITY3_GET(mpidr)); +#endif + WRITE64_SR(ICC_SGI1, value); +} -- cgit v1.2.3