From d03776e804e2cb190442d2a2debf297714ca8049 Mon Sep 17 00:00:00 2001 From: Alex White Date: Thu, 30 Sep 2021 23:57:01 -0500 Subject: microblaze: Rework for RTEMS 6 This reworks the existing MicroBlaze architecture port and BSP to achieve basic functionality using the latest RTEMS APIs. --- bsps/include/bsp/fatal.h | 3 + bsps/microblaze/include/bsp/linker-symbols.h | 106 +++++++ bsps/microblaze/include/common/xil_types.h | 197 +++++++++++++ bsps/microblaze/include/dev/serial/uartlite.h | 62 ++++ bsps/microblaze/include/dev/serial/uartlite_l.h | 323 +++++++++++++++++++++ bsps/microblaze/microblaze_fpga/clock/clock.c | 145 +++++++++ .../microblaze_fpga/console/console-io.c | 57 ++++ bsps/microblaze/microblaze_fpga/console/debug-io.c | 66 +++++ bsps/microblaze/microblaze_fpga/include/bsp.h | 53 ++++ bsps/microblaze/microblaze_fpga/include/bsp/intc.h | 74 +++++ bsps/microblaze/microblaze_fpga/include/bsp/irq.h | 49 ++++ .../microblaze/microblaze_fpga/include/bsp/timer.h | 69 +++++ bsps/microblaze/microblaze_fpga/include/tm27.h | 58 ++++ bsps/microblaze/microblaze_fpga/irq/irq.c | 168 +++++++++++ .../microblaze_fpga/start/_exception_handler.S | 52 ++++ .../microblaze_fpga/start/_hw_exception_handler.S | 52 ++++ .../microblaze_fpga/start/_interrupt_handler.S | 53 ++++ bsps/microblaze/microblaze_fpga/start/bspreset.c | 44 +++ bsps/microblaze/microblaze_fpga/start/bspstart.c | 43 +++ bsps/microblaze/microblaze_fpga/start/crtinit.S | 103 +++++++ bsps/microblaze/shared/cache/cache.c | 36 +++ bsps/microblaze/shared/dev/serial/uartlite.c | 145 +++++++++ bsps/microblaze/shared/dev/serial/uartlite_l.c | 99 +++++++ bsps/microblaze/shared/start/start.S | 114 ++++++++ 24 files changed, 2171 insertions(+) create mode 100644 bsps/microblaze/include/bsp/linker-symbols.h create mode 100644 bsps/microblaze/include/common/xil_types.h create mode 100644 bsps/microblaze/include/dev/serial/uartlite.h create mode 100644 bsps/microblaze/include/dev/serial/uartlite_l.h create mode 100644 bsps/microblaze/microblaze_fpga/clock/clock.c create mode 100644 bsps/microblaze/microblaze_fpga/console/console-io.c create mode 100644 bsps/microblaze/microblaze_fpga/console/debug-io.c create mode 100644 bsps/microblaze/microblaze_fpga/include/bsp.h create mode 100644 bsps/microblaze/microblaze_fpga/include/bsp/intc.h create mode 100644 bsps/microblaze/microblaze_fpga/include/bsp/irq.h create mode 100644 bsps/microblaze/microblaze_fpga/include/bsp/timer.h create mode 100644 bsps/microblaze/microblaze_fpga/include/tm27.h create mode 100644 bsps/microblaze/microblaze_fpga/irq/irq.c create mode 100644 bsps/microblaze/microblaze_fpga/start/_exception_handler.S create mode 100644 bsps/microblaze/microblaze_fpga/start/_hw_exception_handler.S create mode 100644 bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S create mode 100644 bsps/microblaze/microblaze_fpga/start/bspreset.c create mode 100644 bsps/microblaze/microblaze_fpga/start/bspstart.c create mode 100644 bsps/microblaze/microblaze_fpga/start/crtinit.S create mode 100644 bsps/microblaze/shared/cache/cache.c create mode 100644 bsps/microblaze/shared/dev/serial/uartlite.c create mode 100644 bsps/microblaze/shared/dev/serial/uartlite_l.c create mode 100644 bsps/microblaze/shared/start/start.S (limited to 'bsps') diff --git a/bsps/include/bsp/fatal.h b/bsps/include/bsp/fatal.h index f9b9e39193..a11235d00f 100644 --- a/bsps/include/bsp/fatal.h +++ b/bsps/include/bsp/fatal.h @@ -174,6 +174,9 @@ typedef enum { IMXRT_FATAL_LPI2C_HW_INIT_FAILED, IMXRT_FATAL_LPI2C_REGISTER_FAILED, IMXRT_FATAL_LPI2C_UNSUPPORTED_HARDWARE, + + /* MicroBlaze fatal codes */ + MICROBLAZE_FATAL_CLOCK_IRQ_INSTALL = BSP_FATAL_CODE_BLOCK(16), } bsp_fatal_code; RTEMS_NO_RETURN static inline void diff --git a/bsps/microblaze/include/bsp/linker-symbols.h b/bsps/microblaze/include/bsp/linker-symbols.h new file mode 100644 index 0000000000..da162060b5 --- /dev/null +++ b/bsps/microblaze/include/bsp/linker-symbols.h @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2015 Hesham Almatary + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_MICROBLAZE_SHARED_LINKER_SYMBOLS_H +#define LIBBSP_MICROBLAZE_SHARED_LINKER_SYMBOLS_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup microblaze Linker Support + * + * @ingroup microblaze_shared + * + * @brief Linker support. + * + * @{ + */ + +#ifndef ASM + #define LINKER_SYMBOL(sym) extern char sym []; +#else + #define LINKER_SYMBOL(sym) .extern sym +#endif + +LINKER_SYMBOL(bsp_section_start_begin) +LINKER_SYMBOL(bsp_section_start_end) +LINKER_SYMBOL(bsp_section_start_size) + +LINKER_SYMBOL(bsp_section_vector_begin) +LINKER_SYMBOL(bsp_section_vector_end) +LINKER_SYMBOL(bsp_section_vector_size) + +LINKER_SYMBOL(bsp_section_text_begin) +LINKER_SYMBOL(bsp_section_text_end) +LINKER_SYMBOL(bsp_section_text_size) +LINKER_SYMBOL(bsp_section_text_load_begin) +LINKER_SYMBOL(bsp_section_text_load_end) + +LINKER_SYMBOL(bsp_section_rodata_begin) +LINKER_SYMBOL(bsp_section_rodata_end) +LINKER_SYMBOL(bsp_section_rodata_size) +LINKER_SYMBOL(bsp_section_rodata_load_begin) +LINKER_SYMBOL(bsp_section_rodata_load_end) + +LINKER_SYMBOL(bsp_section_data_begin) +LINKER_SYMBOL(bsp_section_data_end) +LINKER_SYMBOL(bsp_section_data_size) +LINKER_SYMBOL(bsp_section_data_load_begin) +LINKER_SYMBOL(bsp_section_data_load_end) + +LINKER_SYMBOL(bsp_section_bss_begin) +LINKER_SYMBOL(bsp_section_bss_end) +LINKER_SYMBOL(bsp_section_bss_size) + +LINKER_SYMBOL(bsp_section_work_begin) +LINKER_SYMBOL(bsp_section_work_end) +LINKER_SYMBOL(bsp_section_work_size) + +LINKER_SYMBOL(bsp_section_stack_begin) +LINKER_SYMBOL(bsp_section_stack_end) +LINKER_SYMBOL(bsp_section_stack_size) + +LINKER_SYMBOL(bsp_vector_table_begin) +LINKER_SYMBOL(bsp_vector_table_end) +LINKER_SYMBOL(bsp_vector_table_size) + +LINKER_SYMBOL(bsp_start_vector_table_begin) +LINKER_SYMBOL(bsp_start_vector_table_end) +LINKER_SYMBOL(bsp_start_vector_table_size) + +LINKER_SYMBOL(bsp_translation_table_base) +LINKER_SYMBOL(bsp_translation_table_end) + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_MICROBLAZE_SHARED_LINKER_SYMBOLS_H */ diff --git a/bsps/microblaze/include/common/xil_types.h b/bsps/microblaze/include/common/xil_types.h new file mode 100644 index 0000000000..929e83f8f0 --- /dev/null +++ b/bsps/microblaze/include/common/xil_types.h @@ -0,0 +1,197 @@ +/****************************************************************************** +* Copyright (c) 2010 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_types.h +* +* @addtogroup common_types Basic Data types for Xilinx® Software IP +* +* The xil_types.h file contains basic types for Xilinx software IP. These data types +* are applicable for all processors supported by Xilinx. +* @{ +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+* 3.03a sdm  05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+* 5.00 	pkp  05/29/14 Made changes for 64 bit architecture
+*	srt  07/14/14 Use standard definitions from stdint.h and stddef.h
+*		      Define LONG and ULONG datatypes and mask values
+* 7.00  mus  01/07/19 Add cpp extern macro
+* 7.1   aru  08/19/19 Shift the value in UPPER_32_BITS only if it
+*                     is 64-bit processor
+*
+* +******************************************************************************/ + +#ifndef XIL_TYPES_H /* prevent circular inclusions */ +#define XIL_TYPES_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/************************** Constant Definitions *****************************/ + +#ifndef TRUE +# define TRUE 1U +#endif + +#ifndef FALSE +# define FALSE 0U +#endif + +#ifndef NULL +#define NULL 0U +#endif + +#define XIL_COMPONENT_IS_READY 0x11111111U /**< In device drivers, This macro will be + assigend to "IsReady" member of driver + instance to indicate that driver + instance is initialized and ready to use. */ +#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< In device drivers, This macro will be assigend to + "IsStarted" member of driver instance + to indicate that driver instance is + started and it can be enabled. */ + +/* @name New types + * New simple types. + * @{ + */ +#ifndef __KERNEL__ +#ifndef XBASIC_TYPES_H +/* + * guarded against xbasic_types.h. + */ +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; +/** @}*/ +#define __XUINT64__ +typedef struct +{ + u32 Upper; + u32 Lower; +} Xuint64; + + +/*****************************************************************************/ +/** +* @brief Return the most significant half of the 64 bit data type. +* +* @param x is the 64 bit word. +* +* @return The upper 32 bits of the 64 bit word. +* +******************************************************************************/ +#define XUINT64_MSW(x) ((x).Upper) + +/*****************************************************************************/ +/** +* @brief Return the least significant half of the 64 bit data type. +* +* @param x is the 64 bit word. +* +* @return The lower 32 bits of the 64 bit word. +* +******************************************************************************/ +#define XUINT64_LSW(x) ((x).Lower) + +#endif /* XBASIC_TYPES_H */ + +/* + * xbasic_types.h does not typedef s* or u64 + */ +/** @{ */ +typedef char char8; +typedef int8_t s8; +typedef int16_t s16; +typedef int32_t s32; +typedef int64_t s64; +typedef uint64_t u64; +typedef int sint32; + +typedef intptr_t INTPTR; +typedef uintptr_t UINTPTR; +typedef ptrdiff_t PTRDIFF; +/** @}*/ +#if !defined(LONG) || !defined(ULONG) +typedef long LONG; +typedef unsigned long ULONG; +#endif + +#define ULONG64_HI_MASK 0xFFFFFFFF00000000U +#define ULONG64_LO_MASK ~ULONG64_HI_MASK + +#else +#include +#endif + +/** @{ */ +/** + * This data type defines an interrupt handler for a device. + * The argument points to the instance of the component + */ +typedef void (*XInterruptHandler) (void *InstancePtr); + +/** + * This data type defines an exception handler for a processor. + * The argument points to the instance of the component + */ +typedef void (*XExceptionHandler) (void *InstancePtr); + +/** + * @brief Returns 32-63 bits of a number. + * @param n : Number being accessed. + * @return Bits 32-63 of number. + * + * @note A basic shift-right of a 64- or 32-bit quantity. + * Use this to suppress the "right shift count >= width of type" + * warning when that quantity is 32-bits. + */ +#if defined (__aarch64__) || defined (__arch64__) +#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16)) +#else +#define UPPER_32_BITS(n) 0U +#endif +/** + * @brief Returns 0-31 bits of a number + * @param n : Number being accessed. + * @return Bits 0-31 of number + */ +#define LOWER_32_BITS(n) ((u32)(n)) + + + + +/************************** Constant Definitions *****************************/ + +#ifndef TRUE +#define TRUE 1U +#endif + +#ifndef FALSE +#define FALSE 0U +#endif + +#ifndef NULL +#define NULL 0U +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_types". +*/ \ No newline at end of file diff --git a/bsps/microblaze/include/dev/serial/uartlite.h b/bsps/microblaze/include/dev/serial/uartlite.h new file mode 100644 index 0000000000..6e288d4dc7 --- /dev/null +++ b/bsps/microblaze/include/dev/serial/uartlite.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze AXI UART Lite terminal definitions + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_MICROBLAZE_SHARED_UARTLITE_H +#define LIBBSP_MICROBLAZE_SHARED_UARTLITE_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { + rtems_termios_device_context base; + uintptr_t address; + uint32_t initial_baud; +#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS + bool transmitting; +#endif +} uart_lite_context; + +extern const rtems_termios_device_handler microblaze_uart_fns; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_MICROBLAZE_SHARED_UARTLITE_H */ diff --git a/bsps/microblaze/include/dev/serial/uartlite_l.h b/bsps/microblaze/include/dev/serial/uartlite_l.h new file mode 100644 index 0000000000..8c0598e191 --- /dev/null +++ b/bsps/microblaze/include/dev/serial/uartlite_l.h @@ -0,0 +1,323 @@ +/****************************************************************************** +* Copyright (C) 2002 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/****************************************************************************/ +/** +* +* @file xuartlite_l.h +* @addtogroup uartlite_v3_5 +* @{ +* +* This header file contains identifiers and low-level driver functions (or +* macros) that can be used to access the device. High-level driver functions +* are defined in xuartlite.h. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00b rpm  04/25/02 First release
+* 1.00b rpm  07/07/03 Removed references to XUartLite_GetControlReg macro
+*                     since the control register is write-only
+* 1.12a mta  03/21/07 Updated to new coding style
+* 1.13a sv   01/21/08 Updated driver to support access through DCR bus
+* 2.00a ktn  10/20/09 Updated to use HAL Processor APIs. The macros have been
+*		      renamed to remove _m from the name.
+* 3.2   sk   11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
+*                     Changed the prototypes of XUartLite_SendByte,
+*                     XUartLite_RecvByte APIs.
+*
+* +*****************************************************************************/ + +#ifndef XUARTLITE_L_H /* prevent circular inclusions */ +#define XUARTLITE_L_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#ifndef __rtems__ +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" +#else +#include +static inline u32 Xil_In32(UINTPTR Addr) +{ + return *(volatile u32 *) Addr; +} +static inline void Xil_Out32(UINTPTR Addr, u32 Value) +{ + volatile u32 *LocalAddr = (volatile u32 *)Addr; + *LocalAddr = Value; +} +#endif /* __rtems__ */ + +/* + * XPAR_XUARTLITE_USE_DCR_BRIDGE has to be set to 1 if the UartLite device is + * accessed through a DCR bus connected to a bridge. + */ +#define XPAR_XUARTLITE_USE_DCR_BRIDGE 0 + +#if (XPAR_XUARTLITE_USE_DCR_BRIDGE != 0) +#include "xio_dcr.h" +#endif + + +/************************** Constant Definitions ****************************/ + +/* UART Lite register offsets */ + +#if (XPAR_XUARTLITE_USE_DCR_BRIDGE != 0) +#define XUL_RX_FIFO_OFFSET 0 /* receive FIFO, read only */ +#define XUL_TX_FIFO_OFFSET 1 /* transmit FIFO, write only */ +#define XUL_STATUS_REG_OFFSET 2 /* status register, read only */ +#define XUL_CONTROL_REG_OFFSET 3 /* control reg, write only */ + +#else + +#define XUL_RX_FIFO_OFFSET 0 /* receive FIFO, read only */ +#define XUL_TX_FIFO_OFFSET 4 /* transmit FIFO, write only */ +#define XUL_STATUS_REG_OFFSET 8 /* status register, read only */ +#define XUL_CONTROL_REG_OFFSET 12 /* control reg, write only */ + +#endif + +/* Control Register bit positions */ + +#define XUL_CR_ENABLE_INTR 0x10 /* enable interrupt */ +#define XUL_CR_FIFO_RX_RESET 0x02 /* reset receive FIFO */ +#define XUL_CR_FIFO_TX_RESET 0x01 /* reset transmit FIFO */ + +/* Status Register bit positions */ + +#define XUL_SR_PARITY_ERROR 0x80 +#define XUL_SR_FRAMING_ERROR 0x40 +#define XUL_SR_OVERRUN_ERROR 0x20 +#define XUL_SR_INTR_ENABLED 0x10 /* interrupt enabled */ +#define XUL_SR_TX_FIFO_FULL 0x08 /* transmit FIFO full */ +#define XUL_SR_TX_FIFO_EMPTY 0x04 /* transmit FIFO empty */ +#define XUL_SR_RX_FIFO_FULL 0x02 /* receive FIFO full */ +#define XUL_SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */ + +/* The following constant specifies the size of the Transmit/Receive FIFOs. + * The FIFO size is fixed to 16 in the Uartlite IP and the size is not + * configurable. This constant is not used in the driver. + */ +#define XUL_FIFO_SIZE 16 + +/* Stop bits are fixed at 1. Baud, parity, and data bits are fixed on a + * per instance basis + */ +#define XUL_STOP_BITS 1 + +/* Parity definitions + */ +#define XUL_PARITY_NONE 0 +#define XUL_PARITY_ODD 1 +#define XUL_PARITY_EVEN 2 + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/* + * Define the appropriate I/O access method to memory mapped I/O or DCR. + */ +#if (XPAR_XUARTLITE_USE_DCR_BRIDGE != 0) + +#define XUartLite_In32 XIo_DcrIn +#define XUartLite_Out32 XIo_DcrOut + +#else + +#define XUartLite_In32 Xil_In32 +#define XUartLite_Out32 Xil_Out32 + +#endif + + +/****************************************************************************/ +/** +* +* Write a value to a UartLite register. A 32 bit write is performed. +* +* @param BaseAddress is the base address of the UartLite device. +* @param RegOffset is the register offset from the base to write to. +* @param Data is the data written to the register. +* +* @return None. +* +* @note C-style signature: +* void XUartLite_WriteReg(u32 BaseAddress, u32 RegOffset, +* u32 Data) +* +****************************************************************************/ +#define XUartLite_WriteReg(BaseAddress, RegOffset, Data) \ + XUartLite_Out32((BaseAddress) + (RegOffset), (u32)(Data)) + +/****************************************************************************/ +/** +* +* Read a value from a UartLite register. A 32 bit read is performed. +* +* @param BaseAddress is the base address of the UartLite device. +* @param RegOffset is the register offset from the base to read from. +* +* @return Data read from the register. +* +* @note C-style signature: +* u32 XUartLite_ReadReg(u32 BaseAddress, u32 RegOffset) +* +****************************************************************************/ +#define XUartLite_ReadReg(BaseAddress, RegOffset) \ + XUartLite_In32((BaseAddress) + (RegOffset)) + + +/****************************************************************************/ +/** +* +* Set the contents of the control register. Use the XUL_CR_* constants defined +* above to create the bit-mask to be written to the register. +* +* @param BaseAddress is the base address of the device +* @param Mask is the 32-bit value to write to the control register +* +* @return None. +* +* @note C-style Signature: +* void XUartLite_SetControlReg(u32 BaseAddress, u32 Mask); +* +*****************************************************************************/ +#define XUartLite_SetControlReg(BaseAddress, Mask) \ + XUartLite_WriteReg((BaseAddress), XUL_CONTROL_REG_OFFSET, (Mask)) + + +/****************************************************************************/ +/** +* +* Get the contents of the status register. Use the XUL_SR_* constants defined +* above to interpret the bit-mask returned. +* +* @param BaseAddress is the base address of the device +* +* @return A 32-bit value representing the contents of the status register. +* +* @note C-style Signature: +* u32 XUartLite_GetStatusReg(u32 BaseAddress); +* +*****************************************************************************/ +#define XUartLite_GetStatusReg(BaseAddress) \ + XUartLite_ReadReg((BaseAddress), XUL_STATUS_REG_OFFSET) + + +/****************************************************************************/ +/** +* +* Check to see if the receiver has data. +* +* @param BaseAddress is the base address of the device +* +* @return TRUE if the receiver is empty, FALSE if there is data present. +* +* @note C-style Signature: +* int XUartLite_IsReceiveEmpty(u32 BaseAddress); +* +*****************************************************************************/ +#define XUartLite_IsReceiveEmpty(BaseAddress) \ + ((XUartLite_GetStatusReg((BaseAddress)) & XUL_SR_RX_FIFO_VALID_DATA) != \ + XUL_SR_RX_FIFO_VALID_DATA) + + +/****************************************************************************/ +/** +* +* Check to see if the transmitter is full. +* +* @param BaseAddress is the base address of the device +* +* @return TRUE if the transmitter is full, FALSE otherwise. +* +* @note C-style Signature: +* int XUartLite_IsTransmitFull(u32 BaseAddress); +* +*****************************************************************************/ +#define XUartLite_IsTransmitFull(BaseAddress) \ + ((XUartLite_GetStatusReg((BaseAddress)) & XUL_SR_TX_FIFO_FULL) == \ + XUL_SR_TX_FIFO_FULL) + + +/****************************************************************************/ +/** +* +* Check to see if the interrupt is enabled. +* +* @param BaseAddress is the base address of the device +* +* @return TRUE if the interrupt is enabled, FALSE otherwise. +* +* @note C-style Signature: +* int XUartLite_IsIntrEnabled(u32 BaseAddress); +* +*****************************************************************************/ +#define XUartLite_IsIntrEnabled(BaseAddress) \ + ((XUartLite_GetStatusReg((BaseAddress)) & XUL_SR_INTR_ENABLED) == \ + XUL_SR_INTR_ENABLED) + + +/****************************************************************************/ +/** +* +* Enable the device interrupt. We cannot read the control register, so we +* just write the enable interrupt bit and clear all others. Since the only +* other ones are the FIFO reset bits, this works without side effects. +* +* @param BaseAddress is the base address of the device +* +* @return None. +* +* @note C-style Signature: +* void XUartLite_EnableIntr(u32 BaseAddress); +* +*****************************************************************************/ +#define XUartLite_EnableIntr(BaseAddress) \ + XUartLite_SetControlReg((BaseAddress), XUL_CR_ENABLE_INTR) + + +/****************************************************************************/ +/** +* +* Disable the device interrupt. We cannot read the control register, so we +* just clear all bits. Since the only other ones are the FIFO reset bits, +* this works without side effects. +* +* @param BaseAddress is the base address of the device +* +* @return None. +* +* @note C-style Signature: +* void XUartLite_DisableIntr(u32 BaseAddress); +* +*****************************************************************************/ +#define XUartLite_DisableIntr(BaseAddress) \ + XUartLite_SetControlReg((BaseAddress), 0) + +/************************** Function Prototypes *****************************/ + +void XUartLite_SendByte(UINTPTR BaseAddress, u8 Data); +u8 XUartLite_RecvByte(UINTPTR BaseAddress); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ + + +/** @} */ diff --git a/bsps/microblaze/microblaze_fpga/clock/clock.c b/bsps/microblaze/microblaze_fpga/clock/clock.c new file mode 100644 index 0000000000..957d0fdadb --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/clock/clock.c @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze AXI Timer clock support + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include +#include +#include + +static rtems_timecounter_simple mblaze_tc; + +static uint32_t microblaze_tc_get( rtems_timecounter_simple *tc ) +{ + volatile Microblaze_Timer *timer = _Microblaze_Timer; + return timer->tcr0; +} + +static bool microblaze_tc_is_pending( rtems_timecounter_simple *tc ) +{ + volatile Microblaze_Timer *timer = _Microblaze_Timer; + return ( timer->tcsr0 & MICROBLAZE_TIMER_TCSR0_T0INT ) != 0; +} + +static uint32_t microblaze_tc_get_timecount( struct timecounter *tc ) +{ + return rtems_timecounter_simple_downcounter_get( + tc, + microblaze_tc_get, + microblaze_tc_is_pending + ); +} + +static void microblaze_clock_initialize( void ) +{ + volatile Microblaze_Timer *timer = _Microblaze_Timer; + /* Set load register to 0 */ + timer->tlr0 = 0; + /* Reset the timer and interrupt */ + timer->tcsr0 = MICROBLAZE_TIMER_TCSR0_T0INT | MICROBLAZE_TIMER_TCSR0_LOAD0; + /* Release the reset */ + timer->tcsr0 = 0; + /* + * Enable interrupt, auto reload mode, external interrupt signal, + * and down counter + */ + timer->tcsr0 = MICROBLAZE_TIMER_TCSR0_ARHT0 | MICROBLAZE_TIMER_TCSR0_ENIT0 | + MICROBLAZE_TIMER_TCSR0_GENT0 | MICROBLAZE_TIMER_TCSR0_UDT0; + + uint64_t us_per_tick = rtems_configuration_get_microseconds_per_tick(); + uint32_t counter_frequency_in_hz = BSP_MICROBLAZE_FPGA_TIMER_FREQUENCY; + uint32_t counter_ticks_per_clock_tick = + ( counter_frequency_in_hz * us_per_tick ) / 1000000; + + /* Set a reset value for the timer counter */ + timer->tlr0 = counter_ticks_per_clock_tick; + uint32_t control_status_reg = timer->tcsr0; + /* Load the reset value into the counter register */ + timer->tcsr0 = MICROBLAZE_TIMER_TCSR0_LOAD0; + /* Enable the timer */ + timer->tcsr0 = control_status_reg | MICROBLAZE_TIMER_TCSR0_ENT0; + + rtems_timecounter_simple_install( + &mblaze_tc, + counter_frequency_in_hz, + counter_ticks_per_clock_tick, + microblaze_tc_get_timecount + ); +} + +static void microblaze_clock_at_tick( rtems_timecounter_simple *tc ) +{ + volatile Microblaze_Timer *timer = _Microblaze_Timer; + if ( ( timer->tcsr0 & MICROBLAZE_TIMER_TCSR0_T0INT ) == 0 ) { + return; + } + /* Clear the interrupt */ + timer->tcsr0 |= MICROBLAZE_TIMER_TCSR0_T0INT; +} + +static void microblaze_tc_tick( void ) +{ + rtems_timecounter_simple_downcounter_tick( + &mblaze_tc, + microblaze_tc_get, + microblaze_clock_at_tick + ); +} + +static void microblaze_clock_handler_install( rtems_interrupt_handler isr ) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + + sc = rtems_interrupt_handler_install( + 0, + "Clock", + RTEMS_INTERRUPT_UNIQUE, + isr, + NULL + ); + + if ( sc != RTEMS_SUCCESSFUL ) { + bsp_fatal( MICROBLAZE_FATAL_CLOCK_IRQ_INSTALL ); + } +} + +#define Clock_driver_support_initialize_hardware() microblaze_clock_initialize() +#define Clock_driver_support_install_isr( isr ) \ + microblaze_clock_handler_install( isr ) +#define Clock_driver_timecounter_tick() microblaze_tc_tick() + +/* Include shared source clock driver code */ +#include "../../shared/dev/clock/clockimpl.h" diff --git a/bsps/microblaze/microblaze_fpga/console/console-io.c b/bsps/microblaze/microblaze_fpga/console/console-io.c new file mode 100644 index 0000000000..cb2e367035 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/console/console-io.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze console configuration + */ + +/* + * Copyright (C) 2015 Hesham Almatary + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include + +uart_lite_context microblaze_qemu_uart_context = { + .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "UARTLITE" ), + .address = BSP_MICROBLAZE_FPGA_UART_BASE, + .initial_baud = 115200 +}; + +const console_device console_device_table[] = { + { + .device_file = "/dev/ttyS0", + .probe = console_device_probe_default, + .handler = µblaze_uart_fns, + .context = µblaze_qemu_uart_context.base + } +}; + +const size_t console_device_count = RTEMS_ARRAY_SIZE( console_device_table ); diff --git a/bsps/microblaze/microblaze_fpga/console/debug-io.c b/bsps/microblaze/microblaze_fpga/console/debug-io.c new file mode 100644 index 0000000000..e88f5468a7 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/console/debug-io.c @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze debug IO support + */ + +/* + * Copyright (C) 2015 Hesham Almatary + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include + +static void output_char( char c ) +{ + if ( c == '\n' ) { + XUartLite_SendByte( BSP_MICROBLAZE_FPGA_UART_BASE, '\r' ); + } + XUartLite_SendByte( BSP_MICROBLAZE_FPGA_UART_BASE, c ); +} + +static int xUartLite_RecvByte( int minor ) +{ + if ( XUartLite_IsReceiveEmpty( BSP_MICROBLAZE_FPGA_UART_BASE ) ) { + return -1; + } + + return XUartLite_ReadReg( BSP_MICROBLAZE_FPGA_UART_BASE, XUL_RX_FIFO_OFFSET ); +} + +static int get_char( void ) +{ + return xUartLite_RecvByte( 0 ); +} + +BSP_output_char_function_type BSP_output_char = output_char; + +BSP_polling_getchar_function_type BSP_poll_char = get_char; diff --git a/bsps/microblaze/microblaze_fpga/include/bsp.h b/bsps/microblaze/microblaze_fpga/include/bsp.h new file mode 100644 index 0000000000..e83e632553 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/include/bsp.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief Core BSP definitions + */ + +/* + * Copyright (C) 2015 Hesham Almatary + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_MICROBLAZE_FPGA_BSP_H +#define LIBBSP_MICROBLAZE_FPGA_BSP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include + +#ifdef __cplusplus +} +#endif + +#endif /* LIBBSP_MICROBLAZE_FPGA_BSP_H */ diff --git a/bsps/microblaze/microblaze_fpga/include/bsp/intc.h b/bsps/microblaze/microblaze_fpga/include/bsp/intc.h new file mode 100644 index 0000000000..df4554386d --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/include/bsp/intc.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze AXI Interrupt Controller definitions + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_MICROBLAZE_FPGA_INTC_H +#define LIBBSP_MICROBLAZE_FPGA_INTC_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { + /* Interrupt Status Register */ + uint32_t isr; + uint32_t ipr; + /* Interrupt Enable Register */ + uint32_t ier; + /* Interrupt Acknowledge Register */ + uint32_t iar; + uint32_t sie; + uint32_t cie; + uint32_t ivr; +#define MICROBLAZE_INTC_MER_HIE BSP_BIT32(1) +#define MICROBLAZE_INTC_MER_ME BSP_BIT32(0) + /* Master Enable Register */ + uint32_t mer; + /* Interrupt Mode Register, this is present only for Fast Interrupt */ + uint32_t imr; + /* Interrupt Level Register */ + uint32_t ilr; +} Microblaze_INTC; + +#define _Microblaze_INTC ((volatile Microblaze_INTC *) BSP_MICROBLAZE_FPGA_INTC_BASE) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_MICROBLAZE_FPGA_INTC_H */ diff --git a/bsps/microblaze/microblaze_fpga/include/bsp/irq.h b/bsps/microblaze/microblaze_fpga/include/bsp/irq.h new file mode 100644 index 0000000000..0a7c211fb0 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/include/bsp/irq.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief BSP IRQ definitions + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_MICROBLAZE_FPGA_IRQ_H +#define LIBBSP_MICROBLAZE_FPGA_IRQ_H + +#ifndef ASM + +#include +#include +#include + +#endif /* ASM */ + +#define BSP_INTERRUPT_VECTOR_COUNT 32 + +#endif /* LIBBSP_MICROBLAZE_FPGA_IRQ_H */ diff --git a/bsps/microblaze/microblaze_fpga/include/bsp/timer.h b/bsps/microblaze/microblaze_fpga/include/bsp/timer.h new file mode 100644 index 0000000000..562fdd79b0 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/include/bsp/timer.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze AXI Timer definitions + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_MICROBLAZE_FPGA_TIMER_H +#define LIBBSP_MICROBLAZE_FPGA_TIMER_H + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { +#define MICROBLAZE_TIMER_TCSR0_T0INT BSP_BIT32(8) +#define MICROBLAZE_TIMER_TCSR0_ENT0 BSP_BIT32(7) +#define MICROBLAZE_TIMER_TCSR0_ENIT0 BSP_BIT32(6) +#define MICROBLAZE_TIMER_TCSR0_LOAD0 BSP_BIT32(5) +#define MICROBLAZE_TIMER_TCSR0_ARHT0 BSP_BIT32(4) +#define MICROBLAZE_TIMER_TCSR0_GENT0 BSP_BIT32(2) +#define MICROBLAZE_TIMER_TCSR0_UDT0 BSP_BIT32(1) + /* Control/Status register */ + uint32_t tcsr0; + /* Load register */ + uint32_t tlr0; + /* Timer counter register */ + uint32_t tcr0; +} Microblaze_Timer; + +#define _Microblaze_Timer ((volatile Microblaze_Timer *) BSP_MICROBLAZE_FPGA_TIMER_BASE) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_MICROBLAZE_FPGA_TIMER_H */ diff --git a/bsps/microblaze/microblaze_fpga/include/tm27.h b/bsps/microblaze/microblaze_fpga/include/tm27.h new file mode 100644 index 0000000000..f2e384b534 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/include/tm27.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief BSP tm27 header + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Time Test 27 cannot be implemented reliably because the AXI interrupt + * controller is not guaranteed to support software interrupts. + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) /* set_vector( (handler), 6, 1 ) */ + +#define Cause_tm27_intr() /* empty */ + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +#endif /* __tm27_h */ diff --git a/bsps/microblaze/microblaze_fpga/irq/irq.c b/bsps/microblaze/microblaze_fpga/irq/irq.c new file mode 100644 index 0000000000..67ddf02079 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/irq/irq.c @@ -0,0 +1,168 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze interrupt support + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include + +static void ack_interrupt( uint8_t source ) +{ + volatile Microblaze_INTC *intc = _Microblaze_INTC; + intc->iar = 0x1 << source; +} + +rtems_status_code bsp_interrupt_get_attributes( + rtems_vector_number vector, + rtems_interrupt_attributes *attributes +) +{ + attributes->is_maskable = true; + attributes->maybe_enable = true; + attributes->maybe_disable = true; + attributes->can_clear = true; + attributes->cleared_by_acknowledge = true; + + return RTEMS_SUCCESSFUL; +} + +rtems_status_code bsp_interrupt_is_pending( + rtems_vector_number vector, + bool *pending +) +{ + bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) ); + bsp_interrupt_assert( pending != NULL ); + *pending = false; + return RTEMS_UNSATISFIED; +} + +rtems_status_code bsp_interrupt_raise( rtems_vector_number vector ) +{ + bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) ); + return RTEMS_UNSATISFIED; +} + +rtems_status_code bsp_interrupt_clear( rtems_vector_number vector ) +{ + bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) ); + + volatile Microblaze_INTC *intc = _Microblaze_INTC; + intc->iar = 0x1 << vector; + + return RTEMS_SUCCESSFUL; +} + +rtems_status_code bsp_interrupt_vector_is_enabled( + rtems_vector_number vector, + bool *enabled +) +{ + bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) ); + bsp_interrupt_assert( enabled != NULL ); + + volatile Microblaze_INTC *intc = _Microblaze_INTC; + uint32_t mask = 1 << vector; + + *enabled = (intc->ier & mask) != 0; + return RTEMS_SUCCESSFUL; +} + +rtems_status_code bsp_interrupt_vector_enable( rtems_vector_number vector ) +{ + bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) ); + + volatile Microblaze_INTC *intc = _Microblaze_INTC; + uint32_t mask = 1 << vector; + + intc->ier |= mask; + + return RTEMS_SUCCESSFUL; +} + +rtems_status_code bsp_interrupt_vector_disable( rtems_vector_number vector ) +{ + bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) ); + + volatile Microblaze_INTC *intc = _Microblaze_INTC; + uint32_t mask = 1 << vector; + + intc->ier &= ~mask; + + return RTEMS_SUCCESSFUL; +} + +void bsp_interrupt_facility_initialize( void ) +{ + volatile Microblaze_INTC *intc = _Microblaze_INTC; + /* + * Enable HW interrupts on the interrupt controller. This happens before + * interrupts are enabled on the processor. + */ + intc->mer = MICROBLAZE_INTC_MER_ME | MICROBLAZE_INTC_MER_HIE; +} + +void bsp_interrupt_dispatch( uint32_t source ) +{ + volatile Microblaze_INTC *intc = _Microblaze_INTC; + uint32_t vector_number = 0; + + if ( source == 0xFF ) { + /* Read interrupt controller to get the source */ + vector_number = intc->isr; + + /* Handle and the first interrupt that is set */ + uint8_t interrupt_status = 0; + for ( int i = 0; i < 32; i++ ) { + interrupt_status = vector_number >> i & 0x1; + if ( interrupt_status != 0 ) { + /* save current ILR */ + uint32_t interrupt_levels = intc->ilr; + /* set ILR to block out every interrupt less than or equal to priority of i */ + intc->ilr = 0xFFFFFFFF >> (32 - i); + bsp_interrupt_handler_dispatch( i ); + ack_interrupt( i ); + /* restore ILR */ + intc->ilr = interrupt_levels; + break; + } + } + } else { + vector_number = source; + + /* Fast interrupt mode. Handle interrupt. Ack happens automatically */ + bsp_interrupt_handler_dispatch( vector_number ); + } +} diff --git a/bsps/microblaze/microblaze_fpga/start/_exception_handler.S b/bsps/microblaze/microblaze_fpga/start/_exception_handler.S new file mode 100644 index 0000000000..1d96b694a7 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/_exception_handler.S @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +/* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + 1. Redistributions source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + 3. Neither the name of Xilinx nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS + IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + + .text + .globl _exception_handler # Exception Handler Label + .align 2 + + _exception_handler: +#ifndef __rtems__ + rtsd r17, 0 + nop +#else /* __rtems__ */ + /* Subtract stack frame */ + addik r1, r1, -52 + + swi r5, r1, 8 + + addi r5, r0, 0xFFFF + + braid _ISR_Handler + nop +#endif /* __rtems__ */ diff --git a/bsps/microblaze/microblaze_fpga/start/_hw_exception_handler.S b/bsps/microblaze/microblaze_fpga/start/_hw_exception_handler.S new file mode 100644 index 0000000000..30436a43e9 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/_hw_exception_handler.S @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +/* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + 1. Redistributions source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + 3. Neither the name of Xilinx nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS + IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + + .text + .globl _hw_exception_handler # HW Exception Handler Label + .align 2 + + _hw_exception_handler: +#ifndef __rtems__ + rtsd r17, 0 + nop +#else /* __rtems__ */ + /* Subtract stack frame */ + addik r1, r1, -52 + + swi r5, r1, 8 + + addi r5, r0, 0xFFFF + + braid _ISR_Handler + nop +#endif /* __rtems__ */ diff --git a/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S b/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S new file mode 100644 index 0000000000..b817503922 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +/* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + 1. Redistributions source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + 3. Neither the name of Xilinx nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS + IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + + .text + .globl _interrupt_handler # Interrupt Handler Label + .align 2 + + _interrupt_handler: +#ifndef __rtems__ + rtid r14, 0 + nop +#else /* __rtems__ */ + /* Subtract stack frame */ + addik r1, r1, -52 + + swi r5, r1, 8 + + /* Indicate unknown interrupt source */ + addi r5, r0, 0xFF + + braid _ISR_Handler + nop +#endif /* __rtems__ */ diff --git a/bsps/microblaze/microblaze_fpga/start/bspreset.c b/bsps/microblaze/microblaze_fpga/start/bspreset.c new file mode 100644 index 0000000000..6a7455f522 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/bspreset.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief BSP Reset + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +void bsp_reset( void ) +{ + __asm__ volatile ( + "brai 0xFFFFFFFFFFFFFFFF" + ); +} diff --git a/bsps/microblaze/microblaze_fpga/start/bspstart.c b/bsps/microblaze/microblaze_fpga/start/bspstart.c new file mode 100644 index 0000000000..0caf385b46 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/bspstart.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief BSP Startup + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +void bsp_start( void ) +{ + bsp_interrupt_initialize(); +} diff --git a/bsps/microblaze/microblaze_fpga/start/crtinit.S b/bsps/microblaze/microblaze_fpga/start/crtinit.S new file mode 100644 index 0000000000..a9779404b2 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/crtinit.S @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +/* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + 1. Redistributions source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + 3. Neither the name of Xilinx nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS + IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + .globl _crtinit + .align 2 + .ent _crtinit + .type _crtinit, @function +_crtinit: + addi r1, r1, -20 /* Save Link register */ + swi r15, r1, 0 + +#ifndef __rtems__ + addi r6, r0, __sbss_start /* clear SBSS */ + addi r7, r0, __sbss_end + rsub r18, r6, r7 + blei r18, .Lendsbss + +.Lloopsbss: + swi r0, r6, 0 + addi r6, r6, 4 + rsub r18, r6, r7 + bgti r18, .Lloopsbss +.Lendsbss: +#endif /* __rtems__ */ + +#ifndef __rtems__ + addi r6, r0, __bss_start /* clear BSS */ + addi r7, r0, __bss_end +#else + addi r6, r0, bsp_section_bss_begin + addi r7, r0, bsp_section_bss_end +#endif /* __rtems__ */ + rsub r18, r6, r7 + blei r18, .Lendbss +.Lloopbss: + swi r0, r6, 0 + addi r6, r6, 4 + rsub r18, r6, r7 + bgti r18, .Lloopbss +.Lendbss: + +#ifndef __rtems__ + brlid r15, _program_init /* Initialize the program */ + nop + + brlid r15, __init /* Invoke language initialization functions */ + nop +#endif /* __rtems__ */ + + addi r6, r0, 0 /* Initialize argc = 1 and argv = NULL and envp = NULL */ + addi r7, r0, 0 +#ifndef __rtems__ + brlid r15, main /* Execute the program */ +#else + brlid r15, boot_card +#endif /* __rtems__ */ + addi r5, r0, 0 + + addik r19, r3, 0 /* Save return value */ + +#ifndef __rtems__ + brlid r15, __fini /* Invoke language cleanup functions */ + nop + + brlid r15, _program_clean /* Cleanup the program */ + nop +#endif /* __rtems__ */ + + lw r15, r1, r0 /* Return back to CRT */ + + addik r3, r19, 0 /* Restore return value */ + rtsd r15, 8 + addi r1, r1, 20 + .end _crtinit diff --git a/bsps/microblaze/shared/cache/cache.c b/bsps/microblaze/shared/cache/cache.c new file mode 100644 index 0000000000..472f3c04f4 --- /dev/null +++ b/bsps/microblaze/shared/cache/cache.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze cache support + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include "../../../bsps/shared/cache/cacheimpl.h" diff --git a/bsps/microblaze/shared/dev/serial/uartlite.c b/bsps/microblaze/shared/dev/serial/uartlite.c new file mode 100644 index 0000000000..7387e22635 --- /dev/null +++ b/bsps/microblaze/shared/dev/serial/uartlite.c @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze AXI UART Lite support + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS +static void microblaze_uart_interrupt( void *arg ) +{ + rtems_termios_tty *tty = arg; + uart_lite_context *ctx = rtems_termios_get_device_context( tty ); + + while ( !XUartLite_IsReceiveEmpty( ctx->address ) ) { + char c = (char) XUartLite_ReadReg( ctx->address, XUL_RX_FIFO_OFFSET ); + rtems_termios_enqueue_raw_characters( tty, &c, 1 ); + } + + while ( ctx->transmitting && !XUartLite_IsTransmitEmpty( ctx ) ) { + rtems_termios_dequeue_characters( tty, 1 ); + } +} +#endif + +static bool uart_first_open( + struct rtems_termios_tty *tty, + rtems_termios_device_context *base, + struct termios *term, + rtems_libio_open_close_args_t *args +) +{ + uart_lite_context *ctx = (uart_lite_context *) base; +#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS + rtems_status_code sc; +#endif + + rtems_termios_set_initial_baud( tty, ctx->initial_baud ); + +#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS + XUartLite_EnableIntr( ctx->address ); + sc = rtems_interrupt_handler_install( + 1, + "UART", + RTEMS_INTERRUPT_SHARED, + microblaze_uart_interrupt, + tty + ); + if ( sc != RTEMS_SUCCESSFUL ) { + return false; + } +#endif + + return true; +} + +static void uart_last_close( + rtems_termios_tty *tty, + rtems_termios_device_context *base, + rtems_libio_open_close_args_t *args +) +{ +#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS + rtems_interrupt_handler_remove( 1, microblaze_uart_interrupt, tty ); +#endif +} + +#ifndef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS +static int uart_read_polled( rtems_termios_device_context *base ) +{ + uart_lite_context *ctx = (uart_lite_context *) base; + + if ( XUartLite_IsReceiveEmpty( ctx->address ) ) { + return -1; + } + + return XUartLite_ReadReg( ctx->address, XUL_RX_FIFO_OFFSET ); +} +#endif + +static void uart_write( + rtems_termios_device_context *base, + const char *s, + size_t n +) +{ + uart_lite_context *ctx = (uart_lite_context *) base; + +#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS + if ( n > 0 ) { + ctx->transmitting = true; + XUartLite_SendByte( ctx->address, s[0] ); + } else { + ctx->transmitting = false; + } +#else + size_t i = 0; + + for ( i = 0; i < n; ++i ) { + XUartLite_SendByte( ctx->address, s[i] ); + } +#endif +} + +const rtems_termios_device_handler microblaze_uart_fns = { + .first_open = uart_first_open, + .last_close = uart_last_close, + .write = uart_write, +#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS + .mode = TERMIOS_IRQ_DRIVEN +#else + .poll_read = uart_read_polled, + .mode = TERMIOS_POLLED +#endif +}; diff --git a/bsps/microblaze/shared/dev/serial/uartlite_l.c b/bsps/microblaze/shared/dev/serial/uartlite_l.c new file mode 100644 index 0000000000..5acbd6c505 --- /dev/null +++ b/bsps/microblaze/shared/dev/serial/uartlite_l.c @@ -0,0 +1,99 @@ +/****************************************************************************** +* Copyright (C) 2002 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/****************************************************************************/ +/** +* +* @file xuartlite_l.c +* @addtogroup uartlite_v3_5 +* @{ +* +* This file contains low-level driver functions that can be used to access the +* device. The user should refer to the hardware device specification for more +* details of the device operation. + +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b rpm  04/25/02 First release
+* 1.12a rpm  07/16/07 Fixed arg type for RecvByte
+* 2.00a ktn  10/20/09 The macros have been renamed to remove _m from the name.
+* 3.2   sk   11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
+*                     Changed the prototypes of XUartLite_SendByte,
+*                     XUartLite_RecvByte APIs.
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#ifndef __rtems__ +#include "xuartlite_l.h" +#else +#include +#endif /* __rtems__ */ + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + + +/************************** Variable Prototypes ******************************/ + + +/****************************************************************************/ +/** +* +* This functions sends a single byte using the UART. It is blocking in that it +* waits for the transmitter to become non-full before it writes the byte to +* the transmit register. +* +* @param BaseAddress is the base address of the device +* @param Data is the byte of data to send +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XUartLite_SendByte(UINTPTR BaseAddress, u8 Data) +{ + while (XUartLite_IsTransmitFull(BaseAddress)); + + XUartLite_WriteReg(BaseAddress, XUL_TX_FIFO_OFFSET, Data); +} + + +/****************************************************************************/ +/** +* +* This functions receives a single byte using the UART. It is blocking in that +* it waits for the receiver to become non-empty before it reads from the +* receive register. +* +* @param BaseAddress is the base address of the device +* +* @return The byte of data received. +* +* @note None. +* +******************************************************************************/ +u8 XUartLite_RecvByte(UINTPTR BaseAddress) +{ + while (XUartLite_IsReceiveEmpty(BaseAddress)); + + return (u8)XUartLite_ReadReg(BaseAddress, XUL_RX_FIFO_OFFSET); +} + +/** @} */ \ No newline at end of file diff --git a/bsps/microblaze/shared/start/start.S b/bsps/microblaze/shared/start/start.S new file mode 100644 index 0000000000..97250f9316 --- /dev/null +++ b/bsps/microblaze/shared/start/start.S @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +/* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + 1. Redistributions source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + 3. Neither the name of Xilinx nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS + IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + + XMD load *.elf error: + MicroBlaze Vector Map for standalone executables + + Address Vector type Label + ------- ----------- ------ + + # 0x00 # (-- IMM --) + # 0x04 # Reset _start1 + + # 0x08 # (-- IMM --) + # 0x0c # Software Exception _exception_handler + + # 0x10 # (-- IMM --) + # 0x14 # Hardware Interrupt _interrupt_handler + + # 0x18 # (-- IMM --) + # 0x1C # Breakpoint Exception (-- Don't Care --) + + # 0x20 # (-- IMM --) + # 0x24 # Hardware Exception _hw_exception_handler + +*/ + + + .globl _start + .section .vectors.reset, "ax" + .align 2 + .ent _start + .type _start, @function +_start: + brai _start1 + .end _start + + .section .vectors.sw_exception, "ax" + .align 2 +_vector_sw_exception: + brai _exception_handler + + .section .vectors.interrupt, "ax" + .align 2 +_vector_interrupt: + brai _interrupt_handler + + .section .vectors.hw_exception, "ax" + .align 2 +_vector_hw_exception: + brai _hw_exception_handler + + .section .text + .globl _start1 + .align 2 + .ent _start1 + .type _start1, @function +_start1: + //la r13, r0, _SDA_BASE_ /* Set the Small Data Anchors and the stack pointer */ + //la r2, r0, _SDA2_BASE_ + la r1, r0, _ISR_Stack_area_end-16 /* 16 bytes (4 words are needed by crtinit for args and link reg */ + + brlid r15, _crtinit /* Initialize BSS and run program */ + nop + +#ifndef __rtems__ + brlid r15, exit /* Call exit with the return value of main */ + addik r5, r3, 0 +#endif /* __rtems__ */ + + /* Control does not reach here */ + .end _start1 + +#ifndef __rtems__ +/* + _exit + Our simple _exit +*/ + .globl _exit + .align 2 + .ent _exit + .type _exit, @function +_exit: + bri 0 + .end _exit +#endif /* __rtems__ */ -- cgit v1.2.3