From b76f382bd427f670ce2fdc2c0fe9270087d3915d Mon Sep 17 00:00:00 2001
From: Kinsey Moore <kinsey.moore@oarcorp.com>
Date: Tue, 3 Jan 2023 10:12:48 -0600
Subject: bsps/xil: Use the LP64 header for ILP32

Xilinx's upstream ILP32 xil_cache.h header is out of date and broken.
This provides a copy of the LP64 header in place of the ILP32 header
since the LP64 header includes all the correct types to work with either
data model.
---
 bsps/include/xil/arm/ARMv8/32bit/xil_cache.h | 35 ++++++++++++++++++++--------
 1 file changed, 25 insertions(+), 10 deletions(-)

(limited to 'bsps')

diff --git a/bsps/include/xil/arm/ARMv8/32bit/xil_cache.h b/bsps/include/xil/arm/ARMv8/32bit/xil_cache.h
index 0fe994b093..b878d05299 100644
--- a/bsps/include/xil/arm/ARMv8/32bit/xil_cache.h
+++ b/bsps/include/xil/arm/ARMv8/32bit/xil_cache.h
@@ -1,5 +1,5 @@
 /******************************************************************************
-* Copyright (c) 2015 - 2020 Xilinx, Inc.  All rights reserved.
+* Copyright (c) 2014 - 2021 Xilinx, Inc.  All rights reserved.
 * SPDX-License-Identifier: MIT
 ******************************************************************************/
 
@@ -8,7 +8,7 @@
 *
 * @file xil_cache.h
 *
-* @addtogroup a53_32_cache_apis Cortex A53 32bit Processor Cache Functions
+* @addtogroup a53_64_cache_apis Cortex A53 64bit Processor Cache Functions
 *
 * Cache functions provide access to cache related operations such as flush
 * and invalidate for instruction and data caches. It gives option to perform
@@ -22,7 +22,7 @@
 *
 * Ver   Who  Date     Changes
 * ----- ---- -------- -----------------------------------------------
-* 5.2	pkp  28/05/15 First release
+* 5.00 	pkp  05/29/14 First release
 * </pre>
 *
 ******************************************************************************/
@@ -35,21 +35,36 @@
 extern "C" {
 #endif
 
+/**
+ *@cond nocomments
+ */
+
+/************************** Constant Definitions *****************************/
+#define L1_DATA_PREFETCH_CONTROL_MASK  0xE000
+#define L1_DATA_PREFETCH_CONTROL_SHIFT  13
+
+/**
+ *@endcond
+ */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define Xil_DCacheFlushRange Xil_DCacheInvalidateRange
+
+/************************** Function Prototypes ******************************/
 void Xil_DCacheEnable(void);
 void Xil_DCacheDisable(void);
 void Xil_DCacheInvalidate(void);
-void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
+void Xil_DCacheInvalidateRange(INTPTR adr, INTPTR len);
+void Xil_DCacheInvalidateLine(INTPTR adr);
 void Xil_DCacheFlush(void);
-void Xil_DCacheFlushRange(INTPTR adr, u32 len);
-void Xil_DCacheInvalidateLine(u32 adr);
-void Xil_DCacheFlushLine(u32 adr);
+void Xil_DCacheFlushLine(INTPTR adr);
 
-void Xil_ICacheInvalidateLine(u32 adr);
 void Xil_ICacheEnable(void);
 void Xil_ICacheDisable(void);
 void Xil_ICacheInvalidate(void);
-void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
-
+void Xil_ICacheInvalidateRange(INTPTR adr, INTPTR len);
+void Xil_ICacheInvalidateLine(INTPTR adr);
+void Xil_ConfigureL1Prefetch(u8 num);
 #ifdef __cplusplus
 }
 #endif
-- 
cgit v1.2.3