From 76c6caad52244ab9a14151620a80ff0f71035b6c Mon Sep 17 00:00:00 2001
From: Gedare Bloom <gedare@rtems.org>
Date: Tue, 22 Jun 2021 20:01:17 -0600
Subject: bsps/aarch64: add non-secure mode and versal support

---
 bsps/aarch64/shared/start/start.S | 18 ++++++++++++++++--
 bsps/shared/dev/irq/arm-gicv3.c   | 23 +++++++++++++++++++++--
 2 files changed, 37 insertions(+), 4 deletions(-)

(limited to 'bsps')

diff --git a/bsps/aarch64/shared/start/start.S b/bsps/aarch64/shared/start/start.S
index d0d9c2160a..338c51f7d0 100644
--- a/bsps/aarch64/shared/start/start.S
+++ b/bsps/aarch64/shared/start/start.S
@@ -98,7 +98,7 @@ _start:
 #endif
 	msr SCTLR_EL1, x0
 
-#ifdef BSP_START_IN_MON_SUPPORT
+#ifdef BSP_START_IN_EL3_MONITOR_MODE_SUPPORT
 	/* Drop from EL3 to EL2 */
 
   /* Initialize HCR_EL2 and SCTLR_EL2 */
@@ -108,21 +108,35 @@ _start:
   mrs x0, SCR_EL3
   /* Set EL2 to AArch64 */
   orr x0, x0, #(1<<10)
+#ifdef AARCH64_IS_NONSECURE
   /* Set EL1 to NS */
   orr x0, x0, #1
+#endif
   msr SCR_EL3, x0
 
   /* set EL2h mode for eret */
+#ifdef AARCH64_IS_NONSECURE
   mov x0, #0b01001
+#else
+  mov x0, #0b00101
+#endif
+
   msr SPSR_EL3, x0
 
   /* Set EL2 entry point */
+#ifdef AARCH64_IS_NONSECURE
   adr x0, _el2_start
+#else
+  adr x0, _el1_start
+#endif
   msr ELR_EL3, x0
   eret
 #endif
 
-#if defined(BSP_START_IN_HYP_SUPPORT) || defined(BSP_START_IN_MON_SUPPORT)
+#if defined(BSP_START_IN_HYP_SUPPORT) || \
+    ( defined(BSP_START_IN_EL3_MONITOR_MODE_SUPPORT) && \
+      defined(AARCH64_IS_NONSECURE) \
+    )
 _el2_start:
 	/* Drop from EL2 to EL1 */
 
diff --git a/bsps/shared/dev/irq/arm-gicv3.c b/bsps/shared/dev/irq/arm-gicv3.c
index 7a0d42b27b..d216f4f5f7 100644
--- a/bsps/shared/dev/irq/arm-gicv3.c
+++ b/bsps/shared/dev/irq/arm-gicv3.c
@@ -175,6 +175,15 @@ void bsp_interrupt_vector_enable(rtems_vector_number vector)
   } else {
     volatile gic_sgi_ppi *sgi_ppi =
       gicv3_get_sgi_ppi(_SMP_Get_current_processor());
+    /* Set interrupt group to 1 in the current security mode */
+#if defined(AARCH64_IS_NONSECURE)
+    sgi_ppi->icspigrpr[0] |= 1 << (vector % 32);
+    sgi_ppi->icspigrpmodr[0] &= ~(1 << (vector % 32));
+#else
+    sgi_ppi->icspigrpr[0] &= ~(1 << (vector % 32));
+    sgi_ppi->icspigrpmodr[0] |= 1 << (vector % 32);
+#endif
+    /* Set enable */
     sgi_ppi->icspiser[0] = 1 << (vector % 32);
   }
 }
@@ -217,10 +226,15 @@ static void gicv3_init_cpu_interface(void)
   waker &= ~waker_mask;
   redist->icrwaker = waker;
 
-  /* Set interrupt group to 1NS for SGI/PPI interrupts routed through the redistributor */
   volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(cpu_index);
+  /* Set interrupt group to 1 in the current security mode */
+#if defined(AARCH64_IS_NONSECURE)
   sgi_ppi->icspigrpr[0] = 0xffffffff;
   sgi_ppi->icspigrpmodr[0] = 0;
+#else
+  sgi_ppi->icspigrpr[0] = 0x0;
+  sgi_ppi->icspigrpmodr[0] = 0xffffffff;
+#endif
   for (int id = 0; id < 32; id++) {
     sgi_ppi->icspiprior[id] = PRIORITY_DEFAULT;
   }
@@ -247,9 +261,14 @@ rtems_status_code bsp_interrupt_facility_initialize(void)
     /* Disable all interrupts */
     dist->icdicer[id / 32] = 0xffffffff;
 
-    /* Set interrupt group to 1NS for all interrupts */
+    /* Set interrupt group to 1 in the current security mode */
+#if defined(AARCH64_IS_NONSECURE)
     dist->icdigr[id / 32] = 0xffffffff;
     dist->icdigmr[id / 32] = 0;
+#else
+    dist->icdigr[id / 32] = 0;
+    dist->icdigmr[id / 32] = 0xffffffff;
+#endif
   }
 
   for (id = 0; id < id_count; ++id) {
-- 
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