From 6f5d88a4695d2f0886fe03e28001926d775938c7 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Fri, 22 Jun 2018 07:06:57 +0200 Subject: bsp/riscv_generic: Rename to "riscv" Update #3433. --- bsps/riscv/riscv/btimer/btimer.c | 70 +++++ bsps/riscv/riscv/clock/clockdrv.c | 122 ++++++++ bsps/riscv/riscv/config/rv32i.cfg | 9 + bsps/riscv/riscv/config/rv32iac.cfg | 9 + bsps/riscv/riscv/config/rv32im.cfg | 9 + bsps/riscv/riscv/config/rv32imac.cfg | 9 + bsps/riscv/riscv/config/rv32imafc.cfg | 9 + bsps/riscv/riscv/config/rv64imac.cfg | 9 + bsps/riscv/riscv/config/rv64imafdc.cfg | 9 + bsps/riscv/riscv/console/console-io.c | 178 +++++++++++ bsps/riscv/riscv/headers.am | 10 + bsps/riscv/riscv/include/bsp.h | 73 +++++ bsps/riscv/riscv/include/bsp/irq.h | 49 +++ bsps/riscv/riscv/include/tm27.h | 1 + bsps/riscv/riscv/irq/irq.c | 60 ++++ bsps/riscv/riscv/start/bsp_fatal_halt.c | 35 +++ bsps/riscv/riscv/start/bsp_specs | 9 + bsps/riscv/riscv/start/linkcmds | 46 +++ bsps/riscv/riscv/start/linkcmds.base | 385 ++++++++++++++++++++++++ bsps/riscv/riscv/start/start.S | 118 ++++++++ bsps/riscv/riscv_generic/btimer/btimer.c | 70 ----- bsps/riscv/riscv_generic/clock/clockdrv.c | 122 -------- bsps/riscv/riscv_generic/config/rv32i.cfg | 9 - bsps/riscv/riscv_generic/config/rv32iac.cfg | 9 - bsps/riscv/riscv_generic/config/rv32im.cfg | 9 - bsps/riscv/riscv_generic/config/rv32imac.cfg | 9 - bsps/riscv/riscv_generic/config/rv32imafc.cfg | 9 - bsps/riscv/riscv_generic/config/rv64imac.cfg | 9 - bsps/riscv/riscv_generic/config/rv64imafdc.cfg | 9 - bsps/riscv/riscv_generic/console/console-io.c | 178 ----------- bsps/riscv/riscv_generic/headers.am | 10 - bsps/riscv/riscv_generic/include/bsp.h | 73 ----- bsps/riscv/riscv_generic/include/bsp/irq.h | 49 --- bsps/riscv/riscv_generic/include/tm27.h | 1 - bsps/riscv/riscv_generic/irq/irq.c | 60 ---- bsps/riscv/riscv_generic/start/bsp_fatal_halt.c | 35 --- bsps/riscv/riscv_generic/start/bsp_specs | 9 - bsps/riscv/riscv_generic/start/linkcmds | 46 --- bsps/riscv/riscv_generic/start/linkcmds.base | 385 ------------------------ bsps/riscv/riscv_generic/start/start.S | 118 -------- 40 files changed, 1219 insertions(+), 1219 deletions(-) create mode 100644 bsps/riscv/riscv/btimer/btimer.c create mode 100644 bsps/riscv/riscv/clock/clockdrv.c create mode 100644 bsps/riscv/riscv/config/rv32i.cfg create mode 100644 bsps/riscv/riscv/config/rv32iac.cfg create mode 100644 bsps/riscv/riscv/config/rv32im.cfg create mode 100644 bsps/riscv/riscv/config/rv32imac.cfg create mode 100644 bsps/riscv/riscv/config/rv32imafc.cfg create mode 100644 bsps/riscv/riscv/config/rv64imac.cfg create mode 100644 bsps/riscv/riscv/config/rv64imafdc.cfg create mode 100644 bsps/riscv/riscv/console/console-io.c create mode 100644 bsps/riscv/riscv/headers.am create mode 100644 bsps/riscv/riscv/include/bsp.h create mode 100644 bsps/riscv/riscv/include/bsp/irq.h create mode 100644 bsps/riscv/riscv/include/tm27.h create mode 100644 bsps/riscv/riscv/irq/irq.c create mode 100644 bsps/riscv/riscv/start/bsp_fatal_halt.c create mode 100644 bsps/riscv/riscv/start/bsp_specs create mode 100644 bsps/riscv/riscv/start/linkcmds create mode 100644 bsps/riscv/riscv/start/linkcmds.base create mode 100644 bsps/riscv/riscv/start/start.S delete mode 100644 bsps/riscv/riscv_generic/btimer/btimer.c delete mode 100644 bsps/riscv/riscv_generic/clock/clockdrv.c delete mode 100644 bsps/riscv/riscv_generic/config/rv32i.cfg delete mode 100644 bsps/riscv/riscv_generic/config/rv32iac.cfg delete mode 100644 bsps/riscv/riscv_generic/config/rv32im.cfg delete mode 100644 bsps/riscv/riscv_generic/config/rv32imac.cfg delete mode 100644 bsps/riscv/riscv_generic/config/rv32imafc.cfg delete mode 100644 bsps/riscv/riscv_generic/config/rv64imac.cfg delete mode 100644 bsps/riscv/riscv_generic/config/rv64imafdc.cfg delete mode 100644 bsps/riscv/riscv_generic/console/console-io.c delete mode 100644 bsps/riscv/riscv_generic/headers.am delete mode 100644 bsps/riscv/riscv_generic/include/bsp.h delete mode 100644 bsps/riscv/riscv_generic/include/bsp/irq.h delete mode 100644 bsps/riscv/riscv_generic/include/tm27.h delete mode 100644 bsps/riscv/riscv_generic/irq/irq.c delete mode 100644 bsps/riscv/riscv_generic/start/bsp_fatal_halt.c delete mode 100644 bsps/riscv/riscv_generic/start/bsp_specs delete mode 100644 bsps/riscv/riscv_generic/start/linkcmds delete mode 100644 bsps/riscv/riscv_generic/start/linkcmds.base delete mode 100644 bsps/riscv/riscv_generic/start/start.S (limited to 'bsps') diff --git a/bsps/riscv/riscv/btimer/btimer.c b/bsps/riscv/riscv/btimer/btimer.c new file mode 100644 index 0000000000..4dd3193685 --- /dev/null +++ b/bsps/riscv/riscv/btimer/btimer.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2015 University of York. + * Hesham Almatary + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +#include +#include +#include + +extern char bsp_start_vector_table_begin[]; + +bool benchmark_timer_find_average_overhead; + +static void benchmark_timer1_interrupt_handler(void) +{ +} + +/* Start eCore tiemr 1 usef for profiling and timing analysis */ +void benchmark_timer_initialize( void ) +{ + /* Install interrupt handler for timer 1 */ +} + +/* + * The following controls the behavior of benchmark_timer_read(). + * + * AVG_OVEREHAD is the overhead for starting and stopping the timer. It + * is usually deducted from the number returned. + * + * LEAST_VALID is the lowest number this routine should trust. Numbers + * below this are "noise" and zero is returned. + */ + +#define AVG_OVERHEAD 0 /* It typically takes X.X microseconds */ +/* (Y countdowns) to start/stop the timer. */ +/* This value is in microseconds. */ +#define LEAST_VALID 1 /* Don't trust a clicks value lower than this */ + +benchmark_timer_t benchmark_timer_read( void ) +{ +} + +void benchmark_timer_disable_subtracting_average_overhead( + bool find_flag +) +{ + benchmark_timer_find_average_overhead = find_flag; +} diff --git a/bsps/riscv/riscv/clock/clockdrv.c b/bsps/riscv/riscv/clock/clockdrv.c new file mode 100644 index 0000000000..340e158489 --- /dev/null +++ b/bsps/riscv/riscv/clock/clockdrv.c @@ -0,0 +1,122 @@ +/** + * @file + * + * @ingroup bsp_clock + * + * @brief riscv clock support. + */ + +/* + * riscv_generic Clock driver + * + * COPYRIGHT (c) 2015 Hesham Alatary + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +/* The number of clock cycles before generating a tick timer interrupt. */ +#define TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT 1000 +#define RISCV_CLOCK_CYCLE_TIME_NANOSECONDS 1 + +static struct timecounter riscv_generic_tc; + +/* CPU counter */ +static CPU_Counter_ticks cpu_counter_ticks; + +/* This prototype is added here to Avoid warnings */ +void Clock_isr(void *arg); + +static void riscv_generic_clock_at_tick(void) +{ + REG(MTIME_MM) = 0; + REG(MTIMECMP_MM) = TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT; + + cpu_counter_ticks += TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT * 10000; +} + +static void riscv_generic_clock_handler_install(proc_ptr new_isr) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + _CPU_ISR_install_vector(RISCV_MACHINE_TIMER_INTERRUPT, + new_isr, + NULL); + + if (sc != RTEMS_SUCCESSFUL) { + rtems_fatal_error_occurred(0xdeadbeef); + } +} + +static uint32_t riscv_generic_get_timecount(struct timecounter *tc) +{ + uint32_t ticks_since_last_timer_interrupt = REG(MTIME_MM); + + return cpu_counter_ticks + ticks_since_last_timer_interrupt; +} + +CPU_Counter_ticks _CPU_Counter_read(void) +{ + return riscv_generic_get_timecount(NULL); +} + +static void riscv_generic_clock_initialize(void) +{ + uint32_t mtimecmp = TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT; + uint64_t frequency = (1000000000 / RISCV_CLOCK_CYCLE_TIME_NANOSECONDS); + + REG(MTIME_MM) = 0; + REG(MTIMECMP_MM) = TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT; + + /* Enable mtimer interrupts */ + set_csr(mie, MIP_MTIP); + set_csr(mip, MIP_MTIP); + + /* Initialize timecounter */ + riscv_generic_tc.tc_get_timecount = riscv_generic_get_timecount; + riscv_generic_tc.tc_counter_mask = 0xffffffff; + riscv_generic_tc.tc_frequency = frequency; + riscv_generic_tc.tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER; + rtems_timecounter_install(&riscv_generic_tc); +} + +CPU_Counter_ticks _CPU_Counter_difference( + CPU_Counter_ticks second, + CPU_Counter_ticks first +) +{ + return second - first; +} + +#define Clock_driver_support_at_tick() riscv_generic_clock_at_tick() + +#define Clock_driver_support_initialize_hardware() riscv_generic_clock_initialize() + +#define Clock_driver_support_install_isr(isr) \ + riscv_generic_clock_handler_install(isr) + +#include "../../../shared/dev/clock/clockimpl.h" diff --git a/bsps/riscv/riscv/config/rv32i.cfg b/bsps/riscv/riscv/config/rv32i.cfg new file mode 100644 index 0000000000..a394590dc2 --- /dev/null +++ b/bsps/riscv/riscv/config/rv32i.cfg @@ -0,0 +1,9 @@ +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU = riscv + +CPU_CFLAGS = -march=rv32i -mabi=ilp32 + +LDFLAGS = -Wl,--gc-sections + +CFLAGS_OPTIMIZE_V ?= -O2 -g -ffunction-sections -fdata-sections diff --git a/bsps/riscv/riscv/config/rv32iac.cfg b/bsps/riscv/riscv/config/rv32iac.cfg new file mode 100644 index 0000000000..369f2c441d --- /dev/null +++ b/bsps/riscv/riscv/config/rv32iac.cfg @@ -0,0 +1,9 @@ +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU = riscv + +CPU_CFLAGS = -march=rv32iac -mabi=ilp32 + +LDFLAGS = -Wl,--gc-sections + +CFLAGS_OPTIMIZE_V ?= -O2 -g -ffunction-sections -fdata-sections diff --git a/bsps/riscv/riscv/config/rv32im.cfg b/bsps/riscv/riscv/config/rv32im.cfg new file mode 100644 index 0000000000..46dfdad09c --- /dev/null +++ b/bsps/riscv/riscv/config/rv32im.cfg @@ -0,0 +1,9 @@ +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU = riscv + +CPU_CFLAGS = -march=rv32im -mabi=ilp32 + +LDFLAGS = -Wl,--gc-sections + +CFLAGS_OPTIMIZE_V ?= -O2 -g -ffunction-sections -fdata-sections diff --git a/bsps/riscv/riscv/config/rv32imac.cfg b/bsps/riscv/riscv/config/rv32imac.cfg new file mode 100644 index 0000000000..e19e431b53 --- /dev/null +++ b/bsps/riscv/riscv/config/rv32imac.cfg @@ -0,0 +1,9 @@ +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU = riscv + +CPU_CFLAGS = -march=rv32imac -mabi=ilp32 + +LDFLAGS = -Wl,--gc-sections + +CFLAGS_OPTIMIZE_V ?= -O2 -g -ffunction-sections -fdata-sections diff --git a/bsps/riscv/riscv/config/rv32imafc.cfg b/bsps/riscv/riscv/config/rv32imafc.cfg new file mode 100644 index 0000000000..bd4a0cacbe --- /dev/null +++ b/bsps/riscv/riscv/config/rv32imafc.cfg @@ -0,0 +1,9 @@ +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU = riscv + +CPU_CFLAGS = -march=rv32imafc -mabi=ilp32f + +LDFLAGS = -Wl,--gc-sections + +CFLAGS_OPTIMIZE_V ?= -O2 -g -ffunction-sections -fdata-sections diff --git a/bsps/riscv/riscv/config/rv64imac.cfg b/bsps/riscv/riscv/config/rv64imac.cfg new file mode 100644 index 0000000000..e5df5995ac --- /dev/null +++ b/bsps/riscv/riscv/config/rv64imac.cfg @@ -0,0 +1,9 @@ +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU = riscv + +CPU_CFLAGS = -march=rv64imac -mabi=lp64 + +LDFLAGS = -Wl,--gc-sections + +CFLAGS_OPTIMIZE_V ?= -O2 -g -ffunction-sections -fdata-sections diff --git a/bsps/riscv/riscv/config/rv64imafdc.cfg b/bsps/riscv/riscv/config/rv64imafdc.cfg new file mode 100644 index 0000000000..09caf7adbf --- /dev/null +++ b/bsps/riscv/riscv/config/rv64imafdc.cfg @@ -0,0 +1,9 @@ +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU = riscv + +CPU_CFLAGS = -march=rv64imafdc -mabi=lp64d + +LDFLAGS = -Wl,--gc-sections + +CFLAGS_OPTIMIZE_V ?= -O2 -g -ffunction-sections -fdata-sections diff --git a/bsps/riscv/riscv/console/console-io.c b/bsps/riscv/riscv/console/console-io.c new file mode 100644 index 0000000000..a300e11753 --- /dev/null +++ b/bsps/riscv/riscv/console/console-io.c @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2015 University of York. + * Hesham Almatary + * + * Copyright (c) 2013, The Regents of the University of California (Regents). + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +/* Most of the code below is copied from riscv-pk project */ +# define TOHOST_CMD(dev, cmd, payload) \ + (((uint64_t)(dev) << 56) | ((uint64_t)(cmd) << 48) | (uint64_t)(payload)) + +#define FROMHOST_DEV(fromhost_value) ((uint64_t)(fromhost_value) >> 56) +#define FROMHOST_CMD(fromhost_value) ((uint64_t)(fromhost_value) << 8 >> 56) +#define FROMHOST_DATA(fromhost_value) ((uint64_t)(fromhost_value) << 16 >> 16) + +volatile uint64_t tohost __attribute__((section(".htif"))); +volatile uint64_t fromhost __attribute__((section(".htif"))); +volatile uint64_t riscv_fill_up_htif_section[510] __attribute__((section(".htif"))); +volatile int htif_console_buf; + +static void __check_fromhost() +{ + uint64_t fh = fromhost; + if (!fh) { + return; + } + fromhost = 0; + + // this should be from the console + assert(FROMHOST_DEV(fh) == 1); + switch (FROMHOST_CMD(fh)) { + case 0: + htif_console_buf = 1 + (uint8_t)FROMHOST_DATA(fh); + break; + case 1: + break; + default: + assert(0); + } +} + +static void __set_tohost(uintptr_t dev, uintptr_t cmd, uintptr_t data) +{ + while (tohost) { + __check_fromhost(); + } + tohost = TOHOST_CMD(dev, cmd, data); +} + +int htif_console_getchar() +{ + __check_fromhost(); + int ch = htif_console_buf; + if (ch >= 0) { + htif_console_buf = -1; + __set_tohost(1, 0, 0); + } + + return ch - 1; +} + +static void do_tohost_fromhost(uintptr_t dev, uintptr_t cmd, uintptr_t data) +{ + __set_tohost(dev, cmd, data); + + while (1) { + uint64_t fh = fromhost; + if (fh) { + if (FROMHOST_DEV(fh) == dev && FROMHOST_CMD(fh) == cmd) { + fromhost = 0; + break; + } + __check_fromhost(); + } + } +} + +void htif_console_putchar(uint8_t ch) +{ + __set_tohost(1, 1, ch); +} + +void htif_poweroff() +{ + while (1) { + fromhost = 0; + tohost = 1; + } +} + +void console_initialize_hardware(void) +{ + /* Do nothing */ +} + +static void outbyte_console(char ch) +{ + htif_console_putchar(ch); +} + +static char inbyte_console(void) +{ + return htif_console_getchar(); +} + +/* + * console_outbyte_polled + * + * This routine transmits a character using polling. + */ +void console_outbyte_polled( + int port, + char ch +) +{ + outbyte_console( ch ); +} + +/* + * console_inbyte_nonblocking + * + * This routine polls for a character. + */ + +int console_inbyte_nonblocking(int port) +{ + char c; + + c = inbyte_console(); + if (!c) { + return -1; + } + return (int) c; +} + +/* + * To support printk + */ + +#include + +static void RISCV_output_char(char c) +{ + console_outbyte_polled( 0, c ); +} + +BSP_output_char_function_type BSP_output_char = RISCV_output_char; +BSP_polling_getchar_function_type BSP_poll_char = + (void *)console_inbyte_nonblocking; diff --git a/bsps/riscv/riscv/headers.am b/bsps/riscv/riscv/headers.am new file mode 100644 index 0000000000..ce637f40d1 --- /dev/null +++ b/bsps/riscv/riscv/headers.am @@ -0,0 +1,10 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/riscv/riscv/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/riscv/riscv/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/riscv/riscv/include/bsp/irq.h diff --git a/bsps/riscv/riscv/include/bsp.h b/bsps/riscv/riscv/include/bsp.h new file mode 100644 index 0000000000..79f359ac34 --- /dev/null +++ b/bsps/riscv/riscv/include/bsp.h @@ -0,0 +1,73 @@ +/* + * + * Copyright (c) 2015 University of York. + * Hesham Almatary + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef LIBBSP_RISCV_GENERIC_H +#define LIBBSP_RISCV_GENERIC_H + +#include +#include +#include + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup riscv_generic Register Definitions + * + * @ingroup riscv_generic + * + * @brief Shared register definitions for RISC-V systems. + * + * @{ + */ + +/** + * @name Register Macros + * + * @{ + */ + +#define REG(x) (*((volatile unsigned long *) (x))) +#define BIT(n) (1 << (n)) + +#define MTIME_MM 0x000000000200bff8 +#define MTIMECMP_MM 0x0000000002004000 + +#ifdef __cplusplus +} +#endif + +#endif /* LIBBSP_RISCV_GENERIC_H */ diff --git a/bsps/riscv/riscv/include/bsp/irq.h b/bsps/riscv/riscv/include/bsp/irq.h new file mode 100644 index 0000000000..d7ee45b378 --- /dev/null +++ b/bsps/riscv/riscv/include/bsp/irq.h @@ -0,0 +1,49 @@ +/** + * @file + * + * @ingroup RISCV_IRQ + * + * @brief Interrupt definitions. + */ + +/* + * + * Copyright (c) 2015 University of York. + * Hesham Almatary + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef LIBBSP_GENERIC_RISCV_IRQ_H +#define LIBBSP_GENERIC_RISCV_IRQ_H + +#ifndef ASM + +#include +#include +#include + +#define BSP_INTERRUPT_VECTOR_MIN 0x0 +#define BSP_INTERRUPT_VECTOR_MAX 0x24 + +#endif /* ASM */ +#endif /* LIBBSP_GENERIC_RISCV_IRQ_H */ diff --git a/bsps/riscv/riscv/include/tm27.h b/bsps/riscv/riscv/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/riscv/riscv/include/tm27.h @@ -0,0 +1 @@ +#include diff --git a/bsps/riscv/riscv/irq/irq.c b/bsps/riscv/riscv/irq/irq.c new file mode 100644 index 0000000000..8090dcea98 --- /dev/null +++ b/bsps/riscv/riscv/irq/irq.c @@ -0,0 +1,60 @@ +/** + * @file + * + * @ingroup riscv_interrupt + * + * @brief Interrupt support. + */ + +/* + * RISCV CPU Dependent Source + * + * Copyright (c) 2015 University of York. + * Hesham Almatary + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +#include + +/* Almost all of the jobs that the following functions should + * do are implemented in cpukit + */ + +void bsp_interrupt_handler_default(rtems_vector_number vector) +{ + printk("spurious interrupt: %u\n", vector); +} + +rtems_status_code bsp_interrupt_facility_initialize() +{ + return RTEMS_NOT_IMPLEMENTED; +} + +void bsp_interrupt_vector_enable(rtems_vector_number vector) +{ +} + +void bsp_interrupt_vector_disable(rtems_vector_number vector) +{ +} diff --git a/bsps/riscv/riscv/start/bsp_fatal_halt.c b/bsps/riscv/riscv/start/bsp_fatal_halt.c new file mode 100644 index 0000000000..64c307990b --- /dev/null +++ b/bsps/riscv/riscv/start/bsp_fatal_halt.c @@ -0,0 +1,35 @@ +/* @ingroup riscv_generic + * @brief riscv_generic BSP Fatal_halt handler. + * + * Copyright (c) 2015 University of York. + * Hesham Almatary + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include + +/* Send a power-off signal to the host */ +void _CPU_Fatal_halt(uint32_t source, uint32_t error) +{ + htif_poweroff(); +} diff --git a/bsps/riscv/riscv/start/bsp_specs b/bsps/riscv/riscv/start/bsp_specs new file mode 100644 index 0000000000..87638cc027 --- /dev/null +++ b/bsps/riscv/riscv/start/bsp_specs @@ -0,0 +1,9 @@ +%rename endfile old_endfile +%rename startfile old_startfile + +*startfile: +%{!qrtems: %(old_startfile)} \ +%{!nostdlib: %{qrtems: crti.o%s crtbegin.o%s}} + +*endfile: +%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtn.o%s} diff --git a/bsps/riscv/riscv/start/linkcmds b/bsps/riscv/riscv/start/linkcmds new file mode 100644 index 0000000000..7bcf657341 --- /dev/null +++ b/bsps/riscv/riscv/start/linkcmds @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2015 University of York. + * Hesham ALMatary + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +MEMORY +{ + RAM : ORIGIN = 0x0000000010000000, LENGTH = 0x10000000 +} + +REGION_ALIAS ("REGION_START", RAM); +REGION_ALIAS ("REGION_TEXT", RAM); +REGION_ALIAS ("REGION_TEXT_LOAD", RAM); +REGION_ALIAS ("REGION_FAST_TEXT", RAM); +REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM); +REGION_ALIAS ("REGION_RODATA", RAM); +REGION_ALIAS ("REGION_RODATA_LOAD", RAM); +REGION_ALIAS ("REGION_DATA", RAM); +REGION_ALIAS ("REGION_DATA_LOAD", RAM); +REGION_ALIAS ("REGION_FAST_DATA", RAM); +REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM); +REGION_ALIAS ("REGION_RTEMSSTACK", RAM); +REGION_ALIAS ("REGION_WORK", RAM); + +INCLUDE linkcmds.base diff --git a/bsps/riscv/riscv/start/linkcmds.base b/bsps/riscv/riscv/start/linkcmds.base new file mode 100644 index 0000000000..7d889ab38c --- /dev/null +++ b/bsps/riscv/riscv/start/linkcmds.base @@ -0,0 +1,385 @@ +/* Copyright (C) 2014-2018 Free Software Foundation, Inc. + Copying and distribution of this script, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. */ + +/* + * Copyright (c) 2018 embedded brains GmbH. + * + * Copyright (c) 2015 University of York. + * Hesham ALMatary + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +OUTPUT_ARCH(riscv) +ENTRY(_start) +STARTUP(start.o) + +bsp_section_robarrier_align = DEFINED (bsp_section_robarrier_align) ? bsp_section_robarrier_align : 1; +bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_section_rwbarrier_align : 1; + +MEMORY { + UNEXPECTED_SECTIONS : ORIGIN = 0xffffffff, LENGTH = 0 +} + +SECTIONS { + .start : ALIGN_WITH_INPUT { + bsp_section_start_begin = .; + KEEP (*(.bsp_start_text)) + KEEP (*(.bsp_start_data)) + bsp_section_start_end = .; + } > REGION_START AT > REGION_START + bsp_section_start_size = bsp_section_start_end - bsp_section_start_begin; + + .text : ALIGN_WITH_INPUT { + bsp_section_text_begin = .; + *(.text.unlikely .text.*_unlikely .text.unlikely.*) + *(.text.exit .text.exit.*) + *(.text.startup .text.startup.*) + *(.text.hot .text.hot.*) + *(.text .stub .text.* .gnu.linkonce.t.*) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + } > REGION_TEXT AT > REGION_TEXT_LOAD + .init : ALIGN_WITH_INPUT { + KEEP (*(SORT_NONE(.init))) + } > REGION_TEXT AT > REGION_TEXT_LOAD + .fini : ALIGN_WITH_INPUT { + KEEP (*(SORT_NONE(.fini))) + bsp_section_text_end = .; + } > REGION_TEXT AT > REGION_TEXT_LOAD + bsp_section_text_size = bsp_section_text_end - bsp_section_text_begin; + bsp_section_text_load_begin = LOADADDR (.text); + bsp_section_text_load_end = bsp_section_text_load_begin + bsp_section_text_size; + + .robarrier : ALIGN_WITH_INPUT { + . = ALIGN (bsp_section_robarrier_align); + } > REGION_RODATA AT > REGION_RODATA + + .rodata : ALIGN_WITH_INPUT { + bsp_section_rodata_begin = .; + *(.rodata .rodata.* .gnu.linkonce.r.*) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .rodata1 : ALIGN_WITH_INPUT { + *(.rodata1) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .sdata2 : ALIGN_WITH_INPUT { + *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .sbss2 : ALIGN_WITH_INPUT { + *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .eh_frame_hdr : ALIGN_WITH_INPUT { + *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .eh_frame : ALIGN_WITH_INPUT { + KEEP (*(.eh_frame)) *(.eh_frame.*) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .gcc_except_table : ALIGN_WITH_INPUT { + *(.gcc_except_table .gcc_except_table.*) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .gnu_extab : ALIGN_WITH_INPUT { + *(.gnu_extab*) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .tdata : ALIGN_WITH_INPUT { + _TLS_Data_begin = .; + *(.tdata .tdata.* .gnu.linkonce.td.*) + _TLS_Data_end = .; + } > REGION_RODATA AT > REGION_RODATA_LOAD + .tbss : ALIGN_WITH_INPUT { + _TLS_BSS_begin = .; + *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) + _TLS_BSS_end = .; + } > REGION_RODATA AT > REGION_RODATA_LOAD + _TLS_Data_size = _TLS_Data_end - _TLS_Data_begin; + _TLS_Data_begin = _TLS_Data_size != 0 ? _TLS_Data_begin : _TLS_BSS_begin; + _TLS_Data_end = _TLS_Data_size != 0 ? _TLS_Data_end : _TLS_BSS_begin; + _TLS_BSS_size = _TLS_BSS_end - _TLS_BSS_begin; + _TLS_Size = _TLS_BSS_end - _TLS_Data_begin; + _TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss)); + .preinit_array : ALIGN_WITH_INPUT { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > REGION_RODATA AT > REGION_RODATA_LOAD + .init_array : ALIGN_WITH_INPUT { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } > REGION_RODATA AT > REGION_RODATA_LOAD + .fini_array : ALIGN_WITH_INPUT { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > REGION_RODATA AT > REGION_RODATA_LOAD + .ctors : ALIGN_WITH_INPUT { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .dtors : ALIGN_WITH_INPUT { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .data.rel.ro : ALIGN_WITH_INPUT { + *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) + *(.data.rel.ro .data.rel.ro.* .gnu.linkonce.d.rel.ro.*) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .jcr : ALIGN_WITH_INPUT { + KEEP (*(.jcr)) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .interp : ALIGN_WITH_INPUT { + *(.interp) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .note.gnu.build-id : { *(.note.gnu.build-id) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .hash : ALIGN_WITH_INPUT { + *(.hash) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .gnu.hash : ALIGN_WITH_INPUT { + *(.gnu.hash) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .dynsym : ALIGN_WITH_INPUT { + *(.dynsym) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .dynstr : ALIGN_WITH_INPUT { + *(.dynstr) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .gnu.version : ALIGN_WITH_INPUT { + *(.gnu.version) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .gnu.version_d : ALIGN_WITH_INPUT { + *(.gnu.version_d) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .gnu.version_r : ALIGN_WITH_INPUT { + *(.gnu.version_r) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .rela.dyn : ALIGN_WITH_INPUT { + *(.rela.init) + *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) + *(.rela.fini) + *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) + *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) + *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) + *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) + *(.rela.ctors) + *(.rela.dtors) + *(.rela.got) + *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) + *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) + *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) + *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) + *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) + PROVIDE_HIDDEN (__rela_iplt_start = .); + *(.rela.iplt) + PROVIDE_HIDDEN (__rela_iplt_end = .); + } > REGION_RODATA AT > REGION_RODATA_LOAD + .rela.plt : ALIGN_WITH_INPUT { + *(.rela.plt) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .plt : ALIGN_WITH_INPUT { + *(.plt) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .iplt : ALIGN_WITH_INPUT { + *(.iplt) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .dynamic : ALIGN_WITH_INPUT { + *(.dynamic) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .tm_clone_table : ALIGN_WITH_INPUT { + *(.tm_clone_table) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .got : ALIGN_WITH_INPUT { + *(.got.plt) *(.igot.plt) *(.got) *(.igot) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .rtemsroset : ALIGN_WITH_INPUT { + /* Special FreeBSD linker set sections */ + __start_set_sysctl_set = .; + *(set_sysctl_*); + __stop_set_sysctl_set = .; + *(set_domain_*); + *(set_pseudo_*); + + KEEP (*(SORT(.rtemsroset.*))) + bsp_section_rodata_end = .; + } > REGION_RODATA AT > REGION_RODATA_LOAD + bsp_section_rodata_size = bsp_section_rodata_end - bsp_section_rodata_begin; + bsp_section_rodata_load_begin = LOADADDR (.rodata); + bsp_section_rodata_load_end = bsp_section_rodata_load_begin + bsp_section_rodata_size; + + .rwbarrier : ALIGN_WITH_INPUT { + . = ALIGN (bsp_section_rwbarrier_align); + } > REGION_DATA AT > REGION_DATA + + .fast_text : ALIGN_WITH_INPUT { + bsp_section_fast_text_begin = .; + *(.bsp_fast_text) + bsp_section_fast_text_end = .; + } > REGION_FAST_TEXT AT > REGION_FAST_TEXT_LOAD + bsp_section_fast_text_size = bsp_section_fast_text_end - bsp_section_fast_text_begin; + bsp_section_fast_text_load_begin = LOADADDR (.fast_text); + bsp_section_fast_text_load_end = bsp_section_fast_text_load_begin + bsp_section_fast_text_size; + + .fast_data : ALIGN_WITH_INPUT { + bsp_section_fast_data_begin = .; + *(.bsp_fast_data) + bsp_section_fast_data_end = .; + } > REGION_FAST_DATA AT > REGION_FAST_DATA_LOAD + bsp_section_fast_data_size = bsp_section_fast_data_end - bsp_section_fast_data_begin; + bsp_section_fast_data_load_begin = LOADADDR (.fast_data); + bsp_section_fast_data_load_end = bsp_section_fast_data_load_begin + bsp_section_fast_data_size; + + .data : ALIGN_WITH_INPUT { + bsp_section_data_begin = .; + *(.data .data.* .gnu.linkonce.d.*) + SORT(CONSTRUCTORS) + } > REGION_DATA AT > REGION_DATA_LOAD + .data1 : ALIGN_WITH_INPUT { + *(.data1) + } > REGION_DATA AT > REGION_DATA_LOAD + .rtemsrwset : ALIGN_WITH_INPUT { + KEEP (*(SORT(.rtemsrwset.*))) + } > REGION_DATA AT > REGION_DATA_LOAD + .htif ALIGN(4096) : ALIGN_WITH_INPUT { + *(.htif) + } > REGION_DATA AT > REGION_DATA_LOAD + .sdata : ALIGN_WITH_INPUT { + __global_pointer$ = . + 0x800; + *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) + *(.sdata .sdata.* .gnu.linkonce.s.*) + bsp_section_data_end = .; + } > REGION_DATA AT > REGION_DATA_LOAD + bsp_section_data_size = bsp_section_data_end - bsp_section_data_begin; + bsp_section_data_load_begin = LOADADDR (.data); + bsp_section_data_load_end = bsp_section_data_load_begin + bsp_section_data_size; + + .sbss : ALIGN_WITH_INPUT { + bsp_section_bss_begin = .; + *(.dynsbss) + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.scommon) + } > REGION_DATA AT > REGION_DATA + .bss : ALIGN_WITH_INPUT { + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + bsp_section_bss_end = .; + } > REGION_DATA AT > REGION_DATA + bsp_section_bss_size = bsp_section_bss_end - bsp_section_bss_begin; + + .rtemsstack (NOLOAD) : ALIGN_WITH_INPUT { + bsp_section_rtemsstack_begin = .; + *(SORT(.rtemsstack.*)) + bsp_section_rtemsstack_end = .; + } > REGION_RTEMSSTACK AT > REGION_RTEMSSTACK + bsp_section_rtemsstack_size = bsp_section_rtemsstack_end - bsp_section_rtemsstack_begin; + + .work : ALIGN_WITH_INPUT { + /* + * The work section will occupy the remaining REGION_WORK region and + * contains the RTEMS work space and heap. + */ + bsp_section_work_begin = .; + . += ORIGIN (REGION_WORK) + LENGTH (REGION_WORK) - ABSOLUTE (.); + bsp_section_work_end = .; + } > REGION_WORK AT > REGION_WORK + bsp_section_work_size = bsp_section_work_end - bsp_section_work_begin; + + /* FIXME */ + RamBase = ORIGIN (REGION_WORK); + RamSize = LENGTH (REGION_WORK); + WorkAreaBase = bsp_section_work_begin; + HeapSize = 0; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /* DWARF 3 */ + .debug_pubtypes 0 : { *(.debug_pubtypes) } + .debug_ranges 0 : { *(.debug_ranges) } + /* DWARF Extension. */ + .debug_macro 0 : { *(.debug_macro) } + .debug_addr 0 : { *(.debug_addr) } + .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) } + /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) } + + /* + * This is a RTEMS specific section to catch all unexpected input + * sections. In case you get an error like + * "section `.unexpected_sections' will not fit in region + * `UNEXPECTED_SECTIONS'" + * you have to figure out the offending input section and add it to the + * appropriate output section definition above. + */ + .unexpected_sections : { *(*) } > UNEXPECTED_SECTIONS +} diff --git a/bsps/riscv/riscv/start/start.S b/bsps/riscv/riscv/start/start.S new file mode 100644 index 0000000000..ac5b6a96ef --- /dev/null +++ b/bsps/riscv/riscv/start/start.S @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2015 University of York. + * Hesham Almatary + * + * Copyright (c) 2013, The Regents of the University of California (Regents). + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#include +#include +#include +#include + +EXTERN(bsp_section_bss_begin) +EXTERN(bsp_section_bss_end) +EXTERN(ISR_Handler) +EXTERN(bsp_section_stack_begin) + +PUBLIC(bsp_start_vector_table_begin) +PUBLIC(bsp_start_vector_table_end) +PUBLIC(_start) + +.section .bsp_start_text, "wax" +TYPE_FUNC(_start) +SYM(_start): + li x2, 0 + li x3, 0 + li x4, 0 + li x5, 0 + li x6, 0 + li x7, 0 + li x8, 0 + li x9, 0 + li x10, 0 + li x11, 0 + li x12, 0 + li x13, 0 + li x14, 0 + li x15, 0 + li x16, 0 + li x17, 0 + li x18, 0 + li x19, 0 + li x20, 0 + li x21, 0 + li x22, 0 + li x23, 0 + li x24, 0 + li x25, 0 + li x26, 0 + li x27, 0 + li x28, 0 + li x29, 0 + li x30, 0 + li x31, 0 + + la t0, ISR_Handler + csrw mtvec, t0 + + /* load stack and frame pointers */ + la sp, _Configuration_Interrupt_stack_area_end + + /* Clearing .bss */ + la t0, bsp_section_bss_begin + la t1, bsp_section_bss_end + +_loop_clear_bss: + bge t0, t1, _end_clear_bss + SREG x0, 0(t0) + addi t0, t0, CPU_SIZEOF_POINTER + j _loop_clear_bss +_end_clear_bss: + + /* Init FPU unit if it's there */ + li t0, MSTATUS_FS + csrs mstatus, t0 + + j boot_card + + .align 4 +bsp_start_vector_table_begin: + .word _RISCV_Exception_default /* User int */ + .word _RISCV_Exception_default /* Supervisor int */ + .word _RISCV_Exception_default /* Reserved */ + .word _RISCV_Exception_default /* Machine int */ + .word _RISCV_Exception_default /* User timer int */ + .word _RISCV_Exception_default /* Supervisor Timer int */ + .word _RISCV_Exception_default /* Reserved */ + .word _RISCV_Exception_default /* Machine Timer int */ + .word _RISCV_Exception_default /* User external int */ + .word _RISCV_Exception_default /* Supervisor external int */ + .word _RISCV_Exception_default /* Reserved */ + .word _RISCV_Exception_default /* Machine external int */ + .word _RISCV_Exception_default + .word _RISCV_Exception_default + .word _RISCV_Exception_default + .word _RISCV_Exception_default +bsp_start_vector_table_end: diff --git a/bsps/riscv/riscv_generic/btimer/btimer.c b/bsps/riscv/riscv_generic/btimer/btimer.c deleted file mode 100644 index 4dd3193685..0000000000 --- a/bsps/riscv/riscv_generic/btimer/btimer.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2015 University of York. - * Hesham Almatary - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -#include -#include -#include - -extern char bsp_start_vector_table_begin[]; - -bool benchmark_timer_find_average_overhead; - -static void benchmark_timer1_interrupt_handler(void) -{ -} - -/* Start eCore tiemr 1 usef for profiling and timing analysis */ -void benchmark_timer_initialize( void ) -{ - /* Install interrupt handler for timer 1 */ -} - -/* - * The following controls the behavior of benchmark_timer_read(). - * - * AVG_OVEREHAD is the overhead for starting and stopping the timer. It - * is usually deducted from the number returned. - * - * LEAST_VALID is the lowest number this routine should trust. Numbers - * below this are "noise" and zero is returned. - */ - -#define AVG_OVERHEAD 0 /* It typically takes X.X microseconds */ -/* (Y countdowns) to start/stop the timer. */ -/* This value is in microseconds. */ -#define LEAST_VALID 1 /* Don't trust a clicks value lower than this */ - -benchmark_timer_t benchmark_timer_read( void ) -{ -} - -void benchmark_timer_disable_subtracting_average_overhead( - bool find_flag -) -{ - benchmark_timer_find_average_overhead = find_flag; -} diff --git a/bsps/riscv/riscv_generic/clock/clockdrv.c b/bsps/riscv/riscv_generic/clock/clockdrv.c deleted file mode 100644 index 340e158489..0000000000 --- a/bsps/riscv/riscv_generic/clock/clockdrv.c +++ /dev/null @@ -1,122 +0,0 @@ -/** - * @file - * - * @ingroup bsp_clock - * - * @brief riscv clock support. - */ - -/* - * riscv_generic Clock driver - * - * COPYRIGHT (c) 2015 Hesham Alatary - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include -#include - -/* The number of clock cycles before generating a tick timer interrupt. */ -#define TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT 1000 -#define RISCV_CLOCK_CYCLE_TIME_NANOSECONDS 1 - -static struct timecounter riscv_generic_tc; - -/* CPU counter */ -static CPU_Counter_ticks cpu_counter_ticks; - -/* This prototype is added here to Avoid warnings */ -void Clock_isr(void *arg); - -static void riscv_generic_clock_at_tick(void) -{ - REG(MTIME_MM) = 0; - REG(MTIMECMP_MM) = TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT; - - cpu_counter_ticks += TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT * 10000; -} - -static void riscv_generic_clock_handler_install(proc_ptr new_isr) -{ - rtems_status_code sc = RTEMS_SUCCESSFUL; - _CPU_ISR_install_vector(RISCV_MACHINE_TIMER_INTERRUPT, - new_isr, - NULL); - - if (sc != RTEMS_SUCCESSFUL) { - rtems_fatal_error_occurred(0xdeadbeef); - } -} - -static uint32_t riscv_generic_get_timecount(struct timecounter *tc) -{ - uint32_t ticks_since_last_timer_interrupt = REG(MTIME_MM); - - return cpu_counter_ticks + ticks_since_last_timer_interrupt; -} - -CPU_Counter_ticks _CPU_Counter_read(void) -{ - return riscv_generic_get_timecount(NULL); -} - -static void riscv_generic_clock_initialize(void) -{ - uint32_t mtimecmp = TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT; - uint64_t frequency = (1000000000 / RISCV_CLOCK_CYCLE_TIME_NANOSECONDS); - - REG(MTIME_MM) = 0; - REG(MTIMECMP_MM) = TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT; - - /* Enable mtimer interrupts */ - set_csr(mie, MIP_MTIP); - set_csr(mip, MIP_MTIP); - - /* Initialize timecounter */ - riscv_generic_tc.tc_get_timecount = riscv_generic_get_timecount; - riscv_generic_tc.tc_counter_mask = 0xffffffff; - riscv_generic_tc.tc_frequency = frequency; - riscv_generic_tc.tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER; - rtems_timecounter_install(&riscv_generic_tc); -} - -CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#define Clock_driver_support_at_tick() riscv_generic_clock_at_tick() - -#define Clock_driver_support_initialize_hardware() riscv_generic_clock_initialize() - -#define Clock_driver_support_install_isr(isr) \ - riscv_generic_clock_handler_install(isr) - -#include "../../../shared/dev/clock/clockimpl.h" diff --git a/bsps/riscv/riscv_generic/config/rv32i.cfg b/bsps/riscv/riscv_generic/config/rv32i.cfg deleted file mode 100644 index a394590dc2..0000000000 --- a/bsps/riscv/riscv_generic/config/rv32i.cfg +++ /dev/null @@ -1,9 +0,0 @@ -include $(RTEMS_ROOT)/make/custom/default.cfg - -RTEMS_CPU = riscv - -CPU_CFLAGS = -march=rv32i -mabi=ilp32 - -LDFLAGS = -Wl,--gc-sections - -CFLAGS_OPTIMIZE_V ?= -O2 -g -ffunction-sections -fdata-sections diff --git a/bsps/riscv/riscv_generic/config/rv32iac.cfg b/bsps/riscv/riscv_generic/config/rv32iac.cfg deleted file mode 100644 index 369f2c441d..0000000000 --- a/bsps/riscv/riscv_generic/config/rv32iac.cfg +++ /dev/null @@ -1,9 +0,0 @@ -include $(RTEMS_ROOT)/make/custom/default.cfg - -RTEMS_CPU = riscv - -CPU_CFLAGS = -march=rv32iac -mabi=ilp32 - -LDFLAGS = -Wl,--gc-sections - -CFLAGS_OPTIMIZE_V ?= -O2 -g -ffunction-sections -fdata-sections diff --git a/bsps/riscv/riscv_generic/config/rv32im.cfg b/bsps/riscv/riscv_generic/config/rv32im.cfg deleted file mode 100644 index 46dfdad09c..0000000000 --- a/bsps/riscv/riscv_generic/config/rv32im.cfg +++ /dev/null @@ -1,9 +0,0 @@ -include $(RTEMS_ROOT)/make/custom/default.cfg - -RTEMS_CPU = riscv - -CPU_CFLAGS = -march=rv32im -mabi=ilp32 - -LDFLAGS = -Wl,--gc-sections - -CFLAGS_OPTIMIZE_V ?= -O2 -g -ffunction-sections -fdata-sections diff --git a/bsps/riscv/riscv_generic/config/rv32imac.cfg b/bsps/riscv/riscv_generic/config/rv32imac.cfg deleted file mode 100644 index e19e431b53..0000000000 --- a/bsps/riscv/riscv_generic/config/rv32imac.cfg +++ /dev/null @@ -1,9 +0,0 @@ -include $(RTEMS_ROOT)/make/custom/default.cfg - -RTEMS_CPU = riscv - -CPU_CFLAGS = -march=rv32imac -mabi=ilp32 - -LDFLAGS = -Wl,--gc-sections - -CFLAGS_OPTIMIZE_V ?= -O2 -g -ffunction-sections -fdata-sections diff --git a/bsps/riscv/riscv_generic/config/rv32imafc.cfg b/bsps/riscv/riscv_generic/config/rv32imafc.cfg deleted file mode 100644 index bd4a0cacbe..0000000000 --- a/bsps/riscv/riscv_generic/config/rv32imafc.cfg +++ /dev/null @@ -1,9 +0,0 @@ -include $(RTEMS_ROOT)/make/custom/default.cfg - -RTEMS_CPU = riscv - -CPU_CFLAGS = -march=rv32imafc -mabi=ilp32f - -LDFLAGS = -Wl,--gc-sections - -CFLAGS_OPTIMIZE_V ?= -O2 -g -ffunction-sections -fdata-sections diff --git a/bsps/riscv/riscv_generic/config/rv64imac.cfg b/bsps/riscv/riscv_generic/config/rv64imac.cfg deleted file mode 100644 index e5df5995ac..0000000000 --- a/bsps/riscv/riscv_generic/config/rv64imac.cfg +++ /dev/null @@ -1,9 +0,0 @@ -include $(RTEMS_ROOT)/make/custom/default.cfg - -RTEMS_CPU = riscv - -CPU_CFLAGS = -march=rv64imac -mabi=lp64 - -LDFLAGS = -Wl,--gc-sections - -CFLAGS_OPTIMIZE_V ?= -O2 -g -ffunction-sections -fdata-sections diff --git a/bsps/riscv/riscv_generic/config/rv64imafdc.cfg b/bsps/riscv/riscv_generic/config/rv64imafdc.cfg deleted file mode 100644 index 09caf7adbf..0000000000 --- a/bsps/riscv/riscv_generic/config/rv64imafdc.cfg +++ /dev/null @@ -1,9 +0,0 @@ -include $(RTEMS_ROOT)/make/custom/default.cfg - -RTEMS_CPU = riscv - -CPU_CFLAGS = -march=rv64imafdc -mabi=lp64d - -LDFLAGS = -Wl,--gc-sections - -CFLAGS_OPTIMIZE_V ?= -O2 -g -ffunction-sections -fdata-sections diff --git a/bsps/riscv/riscv_generic/console/console-io.c b/bsps/riscv/riscv_generic/console/console-io.c deleted file mode 100644 index a300e11753..0000000000 --- a/bsps/riscv/riscv_generic/console/console-io.c +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (c) 2015 University of York. - * Hesham Almatary - * - * Copyright (c) 2013, The Regents of the University of California (Regents). - * All Rights Reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include -#include - -/* Most of the code below is copied from riscv-pk project */ -# define TOHOST_CMD(dev, cmd, payload) \ - (((uint64_t)(dev) << 56) | ((uint64_t)(cmd) << 48) | (uint64_t)(payload)) - -#define FROMHOST_DEV(fromhost_value) ((uint64_t)(fromhost_value) >> 56) -#define FROMHOST_CMD(fromhost_value) ((uint64_t)(fromhost_value) << 8 >> 56) -#define FROMHOST_DATA(fromhost_value) ((uint64_t)(fromhost_value) << 16 >> 16) - -volatile uint64_t tohost __attribute__((section(".htif"))); -volatile uint64_t fromhost __attribute__((section(".htif"))); -volatile uint64_t riscv_fill_up_htif_section[510] __attribute__((section(".htif"))); -volatile int htif_console_buf; - -static void __check_fromhost() -{ - uint64_t fh = fromhost; - if (!fh) { - return; - } - fromhost = 0; - - // this should be from the console - assert(FROMHOST_DEV(fh) == 1); - switch (FROMHOST_CMD(fh)) { - case 0: - htif_console_buf = 1 + (uint8_t)FROMHOST_DATA(fh); - break; - case 1: - break; - default: - assert(0); - } -} - -static void __set_tohost(uintptr_t dev, uintptr_t cmd, uintptr_t data) -{ - while (tohost) { - __check_fromhost(); - } - tohost = TOHOST_CMD(dev, cmd, data); -} - -int htif_console_getchar() -{ - __check_fromhost(); - int ch = htif_console_buf; - if (ch >= 0) { - htif_console_buf = -1; - __set_tohost(1, 0, 0); - } - - return ch - 1; -} - -static void do_tohost_fromhost(uintptr_t dev, uintptr_t cmd, uintptr_t data) -{ - __set_tohost(dev, cmd, data); - - while (1) { - uint64_t fh = fromhost; - if (fh) { - if (FROMHOST_DEV(fh) == dev && FROMHOST_CMD(fh) == cmd) { - fromhost = 0; - break; - } - __check_fromhost(); - } - } -} - -void htif_console_putchar(uint8_t ch) -{ - __set_tohost(1, 1, ch); -} - -void htif_poweroff() -{ - while (1) { - fromhost = 0; - tohost = 1; - } -} - -void console_initialize_hardware(void) -{ - /* Do nothing */ -} - -static void outbyte_console(char ch) -{ - htif_console_putchar(ch); -} - -static char inbyte_console(void) -{ - return htif_console_getchar(); -} - -/* - * console_outbyte_polled - * - * This routine transmits a character using polling. - */ -void console_outbyte_polled( - int port, - char ch -) -{ - outbyte_console( ch ); -} - -/* - * console_inbyte_nonblocking - * - * This routine polls for a character. - */ - -int console_inbyte_nonblocking(int port) -{ - char c; - - c = inbyte_console(); - if (!c) { - return -1; - } - return (int) c; -} - -/* - * To support printk - */ - -#include - -static void RISCV_output_char(char c) -{ - console_outbyte_polled( 0, c ); -} - -BSP_output_char_function_type BSP_output_char = RISCV_output_char; -BSP_polling_getchar_function_type BSP_poll_char = - (void *)console_inbyte_nonblocking; diff --git a/bsps/riscv/riscv_generic/headers.am b/bsps/riscv/riscv_generic/headers.am deleted file mode 100644 index 6993fe8688..0000000000 --- a/bsps/riscv/riscv_generic/headers.am +++ /dev/null @@ -1,10 +0,0 @@ -## This file was generated by "./boostrap -H". - -include_HEADERS = -include_HEADERS += ../../../../../../bsps/riscv/riscv_generic/include/bsp.h -include_HEADERS += include/bspopts.h -include_HEADERS += ../../../../../../bsps/riscv/riscv_generic/include/tm27.h - -include_bspdir = $(includedir)/bsp -include_bsp_HEADERS = -include_bsp_HEADERS += ../../../../../../bsps/riscv/riscv_generic/include/bsp/irq.h diff --git a/bsps/riscv/riscv_generic/include/bsp.h b/bsps/riscv/riscv_generic/include/bsp.h deleted file mode 100644 index 79f359ac34..0000000000 --- a/bsps/riscv/riscv_generic/include/bsp.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * - * Copyright (c) 2015 University of York. - * Hesham Almatary - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef LIBBSP_RISCV_GENERIC_H -#define LIBBSP_RISCV_GENERIC_H - -#include -#include -#include - -#include -#include - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup riscv_generic Register Definitions - * - * @ingroup riscv_generic - * - * @brief Shared register definitions for RISC-V systems. - * - * @{ - */ - -/** - * @name Register Macros - * - * @{ - */ - -#define REG(x) (*((volatile unsigned long *) (x))) -#define BIT(n) (1 << (n)) - -#define MTIME_MM 0x000000000200bff8 -#define MTIMECMP_MM 0x0000000002004000 - -#ifdef __cplusplus -} -#endif - -#endif /* LIBBSP_RISCV_GENERIC_H */ diff --git a/bsps/riscv/riscv_generic/include/bsp/irq.h b/bsps/riscv/riscv_generic/include/bsp/irq.h deleted file mode 100644 index d7ee45b378..0000000000 --- a/bsps/riscv/riscv_generic/include/bsp/irq.h +++ /dev/null @@ -1,49 +0,0 @@ -/** - * @file - * - * @ingroup RISCV_IRQ - * - * @brief Interrupt definitions. - */ - -/* - * - * Copyright (c) 2015 University of York. - * Hesham Almatary - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef LIBBSP_GENERIC_RISCV_IRQ_H -#define LIBBSP_GENERIC_RISCV_IRQ_H - -#ifndef ASM - -#include -#include -#include - -#define BSP_INTERRUPT_VECTOR_MIN 0x0 -#define BSP_INTERRUPT_VECTOR_MAX 0x24 - -#endif /* ASM */ -#endif /* LIBBSP_GENERIC_RISCV_IRQ_H */ diff --git a/bsps/riscv/riscv_generic/include/tm27.h b/bsps/riscv/riscv_generic/include/tm27.h deleted file mode 100644 index 0dfa7bf628..0000000000 --- a/bsps/riscv/riscv_generic/include/tm27.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/bsps/riscv/riscv_generic/irq/irq.c b/bsps/riscv/riscv_generic/irq/irq.c deleted file mode 100644 index 8090dcea98..0000000000 --- a/bsps/riscv/riscv_generic/irq/irq.c +++ /dev/null @@ -1,60 +0,0 @@ -/** - * @file - * - * @ingroup riscv_interrupt - * - * @brief Interrupt support. - */ - -/* - * RISCV CPU Dependent Source - * - * Copyright (c) 2015 University of York. - * Hesham Almatary - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -#include - -/* Almost all of the jobs that the following functions should - * do are implemented in cpukit - */ - -void bsp_interrupt_handler_default(rtems_vector_number vector) -{ - printk("spurious interrupt: %u\n", vector); -} - -rtems_status_code bsp_interrupt_facility_initialize() -{ - return RTEMS_NOT_IMPLEMENTED; -} - -void bsp_interrupt_vector_enable(rtems_vector_number vector) -{ -} - -void bsp_interrupt_vector_disable(rtems_vector_number vector) -{ -} diff --git a/bsps/riscv/riscv_generic/start/bsp_fatal_halt.c b/bsps/riscv/riscv_generic/start/bsp_fatal_halt.c deleted file mode 100644 index 64c307990b..0000000000 --- a/bsps/riscv/riscv_generic/start/bsp_fatal_halt.c +++ /dev/null @@ -1,35 +0,0 @@ -/* @ingroup riscv_generic - * @brief riscv_generic BSP Fatal_halt handler. - * - * Copyright (c) 2015 University of York. - * Hesham Almatary - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include - -/* Send a power-off signal to the host */ -void _CPU_Fatal_halt(uint32_t source, uint32_t error) -{ - htif_poweroff(); -} diff --git a/bsps/riscv/riscv_generic/start/bsp_specs b/bsps/riscv/riscv_generic/start/bsp_specs deleted file mode 100644 index 87638cc027..0000000000 --- a/bsps/riscv/riscv_generic/start/bsp_specs +++ /dev/null @@ -1,9 +0,0 @@ -%rename endfile old_endfile -%rename startfile old_startfile - -*startfile: -%{!qrtems: %(old_startfile)} \ -%{!nostdlib: %{qrtems: crti.o%s crtbegin.o%s}} - -*endfile: -%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtn.o%s} diff --git a/bsps/riscv/riscv_generic/start/linkcmds b/bsps/riscv/riscv_generic/start/linkcmds deleted file mode 100644 index 7bcf657341..0000000000 --- a/bsps/riscv/riscv_generic/start/linkcmds +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2015 University of York. - * Hesham ALMatary - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -MEMORY -{ - RAM : ORIGIN = 0x0000000010000000, LENGTH = 0x10000000 -} - -REGION_ALIAS ("REGION_START", RAM); -REGION_ALIAS ("REGION_TEXT", RAM); -REGION_ALIAS ("REGION_TEXT_LOAD", RAM); -REGION_ALIAS ("REGION_FAST_TEXT", RAM); -REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM); -REGION_ALIAS ("REGION_RODATA", RAM); -REGION_ALIAS ("REGION_RODATA_LOAD", RAM); -REGION_ALIAS ("REGION_DATA", RAM); -REGION_ALIAS ("REGION_DATA_LOAD", RAM); -REGION_ALIAS ("REGION_FAST_DATA", RAM); -REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM); -REGION_ALIAS ("REGION_RTEMSSTACK", RAM); -REGION_ALIAS ("REGION_WORK", RAM); - -INCLUDE linkcmds.base diff --git a/bsps/riscv/riscv_generic/start/linkcmds.base b/bsps/riscv/riscv_generic/start/linkcmds.base deleted file mode 100644 index 7d889ab38c..0000000000 --- a/bsps/riscv/riscv_generic/start/linkcmds.base +++ /dev/null @@ -1,385 +0,0 @@ -/* Copyright (C) 2014-2018 Free Software Foundation, Inc. - Copying and distribution of this script, with or without modification, - are permitted in any medium without royalty provided the copyright - notice and this notice are preserved. */ - -/* - * Copyright (c) 2018 embedded brains GmbH. - * - * Copyright (c) 2015 University of York. - * Hesham ALMatary - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -OUTPUT_ARCH(riscv) -ENTRY(_start) -STARTUP(start.o) - -bsp_section_robarrier_align = DEFINED (bsp_section_robarrier_align) ? bsp_section_robarrier_align : 1; -bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_section_rwbarrier_align : 1; - -MEMORY { - UNEXPECTED_SECTIONS : ORIGIN = 0xffffffff, LENGTH = 0 -} - -SECTIONS { - .start : ALIGN_WITH_INPUT { - bsp_section_start_begin = .; - KEEP (*(.bsp_start_text)) - KEEP (*(.bsp_start_data)) - bsp_section_start_end = .; - } > REGION_START AT > REGION_START - bsp_section_start_size = bsp_section_start_end - bsp_section_start_begin; - - .text : ALIGN_WITH_INPUT { - bsp_section_text_begin = .; - *(.text.unlikely .text.*_unlikely .text.unlikely.*) - *(.text.exit .text.exit.*) - *(.text.startup .text.startup.*) - *(.text.hot .text.hot.*) - *(.text .stub .text.* .gnu.linkonce.t.*) - /* .gnu.warning sections are handled specially by elf32.em. */ - *(.gnu.warning) - } > REGION_TEXT AT > REGION_TEXT_LOAD - .init : ALIGN_WITH_INPUT { - KEEP (*(SORT_NONE(.init))) - } > REGION_TEXT AT > REGION_TEXT_LOAD - .fini : ALIGN_WITH_INPUT { - KEEP (*(SORT_NONE(.fini))) - bsp_section_text_end = .; - } > REGION_TEXT AT > REGION_TEXT_LOAD - bsp_section_text_size = bsp_section_text_end - bsp_section_text_begin; - bsp_section_text_load_begin = LOADADDR (.text); - bsp_section_text_load_end = bsp_section_text_load_begin + bsp_section_text_size; - - .robarrier : ALIGN_WITH_INPUT { - . = ALIGN (bsp_section_robarrier_align); - } > REGION_RODATA AT > REGION_RODATA - - .rodata : ALIGN_WITH_INPUT { - bsp_section_rodata_begin = .; - *(.rodata .rodata.* .gnu.linkonce.r.*) - } > REGION_RODATA AT > REGION_RODATA_LOAD - .rodata1 : ALIGN_WITH_INPUT { - *(.rodata1) - } > REGION_RODATA AT > REGION_RODATA_LOAD - .sdata2 : ALIGN_WITH_INPUT { - *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) - } > REGION_RODATA AT > REGION_RODATA_LOAD - .sbss2 : ALIGN_WITH_INPUT { - *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) - } > REGION_RODATA AT > REGION_RODATA_LOAD - .eh_frame_hdr : ALIGN_WITH_INPUT { - *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) - } > REGION_RODATA AT > REGION_RODATA_LOAD - .eh_frame : ALIGN_WITH_INPUT { - KEEP (*(.eh_frame)) *(.eh_frame.*) - } > REGION_RODATA AT > REGION_RODATA_LOAD - .gcc_except_table : ALIGN_WITH_INPUT { - *(.gcc_except_table .gcc_except_table.*) - } > REGION_RODATA AT > REGION_RODATA_LOAD - .gnu_extab : ALIGN_WITH_INPUT { - *(.gnu_extab*) - } > REGION_RODATA AT > REGION_RODATA_LOAD - .tdata : ALIGN_WITH_INPUT { - _TLS_Data_begin = .; - *(.tdata .tdata.* .gnu.linkonce.td.*) - _TLS_Data_end = .; - } > REGION_RODATA AT > REGION_RODATA_LOAD - .tbss : ALIGN_WITH_INPUT { - _TLS_BSS_begin = .; - *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) - _TLS_BSS_end = .; - } > REGION_RODATA AT > REGION_RODATA_LOAD - _TLS_Data_size = _TLS_Data_end - _TLS_Data_begin; - _TLS_Data_begin = _TLS_Data_size != 0 ? _TLS_Data_begin : _TLS_BSS_begin; - _TLS_Data_end = _TLS_Data_size != 0 ? _TLS_Data_end : _TLS_BSS_begin; - _TLS_BSS_size = _TLS_BSS_end - _TLS_BSS_begin; - _TLS_Size = _TLS_BSS_end - _TLS_Data_begin; - _TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss)); - .preinit_array : ALIGN_WITH_INPUT { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } > REGION_RODATA AT > REGION_RODATA_LOAD - .init_array : ALIGN_WITH_INPUT { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) - PROVIDE_HIDDEN (__init_array_end = .); - } > REGION_RODATA AT > REGION_RODATA_LOAD - .fini_array : ALIGN_WITH_INPUT { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) - KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) - PROVIDE_HIDDEN (__fini_array_end = .); - } > REGION_RODATA AT > REGION_RODATA_LOAD - .ctors : ALIGN_WITH_INPUT { - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - } > REGION_RODATA AT > REGION_RODATA_LOAD - .dtors : ALIGN_WITH_INPUT { - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - } > REGION_RODATA AT > REGION_RODATA_LOAD - .data.rel.ro : ALIGN_WITH_INPUT { - *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) - *(.data.rel.ro .data.rel.ro.* .gnu.linkonce.d.rel.ro.*) - } > REGION_RODATA AT > REGION_RODATA_LOAD - .jcr : ALIGN_WITH_INPUT { - KEEP (*(.jcr)) - } > REGION_RODATA AT > REGION_RODATA_LOAD - .interp : ALIGN_WITH_INPUT { - *(.interp) - } > REGION_RODATA AT > REGION_RODATA_LOAD - .note.gnu.build-id : { *(.note.gnu.build-id) - } > REGION_RODATA AT > REGION_RODATA_LOAD - .hash : ALIGN_WITH_INPUT { - *(.hash) - } > REGION_RODATA AT > REGION_RODATA_LOAD - .gnu.hash : ALIGN_WITH_INPUT { - *(.gnu.hash) - } > REGION_RODATA AT > REGION_RODATA_LOAD - .dynsym : ALIGN_WITH_INPUT { - *(.dynsym) - } > REGION_RODATA AT > REGION_RODATA_LOAD - .dynstr : ALIGN_WITH_INPUT { - *(.dynstr) - } > REGION_RODATA AT > REGION_RODATA_LOAD - .gnu.version : ALIGN_WITH_INPUT { - *(.gnu.version) - } > REGION_RODATA AT > REGION_RODATA_LOAD - .gnu.version_d : ALIGN_WITH_INPUT { - *(.gnu.version_d) - } > REGION_RODATA AT > REGION_RODATA_LOAD - .gnu.version_r : ALIGN_WITH_INPUT { - *(.gnu.version_r) - } > REGION_RODATA AT > REGION_RODATA_LOAD - .rela.dyn : ALIGN_WITH_INPUT { - *(.rela.init) - *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) - *(.rela.fini) - *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) - *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) - *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) - *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) - *(.rela.ctors) - *(.rela.dtors) - *(.rela.got) - *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) - *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) - *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) - *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) - *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) - PROVIDE_HIDDEN (__rela_iplt_start = .); - *(.rela.iplt) - PROVIDE_HIDDEN (__rela_iplt_end = .); - } > REGION_RODATA AT > REGION_RODATA_LOAD - .rela.plt : ALIGN_WITH_INPUT { - *(.rela.plt) - } > REGION_RODATA AT > REGION_RODATA_LOAD - .plt : ALIGN_WITH_INPUT { - *(.plt) - } > REGION_RODATA AT > REGION_RODATA_LOAD - .iplt : ALIGN_WITH_INPUT { - *(.iplt) - } > REGION_RODATA AT > REGION_RODATA_LOAD - .dynamic : ALIGN_WITH_INPUT { - *(.dynamic) - } > REGION_RODATA AT > REGION_RODATA_LOAD - .tm_clone_table : ALIGN_WITH_INPUT { - *(.tm_clone_table) - } > REGION_RODATA AT > REGION_RODATA_LOAD - .got : ALIGN_WITH_INPUT { - *(.got.plt) *(.igot.plt) *(.got) *(.igot) - } > REGION_RODATA AT > REGION_RODATA_LOAD - .rtemsroset : ALIGN_WITH_INPUT { - /* Special FreeBSD linker set sections */ - __start_set_sysctl_set = .; - *(set_sysctl_*); - __stop_set_sysctl_set = .; - *(set_domain_*); - *(set_pseudo_*); - - KEEP (*(SORT(.rtemsroset.*))) - bsp_section_rodata_end = .; - } > REGION_RODATA AT > REGION_RODATA_LOAD - bsp_section_rodata_size = bsp_section_rodata_end - bsp_section_rodata_begin; - bsp_section_rodata_load_begin = LOADADDR (.rodata); - bsp_section_rodata_load_end = bsp_section_rodata_load_begin + bsp_section_rodata_size; - - .rwbarrier : ALIGN_WITH_INPUT { - . = ALIGN (bsp_section_rwbarrier_align); - } > REGION_DATA AT > REGION_DATA - - .fast_text : ALIGN_WITH_INPUT { - bsp_section_fast_text_begin = .; - *(.bsp_fast_text) - bsp_section_fast_text_end = .; - } > REGION_FAST_TEXT AT > REGION_FAST_TEXT_LOAD - bsp_section_fast_text_size = bsp_section_fast_text_end - bsp_section_fast_text_begin; - bsp_section_fast_text_load_begin = LOADADDR (.fast_text); - bsp_section_fast_text_load_end = bsp_section_fast_text_load_begin + bsp_section_fast_text_size; - - .fast_data : ALIGN_WITH_INPUT { - bsp_section_fast_data_begin = .; - *(.bsp_fast_data) - bsp_section_fast_data_end = .; - } > REGION_FAST_DATA AT > REGION_FAST_DATA_LOAD - bsp_section_fast_data_size = bsp_section_fast_data_end - bsp_section_fast_data_begin; - bsp_section_fast_data_load_begin = LOADADDR (.fast_data); - bsp_section_fast_data_load_end = bsp_section_fast_data_load_begin + bsp_section_fast_data_size; - - .data : ALIGN_WITH_INPUT { - bsp_section_data_begin = .; - *(.data .data.* .gnu.linkonce.d.*) - SORT(CONSTRUCTORS) - } > REGION_DATA AT > REGION_DATA_LOAD - .data1 : ALIGN_WITH_INPUT { - *(.data1) - } > REGION_DATA AT > REGION_DATA_LOAD - .rtemsrwset : ALIGN_WITH_INPUT { - KEEP (*(SORT(.rtemsrwset.*))) - } > REGION_DATA AT > REGION_DATA_LOAD - .htif ALIGN(4096) : ALIGN_WITH_INPUT { - *(.htif) - } > REGION_DATA AT > REGION_DATA_LOAD - .sdata : ALIGN_WITH_INPUT { - __global_pointer$ = . + 0x800; - *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - *(.sdata .sdata.* .gnu.linkonce.s.*) - bsp_section_data_end = .; - } > REGION_DATA AT > REGION_DATA_LOAD - bsp_section_data_size = bsp_section_data_end - bsp_section_data_begin; - bsp_section_data_load_begin = LOADADDR (.data); - bsp_section_data_load_end = bsp_section_data_load_begin + bsp_section_data_size; - - .sbss : ALIGN_WITH_INPUT { - bsp_section_bss_begin = .; - *(.dynsbss) - *(.sbss .sbss.* .gnu.linkonce.sb.*) - *(.scommon) - } > REGION_DATA AT > REGION_DATA - .bss : ALIGN_WITH_INPUT { - *(.dynbss) - *(.bss .bss.* .gnu.linkonce.b.*) - *(COMMON) - bsp_section_bss_end = .; - } > REGION_DATA AT > REGION_DATA - bsp_section_bss_size = bsp_section_bss_end - bsp_section_bss_begin; - - .rtemsstack (NOLOAD) : ALIGN_WITH_INPUT { - bsp_section_rtemsstack_begin = .; - *(SORT(.rtemsstack.*)) - bsp_section_rtemsstack_end = .; - } > REGION_RTEMSSTACK AT > REGION_RTEMSSTACK - bsp_section_rtemsstack_size = bsp_section_rtemsstack_end - bsp_section_rtemsstack_begin; - - .work : ALIGN_WITH_INPUT { - /* - * The work section will occupy the remaining REGION_WORK region and - * contains the RTEMS work space and heap. - */ - bsp_section_work_begin = .; - . += ORIGIN (REGION_WORK) + LENGTH (REGION_WORK) - ABSOLUTE (.); - bsp_section_work_end = .; - } > REGION_WORK AT > REGION_WORK - bsp_section_work_size = bsp_section_work_end - bsp_section_work_begin; - - /* FIXME */ - RamBase = ORIGIN (REGION_WORK); - RamSize = LENGTH (REGION_WORK); - WorkAreaBase = bsp_section_work_begin; - HeapSize = 0; - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - /* DWARF 3 */ - .debug_pubtypes 0 : { *(.debug_pubtypes) } - .debug_ranges 0 : { *(.debug_ranges) } - /* DWARF Extension. */ - .debug_macro 0 : { *(.debug_macro) } - .debug_addr 0 : { *(.debug_addr) } - .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) } - /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) } - - /* - * This is a RTEMS specific section to catch all unexpected input - * sections. In case you get an error like - * "section `.unexpected_sections' will not fit in region - * `UNEXPECTED_SECTIONS'" - * you have to figure out the offending input section and add it to the - * appropriate output section definition above. - */ - .unexpected_sections : { *(*) } > UNEXPECTED_SECTIONS -} diff --git a/bsps/riscv/riscv_generic/start/start.S b/bsps/riscv/riscv_generic/start/start.S deleted file mode 100644 index ac5b6a96ef..0000000000 --- a/bsps/riscv/riscv_generic/start/start.S +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright (c) 2015 University of York. - * Hesham Almatary - * - * Copyright (c) 2013, The Regents of the University of California (Regents). - * All Rights Reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ -#include -#include -#include -#include - -EXTERN(bsp_section_bss_begin) -EXTERN(bsp_section_bss_end) -EXTERN(ISR_Handler) -EXTERN(bsp_section_stack_begin) - -PUBLIC(bsp_start_vector_table_begin) -PUBLIC(bsp_start_vector_table_end) -PUBLIC(_start) - -.section .bsp_start_text, "wax" -TYPE_FUNC(_start) -SYM(_start): - li x2, 0 - li x3, 0 - li x4, 0 - li x5, 0 - li x6, 0 - li x7, 0 - li x8, 0 - li x9, 0 - li x10, 0 - li x11, 0 - li x12, 0 - li x13, 0 - li x14, 0 - li x15, 0 - li x16, 0 - li x17, 0 - li x18, 0 - li x19, 0 - li x20, 0 - li x21, 0 - li x22, 0 - li x23, 0 - li x24, 0 - li x25, 0 - li x26, 0 - li x27, 0 - li x28, 0 - li x29, 0 - li x30, 0 - li x31, 0 - - la t0, ISR_Handler - csrw mtvec, t0 - - /* load stack and frame pointers */ - la sp, _Configuration_Interrupt_stack_area_end - - /* Clearing .bss */ - la t0, bsp_section_bss_begin - la t1, bsp_section_bss_end - -_loop_clear_bss: - bge t0, t1, _end_clear_bss - SREG x0, 0(t0) - addi t0, t0, CPU_SIZEOF_POINTER - j _loop_clear_bss -_end_clear_bss: - - /* Init FPU unit if it's there */ - li t0, MSTATUS_FS - csrs mstatus, t0 - - j boot_card - - .align 4 -bsp_start_vector_table_begin: - .word _RISCV_Exception_default /* User int */ - .word _RISCV_Exception_default /* Supervisor int */ - .word _RISCV_Exception_default /* Reserved */ - .word _RISCV_Exception_default /* Machine int */ - .word _RISCV_Exception_default /* User timer int */ - .word _RISCV_Exception_default /* Supervisor Timer int */ - .word _RISCV_Exception_default /* Reserved */ - .word _RISCV_Exception_default /* Machine Timer int */ - .word _RISCV_Exception_default /* User external int */ - .word _RISCV_Exception_default /* Supervisor external int */ - .word _RISCV_Exception_default /* Reserved */ - .word _RISCV_Exception_default /* Machine external int */ - .word _RISCV_Exception_default - .word _RISCV_Exception_default - .word _RISCV_Exception_default - .word _RISCV_Exception_default -bsp_start_vector_table_end: -- cgit v1.2.3