From 63e327f9fb0d35a6e9db42a42c4fb9cfb64c8557 Mon Sep 17 00:00:00 2001
From: Karel Gardas <karel@functional.vision>
Date: Sun, 15 May 2022 22:10:39 +0200
Subject: bsp/stm32h7: cleanup osc, clk, per files for stm32h7b3i-dk board

Sponsored-By:	Precidata
---
 .../boards/stm/stm32h7b3i-dk/stm32h7-config-clk.c  |  4 ---
 .../boards/stm/stm32h7b3i-dk/stm32h7-config-osc.c  | 20 ---------------
 .../boards/stm/stm32h7b3i-dk/stm32h7-config-per.c  | 30 ----------------------
 3 files changed, 54 deletions(-)

(limited to 'bsps')

diff --git a/bsps/arm/stm32h7/boards/stm/stm32h7b3i-dk/stm32h7-config-clk.c b/bsps/arm/stm32h7/boards/stm/stm32h7b3i-dk/stm32h7-config-clk.c
index 4c25241b99..c7e62179ce 100644
--- a/bsps/arm/stm32h7/boards/stm/stm32h7b3i-dk/stm32h7-config-clk.c
+++ b/bsps/arm/stm32h7/boards/stm/stm32h7b3i-dk/stm32h7-config-clk.c
@@ -37,11 +37,7 @@ const RCC_ClkInitTypeDef stm32h7_config_clocks = {
     | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1,
   .SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK,
   .SYSCLKDivider = RCC_SYSCLK_DIV1,
-#ifdef STM32H7B3xxQ
   .AHBCLKDivider = RCC_HCLK_DIV1,
-#else
-  .AHBCLKDivider = RCC_HCLK_DIV2,
-#endif
   .APB3CLKDivider = RCC_APB3_DIV2,
   .APB1CLKDivider = RCC_APB1_DIV2,
   .APB2CLKDivider = RCC_APB2_DIV2,
diff --git a/bsps/arm/stm32h7/boards/stm/stm32h7b3i-dk/stm32h7-config-osc.c b/bsps/arm/stm32h7/boards/stm/stm32h7b3i-dk/stm32h7-config-osc.c
index f790201e5a..c09ae4c738 100644
--- a/bsps/arm/stm32h7/boards/stm/stm32h7b3i-dk/stm32h7-config-osc.c
+++ b/bsps/arm/stm32h7/boards/stm/stm32h7b3i-dk/stm32h7-config-osc.c
@@ -32,7 +32,6 @@
 #include <stm32h7/hal.h>
 
 const RCC_OscInitTypeDef stm32h7_config_oscillator = {
-#ifdef STM32H7B3xxQ
   .OscillatorType = RCC_OSCILLATORTYPE_HSE,
   .HSEState = RCC_HSE_ON,
   .HSIState = RCC_HSI_OFF,
@@ -47,23 +46,4 @@ const RCC_OscInitTypeDef stm32h7_config_oscillator = {
   .PLL.PLLQ = 2,
   .PLL.PLLVCOSEL = RCC_PLL1VCOWIDE,
   .PLL.PLLRGE = RCC_PLL1VCIRANGE_1,
-#else
-  .OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE
-    | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_HSI48,
-  .HSEState = RCC_HSE_ON,
-  .LSEState = RCC_LSE_ON,
-  .HSIState = RCC_HSI_DIV1,
-  .HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT,
-  .HSI48State = RCC_HSI48_ON,
-  .PLL.PLLState = RCC_PLL_ON,
-  .PLL.PLLSource = RCC_PLLSOURCE_HSE,
-  .PLL.PLLM = 5,
-  .PLL.PLLN = 192,
-  .PLL.PLLP = 2,
-  .PLL.PLLQ = 12,
-  .PLL.PLLR = 2,
-  .PLL.PLLRGE = RCC_PLL1VCIRANGE_2,
-  .PLL.PLLVCOSEL = RCC_PLL1VCOWIDE,
-  .PLL.PLLFRACN = 0
-#endif
 };
diff --git a/bsps/arm/stm32h7/boards/stm/stm32h7b3i-dk/stm32h7-config-per.c b/bsps/arm/stm32h7/boards/stm/stm32h7b3i-dk/stm32h7-config-per.c
index ce6370d3d0..5b34d72624 100644
--- a/bsps/arm/stm32h7/boards/stm/stm32h7b3i-dk/stm32h7-config-per.c
+++ b/bsps/arm/stm32h7/boards/stm/stm32h7b3i-dk/stm32h7-config-per.c
@@ -32,7 +32,6 @@
 #include <stm32h7/hal.h>
 
 const RCC_PeriphCLKInitTypeDef stm32h7_config_peripheral_clocks = {
-#ifdef STM32H7B3xxQ
   /* for stm32h7b3i-dk BSP we provide only minimalistic peripheral
      configuration just to make available U(S)ARTs working */
   .PeriphClockSelection = RCC_PERIPHCLK_USART3
@@ -47,33 +46,4 @@ const RCC_PeriphCLKInitTypeDef stm32h7_config_peripheral_clocks = {
   .PLL2.PLL2FRACN = 0,
   .Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1,
   .Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2,
-#else
-  .PeriphClockSelection = RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3
-    | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1
-    | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_RNG,
-  .PLL2.PLL2M = 3,
-  .PLL2.PLL2N = 48,
-  .PLL2.PLL2P = 1,
-  .PLL2.PLL2Q = 2,
-  .PLL2.PLL2R = 2,
-  .PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3,
-  .PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE,
-  .PLL2.PLL2FRACN = 0,
-  .PLL3.PLL3M = 25,
-  .PLL3.PLL3N = 192,
-  .PLL3.PLL3P = 2,
-  .PLL3.PLL3Q = 4,
-  .PLL3.PLL3R = 2,
-  .PLL3.PLL3RGE = RCC_PLL3VCIRANGE_0,
-  .PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE,
-  .PLL3.PLL3FRACN = 0,
-  .FmcClockSelection = RCC_FMCCLKSOURCE_PLL2,
-  .FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL,
-  .Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1,
-  .Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2,
-  .I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1,
-  .UsbClockSelection = RCC_USBCLKSOURCE_PLL3,
-  .RTCClockSelection = RCC_RTCCLKSOURCE_LSE,
-  .RngClockSelection = RCC_RNGCLKSOURCE_HSI48
-#endif
 };
-- 
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