From 5cc075712e628191477d0c9d074e15b6a7c1e1e3 Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Fri, 1 Jul 2022 15:21:47 +0200
Subject: irq/arm-gicv3.h: Customize CPU Interface init

Use the existing WRITE_SR() abstraction to access the interrupt group 0 and 1
enable registers.  This fixes the build for the AArch32 target.

Add BSP options which define the initial values of CPU Interface registers.
---
 bsps/include/dev/irq/arm-gicv3.h | 58 +++++++++++++++++++++++++---------------
 1 file changed, 37 insertions(+), 21 deletions(-)

(limited to 'bsps')

diff --git a/bsps/include/dev/irq/arm-gicv3.h b/bsps/include/dev/irq/arm-gicv3.h
index a79368ebdf..a716ffbca5 100644
--- a/bsps/include/dev/irq/arm-gicv3.h
+++ b/bsps/include/dev/irq/arm-gicv3.h
@@ -116,13 +116,16 @@ extern "C" {
 #else /* ARM_MULTILIB_ARCH_V4 */
 
 /* AArch64 GICv3 registers are not named in GCC */
-#define ICC_IGRPEN0 "S3_0_C12_C12_6, %0"
-#define ICC_IGRPEN1 "S3_0_C12_C12_7, %0"
+#define ICC_IGRPEN0_EL1 "S3_0_C12_C12_6, %0"
+#define ICC_IGRPEN1_EL1 "S3_0_C12_C12_7, %0"
 #define ICC_IGRPEN1_EL3 "S3_6_C12_C12_7, %0"
+#define ICC_IGRPEN0 ICC_IGRPEN0_EL1
+#define ICC_IGRPEN1 ICC_IGRPEN1_EL1
 #define ICC_PMR     "S3_0_C4_C6_0, %0"
 #define ICC_EOIR1   "S3_0_C12_C12_1, %0"
 #define ICC_SRE     "S3_0_C12_C12_5, %0"
 #define ICC_BPR0    "S3_0_C12_C8_3, %0"
+#define ICC_BPR1    "S3_0_C12_C12_3, %0"
 #define ICC_CTLR    "S3_0_C12_C12_4, %0"
 #define ICC_IAR1    "%0, S3_0_C12_C12_0"
 #define MPIDR       "%0, mpidr_el1"
@@ -300,25 +303,27 @@ static void gicv3_init_dist(volatile gic_dist *dist)
   }
 }
 
-/*
- * A better way to access these registers than special opcodes
- */
-#define isb() __asm __volatile("isb" : : : "memory")
+static void gicv3_init_cpu_interface(uint32_t cpu_index)
+{
+  /* Initialize Interrupt Controller System Register Enable Register */
+#ifdef BSP_ARM_GIC_ICC_SRE
+  WRITE_SR(ICC_SRE, BSP_ARM_GIC_ICC_SRE);
+#endif
 
-#define  WRITE_SPECIALREG(reg, _val)                                    \
-  __asm __volatile("msr  " __STRING(reg) ", %0" : : "r"((uint64_t)_val))
+  /* Initialize Interrupt Controller Interrupt Priority Mask Register */
+#ifdef BSP_ARM_GIC_ICC_PMR
+  WRITE_SR(ICC_PMR, BSP_ARM_GIC_ICC_PMR);
+#endif
 
-#define  gic_icc_write(reg, val)            \
-do {                                        \
-  WRITE_SPECIALREG(icc_ ##reg ##_el1, val); \
-  isb();                                    \
-} while (0)
+  /* Initialize Interrupt Controller Binary Point Register 0 */
+#ifdef BSP_ARM_GIC_ICC_BPR0
+  WRITE_SR(ICC_BPR0, BSP_ARM_GIC_ICC_BPR0);
+#endif
 
-static void gicv3_init_cpu_interface(uint32_t cpu_index)
-{
-  uint32_t sre_value = 0x7;
-  WRITE_SR(ICC_SRE, sre_value);
-  WRITE_SR(ICC_PMR, GIC_CPUIF_ICCPMR_PRIORITY(0xff));
+  /* Initialize Interrupt Controller Binary Point Register 1 */
+#ifdef BSP_ARM_GIC_ICC_BPR1
+  WRITE_SR(ICC_BPR1, BSP_ARM_GIC_ICC_BPR1);
+#endif
 
   volatile gic_redist *redist = gicv3_get_redist(cpu_index);
   uint32_t waker = redist->icrwaker;
@@ -334,9 +339,20 @@ static void gicv3_init_cpu_interface(uint32_t cpu_index)
     sgi_ppi->icspiprior[id] = PRIORITY_DEFAULT;
   }
 
-  /* Enable interrupt groups 0 and 1 */
-  gic_icc_write(IGRPEN1, 1);
-  WRITE_SR(ICC_CTLR, 0x0);
+  /* Initialize Interrupt Controller Interrupt Group Enable 0 Register */
+#ifdef BSP_ARM_GIC_ICC_IGRPEN0
+  WRITE_SR(ICC_IGRPEN0, BSP_ARM_GIC_ICC_IGRPEN0);
+#endif
+
+  /* Initialize Interrupt Controller Interrupt Group Enable 1 Register */
+#ifdef BSP_ARM_GIC_ICC_IGRPEN1
+  WRITE_SR(ICC_IGRPEN1, BSP_ARM_GIC_ICC_IGRPEN1);
+#endif
+
+  /* Initialize Interrupt Controller Control Register */
+#ifdef BSP_ARM_GIC_ICC_CTRL
+  WRITE_SR(ICC_CTLR, BSP_ARM_GIC_ICC_CTRL);
+#endif
 }
 
 static inline void gicv3_get_attributes(
-- 
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