From 15b6f44deb42867fb208ebe1632f56cdd7a0cd7b Mon Sep 17 00:00:00 2001 From: Chris Johns Date: Mon, 12 Aug 2019 13:58:31 +1000 Subject: arm/tlb: Fix the MP affinity check to invalidate ASIDs. - The TI's CortexA7 MP MPIDR register returns 0 Updates #3760 --- bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'bsps') diff --git a/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c b/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c index cf2d555d18..fae6a6ba79 100644 --- a/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c +++ b/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c @@ -66,7 +66,15 @@ static uint32_t set_translation_table_entries( for ( i = istart; i != iend; i = (i + 1U) & index_mask ) { void *mva = (void *) (i << ARM_MMU_SECT_BASE_SHIFT); #if defined(__ARM_ARCH_7A__) - if ((arm_cp15_get_multiprocessor_affinity() & (1 << 30)) == 0) { + /* + * Bit 31 needs to be 1 to indicate the register implements the + * Multiprocessing Extensions register format and the U (bit 30) + * is 0. + */ + #define MPIDR_MX_FMT (1 << 31) + #define MPIDR_UP (1 << 30) + const uint32_t mpidr = arm_cp15_get_multiprocessor_affinity(); + if ((mpidr & (MPIDR_MX_FMT | MPIDR_UP)) == MPIDR_MX_FMT) { arm_cp15_tlb_invalidate_entry_all_asids(mva); } else -- cgit v1.2.3