From 044687d335c4fc11e90927be5f9a0dec698a5371 Mon Sep 17 00:00:00 2001 From: Hesham Almatary Date: Sun, 31 Mar 2019 13:49:19 +0100 Subject: bsps/riscv: UART - Read reg-shift from DTB to properly set/get registers --- bsps/riscv/riscv/console/console-config.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) (limited to 'bsps') diff --git a/bsps/riscv/riscv/console/console-config.c b/bsps/riscv/riscv/console/console-config.c index 3cd1d89e08..9a8195dda7 100644 --- a/bsps/riscv/riscv/console/console-config.c +++ b/bsps/riscv/riscv/console/console-config.c @@ -161,12 +161,19 @@ static void riscv_console_probe(void) ns16550_context *ctx; fdt32_t *val; int len; + int reg_shift; ctx = &ns16550_instances[ns16550_devices]; ctx->initial_baud = BSP_CONSOLE_BAUD; - if (RISCV_CONSOLE_IS_COMPATIBLE(compat, compat_len, "ns16750")) { - ctx->has_precision_clock_synthesizer = true; + /* Get register shift property of the UART device */ + val = (fdt32_t *) fdt_getprop(fdt, node, "reg-shift", &len); + + if (val) { + reg_shift = fdt32_to_cpu(val[0]); + } + + if (reg_shift == 2) { ctx->get_reg = riscv_console_get_reg_32; ctx->set_reg = riscv_console_set_reg_32; } else { @@ -174,6 +181,10 @@ static void riscv_console_probe(void) ctx->set_reg = riscv_console_set_reg_8; } + if (RISCV_CONSOLE_IS_COMPATIBLE(compat, compat_len, "ns16750")) { + ctx->has_precision_clock_synthesizer = true; + } + ctx->port = (uintptr_t) riscv_fdt_get_address(fdt, node); if (ctx->port == 0) { -- cgit v1.2.3