From 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9 Mon Sep 17 00:00:00 2001 From: Chris Johns Date: Sat, 23 Dec 2017 18:18:56 +1100 Subject: Remove make preinstall A speciality of the RTEMS build system was the make preinstall step. It copied header files from arbitrary locations into the build tree. The header files were included via the -Bsome/build/tree/path GCC command line option. This has at least seven problems: * The make preinstall step itself needs time and disk space. * Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error. * There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult. * The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit. * An introduction of a new build system is difficult. * Include paths specified by the -B option are system headers. This may suppress warnings. * The parallel build had sporadic failures on some hosts. This patch removes the make preinstall step. All installed header files are moved to dedicated include directories in the source tree. Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc, etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g. erc32, imx, qoriq, etc. The new cpukit include directories are: * cpukit/include * cpukit/score/cpu/@RTEMS_CPU@/include * cpukit/libnetworking The new BSP include directories are: * bsps/include * bsps/@RTEMS_CPU@/include * bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include There are build tree include directories for generated files. The include directory order favours the most general header file, e.g. it is not possible to override general header files via the include path order. The "bootstrap -p" option was removed. The new "bootstrap -H" option should be used to regenerate the "headers.am" files. Update #3254. --- bsps/sparc/include/bsp/gr1553b.h | 369 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 369 insertions(+) create mode 100644 bsps/sparc/include/bsp/gr1553b.h (limited to 'bsps/sparc/include/bsp/gr1553b.h') diff --git a/bsps/sparc/include/bsp/gr1553b.h b/bsps/sparc/include/bsp/gr1553b.h new file mode 100644 index 0000000000..006417b530 --- /dev/null +++ b/bsps/sparc/include/bsp/gr1553b.h @@ -0,0 +1,369 @@ +/* GR1553B driver, used by BC, RT and/or BM driver + * + * COPYRIGHT (c) 2010. + * Cobham Gaisler AB. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * OVERVIEW + * ======== + * This driver controls the GR1553B device regardless of interfaces supported + * (BC, RT and/or BM). The device can be located at an on-chip AMBA or an + * AMBA-over-PCI bus. This driver provides an interface for the BC, RT and BM + * drivers to use. Since the different interfaces are accessed over the same + * register interface on the same core, the other drivers must share a GR1553B + * device. Any combination of interface functionality is supported, but the RT + * and BC functionality can nnot be used simultaneously due to hardware + * limitation. + * + */ + +#ifndef __GR1553B_H__ +#define __GR1553B_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* The GR1553B registers */ +struct gr1553b_regs { + /* Common Registers */ + volatile uint32_t irq; /* 0x00 IRQ register */ + volatile uint32_t imask; /* 0x04 IRQ enable mask */ + int unused0[(0x10-0x08)/4]; + volatile uint32_t hwcfg; /* 0x10 HW config register */ + + int unused1[(0x40-0x14)/4]; /* Padding */ + + /* BC Registers */ + volatile uint32_t bc_stat; /* 0x40 BC status */ + volatile uint32_t bc_ctrl; /* 0x44 BC Action register */ + volatile uint32_t bc_bd; /* 0x48 BC transfer list pointer */ + volatile uint32_t bc_abd; /* 0x4c BC async list pointer */ + volatile uint32_t bc_timer; /* 0x50 BC timer register */ + volatile uint32_t bc_wake; /* 0x54 BC wakeup control register */ + volatile uint32_t bc_irqptr; /* 0x58 BC transfer IRQ pointer */ + volatile uint32_t bc_busmsk; /* 0x5C BC per-RT bus mask register */ + + int unused2[(0x68-0x60)/4]; /* Padding */ + + volatile uint32_t bc_slot; /* 0x68 BC Current BD pointer */ + volatile uint32_t bc_aslot; /* 0x6c BC Current async BD pointer */ + + int unused3[(0x80-0x70)/4]; /* Padding */ + + /* RT Registers */ + volatile uint32_t rt_stat; /* 0x80 RT status */ + volatile uint32_t rt_cfg; /* 0x84 RT config register */ + volatile uint32_t rt_stat2; /* 0x88 RT bus status bits */ + volatile uint32_t rt_statw; /* 0x8c RT status words */ + volatile uint32_t rt_sync; /* 0x90 RT bus synchronize */ + volatile uint32_t rt_tab; /* 0x94 RT subaddress table base */ + volatile uint32_t rt_mcctrl; /* 0x98 RT valid mode code mask */ + int unused4[(0xa4-0x9c)/4]; + volatile uint32_t rt_ttag; /* 0xa4 RT time tag register */ + int unused5; /* 0xa8 RESERVED */ + volatile uint32_t rt_evsz; /* 0xac RT event log end pointer */ + volatile uint32_t rt_evlog; /* 0xb0 RT event log position */ + volatile uint32_t rt_evirq; /* 0xb4 RT event log IRQ position */ + + int unused6[(0xc0-0xb8)/4]; /* Padding */ + + /* BM Registers */ + volatile uint32_t bm_stat; /* 0xc0 BM status */ + volatile uint32_t bm_ctrl; /* 0xc4 BM control register */ + volatile uint32_t bm_adr; /* 0xc8 BM address filter */ + volatile uint32_t bm_subadr; /* 0xcc BM subaddress filter */ + volatile uint32_t bm_mc; /* 0xd0 BM mode code filter */ + volatile uint32_t bm_start; /* 0xd4 BM log start address */ + volatile uint32_t bm_end; /* 0xd8 BM log size/alignment mask */ + volatile uint32_t bm_pos; /* 0xdc BM log position */ + volatile uint32_t bm_ttag; /* 0xe0 BM time tag register */ +}; + +#define GR1553BC_KEY 0x15520000 +#define GR1553RT_KEY 0x15530000 + +/* IRQ Definitions */ +#define GR1553BC_IRQLOG_SIZE 64 +#define GR1553BC_IRQLOG_CNT (GR1553BC_IRQLOG_SIZE/sizeof(uint32_t)) + +/*** IRQ Flag Register ***/ +#define GR1553B_IRQ_BCEV_BIT 0 +#define GR1553B_IRQ_BCD_BIT 1 +#define GR1553B_IRQ_BCWK_BIT 2 +#define GR1553B_IRQ_RTEV_BIT 8 +#define GR1553B_IRQ_RTD_BIT 9 +#define GR1553B_IRQ_RTTE_BIT 10 +#define GR1553B_IRQ_BMD_BIT 16 +#define GR1553B_IRQ_BMTOF_BIT 17 + +#define GR1553B_IRQ_BCEV (1<