From f2b08776424c50c71efe441ed04e674b0511b1eb Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Wed, 30 Jun 2021 15:22:57 +0200 Subject: bsps: Fix GICv3 support for AArch32 The GICv3 support is shared between AArch32 and AArch64. For AArch32, the new AARCH64_IS_NONSECURE is never defined. Use ARM_MULTILIB_ARCH_V4 instead. This issue was introduced by 76c6caad52244ab9a14151620a80ff0f71035b6c. There is still a change in bsp_interrupt_vector_enable() for AArch32 compared to the version before 76c6caad52244ab9a14151620a80ff0f71035b6c. --- bsps/shared/dev/irq/arm-gicv3.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'bsps/shared') diff --git a/bsps/shared/dev/irq/arm-gicv3.c b/bsps/shared/dev/irq/arm-gicv3.c index d216f4f5f7..75b089b6b5 100644 --- a/bsps/shared/dev/irq/arm-gicv3.c +++ b/bsps/shared/dev/irq/arm-gicv3.c @@ -176,7 +176,7 @@ void bsp_interrupt_vector_enable(rtems_vector_number vector) volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(_SMP_Get_current_processor()); /* Set interrupt group to 1 in the current security mode */ -#if defined(AARCH64_IS_NONSECURE) +#if defined(ARM_MULTILIB_ARCH_V4) || defined(AARCH64_IS_NONSECURE) sgi_ppi->icspigrpr[0] |= 1 << (vector % 32); sgi_ppi->icspigrpmodr[0] &= ~(1 << (vector % 32)); #else @@ -228,7 +228,7 @@ static void gicv3_init_cpu_interface(void) volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(cpu_index); /* Set interrupt group to 1 in the current security mode */ -#if defined(AARCH64_IS_NONSECURE) +#if defined(ARM_MULTILIB_ARCH_V4) || defined(AARCH64_IS_NONSECURE) sgi_ppi->icspigrpr[0] = 0xffffffff; sgi_ppi->icspigrpmodr[0] = 0; #else @@ -262,7 +262,7 @@ rtems_status_code bsp_interrupt_facility_initialize(void) dist->icdicer[id / 32] = 0xffffffff; /* Set interrupt group to 1 in the current security mode */ -#if defined(AARCH64_IS_NONSECURE) +#if defined(ARM_MULTILIB_ARCH_V4) || defined(AARCH64_IS_NONSECURE) dist->icdigr[id / 32] = 0xffffffff; dist->icdigmr[id / 32] = 0; #else -- cgit v1.2.3