From b5aceef5d921de3d146b45c20f6f8aa7e9413717 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Thu, 10 Dec 2020 10:49:37 +0100 Subject: bsps: Remove gicvx_interrupt_dispatch() Avoid one level of indirection. Update #4202. --- bsps/shared/dev/irq/arm-gicv2.c | 2 +- bsps/shared/dev/irq/arm-gicv3.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'bsps/shared/dev') diff --git a/bsps/shared/dev/irq/arm-gicv2.c b/bsps/shared/dev/irq/arm-gicv2.c index 97f397dffd..74989a4de5 100644 --- a/bsps/shared/dev/irq/arm-gicv2.c +++ b/bsps/shared/dev/irq/arm-gicv2.c @@ -49,7 +49,7 @@ #define CPUIF_ICCICR GIC_CPUIF_ICCICR_ENABLE #endif -void gicvx_interrupt_dispatch(void) +void bsp_interrupt_dispatch(void) { volatile gic_cpuif *cpuif = GIC_CPUIF; uint32_t icciar = cpuif->icciar; diff --git a/bsps/shared/dev/irq/arm-gicv3.c b/bsps/shared/dev/irq/arm-gicv3.c index e23778ea37..65b049cd5a 100644 --- a/bsps/shared/dev/irq/arm-gicv3.c +++ b/bsps/shared/dev/irq/arm-gicv3.c @@ -143,7 +143,7 @@ static volatile gic_sgi_ppi *gicv3_get_sgi_ppi(uint32_t cpu_index) ((uintptr_t)BSP_ARM_GIC_REDIST_BASE + cpu_index * 0x20000 + 0x10000); } -void gicvx_interrupt_dispatch(void) +void bsp_interrupt_dispatch(void) { uint32_t icciar = READ_SR(ICC_IAR1); rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar); -- cgit v1.2.3