From 6b0d3c987349d188b65e9fc8229daeba247928c5 Mon Sep 17 00:00:00 2001 From: Padmarao Begari Date: Mon, 19 Sep 2022 18:30:26 +0530 Subject: bsps/riscv: Add Microchip PolarFire SoC BSP variant The Microchip PolarFire SoC support is implemented as a riscv BSP variant to boot with any individual hart(cpu core) or SMP based on the boot HARTID configurable and support components are 4 CPU Cores (U54), Interrupt controller (PLIC), Timer (CLINT), UART. --- bsps/riscv/riscv/config/mpfs64imafdc.cfg | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 bsps/riscv/riscv/config/mpfs64imafdc.cfg (limited to 'bsps/riscv/riscv/config/mpfs64imafdc.cfg') diff --git a/bsps/riscv/riscv/config/mpfs64imafdc.cfg b/bsps/riscv/riscv/config/mpfs64imafdc.cfg new file mode 100644 index 0000000000..b04e78b0e9 --- /dev/null +++ b/bsps/riscv/riscv/config/mpfs64imafdc.cfg @@ -0,0 +1,9 @@ +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU = riscv + +CPU_CFLAGS = -march=rv64imafdc -mabi=lp64d -mcmodel=medany + +LDFLAGS = -Wl,--gc-sections + +CFLAGS_OPTIMIZE_V ?= -O2 -g -ffunction-sections -fdata-sections -- cgit v1.2.3