From e92bc254530825ae14646520b35efe000699ce74 Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Fri, 17 Dec 2021 10:25:52 -0600 Subject: Remove powerpc/haleakala board Closes #4302. --- bsps/powerpc/haleakala/irq/irq.c | 237 --------------------------------------- 1 file changed, 237 deletions(-) delete mode 100644 bsps/powerpc/haleakala/irq/irq.c (limited to 'bsps/powerpc/haleakala/irq/irq.c') diff --git a/bsps/powerpc/haleakala/irq/irq.c b/bsps/powerpc/haleakala/irq/irq.c deleted file mode 100644 index c9607a032d..0000000000 --- a/bsps/powerpc/haleakala/irq/irq.c +++ /dev/null @@ -1,237 +0,0 @@ -/* - * - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Middleware support for PPC405 by M.Hamel ADInstruments Ltd 2008 - */ - -#include -#include -#include -#include -#include -#include - - -/* PPC405EX UIC numbers */ -#define UIC_DCR_BASE 0xc0 -#define UIC0_SR (UIC_DCR_BASE+0x0) /* UIC status */ -#define UIC0_SRS (UIC_DCR_BASE+0x1) /* UIC status set */ -#define UIC0_ER (UIC_DCR_BASE+0x2) /* UIC enable */ -#define UIC0_CR (UIC_DCR_BASE+0x3) /* UIC critical */ -#define UIC0_PR (UIC_DCR_BASE+0x4) /* UIC polarity */ -#define UIC0_TR (UIC_DCR_BASE+0x5) /* UIC triggering */ -#define UIC0_MSR (UIC_DCR_BASE+0x6) /* UIC masked status */ -#define UIC0_VR (UIC_DCR_BASE+0x7) /* UIC vector */ -#define UIC0_VCR (UIC_DCR_BASE+0x8) /* UIC vector configuration */ - -#define UIC1_SR (UIC_DCR_BASE+0x10) /* UIC status */ -#define UIC1_SRS (UIC_DCR_BASE+0x11) /* UIC status set */ -#define UIC1_ER (UIC_DCR_BASE+0x12) /* UIC enable */ -#define UIC1_CR (UIC_DCR_BASE+0x13) /* UIC critical */ -#define UIC1_PR (UIC_DCR_BASE+0x14) /* UIC polarity */ -#define UIC1_TR (UIC_DCR_BASE+0x15) /* UIC triggering */ -#define UIC1_MSR (UIC_DCR_BASE+0x16) /* UIC masked status */ -#define UIC1_VR (UIC_DCR_BASE+0x17) /* UIC vector */ -#define UIC1_VCR (UIC_DCR_BASE+0x18) /* UIC vector configuration */ - -#define UIC2_SR (UIC_DCR_BASE+0x20) /* UIC status */ -#define UIC2_SRS (UIC_DCR_BASE+0x21) /* UIC status set */ -#define UIC2_ER (UIC_DCR_BASE+0x22) /* UIC enable */ -#define UIC2_CR (UIC_DCR_BASE+0x23) /* UIC critical */ -#define UIC2_PR (UIC_DCR_BASE+0x24) /* UIC polarity */ -#define UIC2_TR (UIC_DCR_BASE+0x25) /* UIC triggering */ -#define UIC2_MSR (UIC_DCR_BASE+0x26) /* UIC masked status */ -#define UIC2_VR (UIC_DCR_BASE+0x27) /* UIC vector */ -#define UIC2_VCR (UIC_DCR_BASE+0x28) /* UIC vector configuration */ - -enum { kUICWords = 3 }; - -static rtems_irq_connect_data* rtems_hdl_tblP; -static rtems_irq_connect_data dflt_entry; - -static uint32_t gEnabledInts[kUICWords]; /* 1-bits mean enabled */ -static uint32_t gIntInhibited[kUICWords]; /* 1-bits disable, overriding gEnabledInts because the interrupt - is being processed in C_dispatch_irq_handler */ - -static inline int IsUICIRQ(const rtems_irq_number irqLine) -{ - return (((int) irqLine <= BSP_UIC_IRQ_MAX_OFFSET) && - ((int) irqLine >= BSP_UIC_IRQ_LOWEST_OFFSET) - ); -} - -static void WriteIState(void) -/* Write the gEnabledInts state masked by gIntInhibited to the hardware */ -{ - PPC_SET_DEVICE_CONTROL_REGISTER(UIC0_ER, - gEnabledInts[0] & ~gIntInhibited[0]); - PPC_SET_DEVICE_CONTROL_REGISTER(UIC1_ER, - gEnabledInts[1] & ~gIntInhibited[1]); - PPC_SET_DEVICE_CONTROL_REGISTER(UIC2_ER, - gEnabledInts[2] & ~gIntInhibited[2]); -} - -void -BSP_enable_irq_at_pic(const rtems_irq_number irq) -/* Enable an interrupt; this can be called from inside C_dispatch_irq_handler */ -{ - if (IsUICIRQ(irq)) { - /* Set relevant bit in the state, write state to the UIC */ - gEnabledInts[irq>>5] |= (0x80000000 >> (irq & 0x1F)); - WriteIState(); - } -} - -int -BSP_disable_irq_at_pic(const rtems_irq_number irq) -/* Enable an interrupt; this can be called from inside C_dispatch_irq_handler */ -{ - if (IsUICIRQ(irq)) { - uint32_t oldState; - int iword = irq>>5; - uint32_t mask = (0x80000000 >> (irq & 0x1F)); - - oldState = gEnabledInts[iword] & mask; - gEnabledInts[iword] &= ~mask; - WriteIState(); - return oldState ? 1 : 0; - } else - return -1; -} - -int -BSP_setup_the_pic(rtems_irq_global_settings* config) -{ - int i; - - dflt_entry = config->defaultEntry; - rtems_hdl_tblP = config->irqHdlTbl; - for (i=0; i> bit; - switch (index) { - case 0: - PPC_SET_DEVICE_CONTROL_REGISTER(UIC0_SR, bmask); - break; - case 1: - PPC_SET_DEVICE_CONTROL_REGISTER(UIC1_SR, bmask); - break; - case 2: - PPC_SET_DEVICE_CONTROL_REGISTER(UIC2_SR, bmask); - break; - } - - /* Clear in the active record and gIntInhibited */ - active[index] &= ~bmask; - gIntInhibited[index] &= ~bmask; - }; - - /* Update the hardware again so the interrupts we have handled are unmasked */ - WriteIState(); - return 0; - - } else if (excNum == ASM_DEC_VECTOR) { /* 0x1000 remapped by C_dispatch_dec_handler_bookE */ - bsp_irq_dispatch_list(rtems_hdl_tblP, BSP_PIT, dflt_entry.hdl); - return 0; - - } else if (excNum == ASM_BOOKE_FIT_VECTOR) { /* 0x1010 mapped to 0x13 by ppc_get_vector_addr */ - bsp_irq_dispatch_list(rtems_hdl_tblP, BSP_FIT, dflt_entry.hdl); - return 0; - - } else if (excNum == ASM_BOOKE_WDOG_VECTOR) { /* 0x1020 mapped to 0x14 by ppc_get_vector_addr */ - bsp_irq_dispatch_list(rtems_hdl_tblP, BSP_WDOG, dflt_entry.hdl); - return 0; - - } else - return -1; /* unhandled interrupt, panic time */ -} - -- cgit v1.2.3