From 1efa1c8389604dcf303b9acfa26c0ae60db9d9b4 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Fri, 20 Apr 2018 13:38:33 +0200 Subject: bsps: Move MPCI support to bsps This patch is a part of the BSP source reorganization. Update #3285. --- bsps/no_cpu/no_bsp/mpci/addrconv.c | 28 +++++++++++++ bsps/no_cpu/no_bsp/mpci/getcfg.c | 73 +++++++++++++++++++++++++++++++++ bsps/no_cpu/no_bsp/mpci/lock.c | 84 ++++++++++++++++++++++++++++++++++++++ bsps/no_cpu/no_bsp/mpci/mpisr.c | 44 ++++++++++++++++++++ 4 files changed, 229 insertions(+) create mode 100644 bsps/no_cpu/no_bsp/mpci/addrconv.c create mode 100644 bsps/no_cpu/no_bsp/mpci/getcfg.c create mode 100644 bsps/no_cpu/no_bsp/mpci/lock.c create mode 100644 bsps/no_cpu/no_bsp/mpci/mpisr.c (limited to 'bsps/no_cpu/no_bsp') diff --git a/bsps/no_cpu/no_bsp/mpci/addrconv.c b/bsps/no_cpu/no_bsp/mpci/addrconv.c new file mode 100644 index 0000000000..2656bc1ccf --- /dev/null +++ b/bsps/no_cpu/no_bsp/mpci/addrconv.c @@ -0,0 +1,28 @@ +/* Shm_Convert_address + * + * No address range conversion is required. + * + * Input parameters: + * address - address to convert + * + * Output parameters: + * returns - converted address + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include +#include +#include + +void *Shm_Convert_address( + void *address +) +{ + return ( address ); +} diff --git a/bsps/no_cpu/no_bsp/mpci/getcfg.c b/bsps/no_cpu/no_bsp/mpci/getcfg.c new file mode 100644 index 0000000000..2179838b4b --- /dev/null +++ b/bsps/no_cpu/no_bsp/mpci/getcfg.c @@ -0,0 +1,73 @@ +/* void Shm_Get_configuration( localnode, &shmcfg ) + * + * This routine initializes, if necessary, and returns a pointer + * to the Shared Memory Configuration Table for the XXX target. + * + * INPUT PARAMETERS: + * localnode - local node number + * shmcfg - address of pointer to SHM Config Table + * + * OUTPUT PARAMETERS: + * *shmcfg - pointer to SHM Config Table + * +XXX: FIX THE COMMENTS BELOW WHEN THE CPU IS KNOWN + * NOTES: The XYZ does not have an interprocessor interrupt. + * + * The following table illustrates the configuration limitations: + * + * BUS MAX + * MODE ENDIAN NODES + * ========= ====== ======= + * POLLED BIG 2+ + * INTERRUPT **** NOT SUPPORTED **** + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include +#include +#include + +/* + * configured if currently polling of interrupt driven + */ + +#define INTERRUPT 0 /* XXX: */ +#define POLLING 1 /* XXX: fix me -- is polling ONLY!!! */ + +shm_config_table BSP_shm_cfgtbl; + +void Shm_Get_configuration( + uint32_t localnode, + shm_config_table **shmcfg +) +{ + BSP_shm_cfgtbl.base = 0x0; + BSP_shm_cfgtbl.length = 1 * MEGABYTE; + BSP_shm_cfgtbl.format = SHM_BIG; + + /* + * Override cause_intr or shm_isr if your target has + * special requirements. + */ + + BSP_shm_cfgtbl.cause_intr = Shm_Cause_interrupt; + +#ifdef NEUTRAL_BIG + BSP_shm_cfgtbl.convert = NULL_CONVERT; +#else + BSP_shm_cfgtbl.convert = CPU_swap_u32; +#endif + + BSP_shm_cfgtbl.poll_intr = POLLED_MODE; + BSP_shm_cfgtbl.Intr.address = NO_INTERRUPT; + BSP_shm_cfgtbl.Intr.value = NO_INTERRUPT; + BSP_shm_cfgtbl.Intr.length = NO_INTERRUPT; + + *shmcfg = &BSP_shm_cfgtbl; +} diff --git a/bsps/no_cpu/no_bsp/mpci/lock.c b/bsps/no_cpu/no_bsp/mpci/lock.c new file mode 100644 index 0000000000..5b53df8d38 --- /dev/null +++ b/bsps/no_cpu/no_bsp/mpci/lock.c @@ -0,0 +1,84 @@ +/* Shared Memory Lock Routines + * + * This shared memory locked queue support routine need to be + * able to lock the specified locked queue. Interrupts are + * disabled while the queue is locked to prevent preemption + * and deadlock when two tasks poll for the same lock. + * previous level. + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include +#include +#include + +/* + * Shm_Initialize_lock + * + * Initialize the lock for the specified locked queue. + */ + +void Shm_Initialize_lock( + Shm_Locked_queue_Control *lq_cb +) +{ + lq_cb->lock = LQ_UNLOCKED; +} + +/* void _Shm_Lock( &lq_cb ) + * + * This shared memory locked queue support routine locks the + * specified locked queue. It disables interrupts to prevent + * a deadlock condition. + */ + +void Shm_Lock( + Shm_Locked_queue_Control *lq_cb +) +{ + uint32_t isr_level; + uint32_t *lockptr = (uint32_t*) &lq_cb->lock; + uint32_t lock_value; + + lock_value = 0x80000000; + rtems_interrupt_disable( isr_level ); + + Shm_isrstat = isr_level; + while ( lock_value ) { + __asm__ volatile( "" + : "=r" (lockptr), "=r" (lock_value) + : "0" (lockptr), "1" (lock_value) + ); + /* + * If not available, then may want to delay to reduce load on lock. + * + * NOTE: BSP must initialize the counter facility. Delay value is BSP + * dependent. + */ + if ( lock_value ) + rtems_counter_delay_nanoseconds( 100 ); + } +} + +/* + * Shm_Unlock + * + * Unlock the lock for the specified locked queue. + */ + +void Shm_Unlock( + Shm_Locked_queue_Control *lq_cb +) +{ + uint32_t isr_level; + + lq_cb->lock = SHM_UNLOCK_VALUE; + isr_level = Shm_isrstat; + rtems_interrupt_enable( isr_level ); +} diff --git a/bsps/no_cpu/no_bsp/mpci/mpisr.c b/bsps/no_cpu/no_bsp/mpci/mpisr.c new file mode 100644 index 0000000000..19939ec81c --- /dev/null +++ b/bsps/no_cpu/no_bsp/mpci/mpisr.c @@ -0,0 +1,44 @@ +/** + * @file + * + * Template for Shared Memory Driver Interrupt Support + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include +#include +#include + +rtems_isr Shm_isr_nobsp(rtems_vector_number ignored) +{ + /* + * If this routine has to do anything other than the mpisr.c + * found in the generic driver, then copy the contents of the generic + * mpisr.c and augment it to satisfy this particular board. Typically, + * you need to have a board specific mpisr.c when the interrupt + * must be cleared. + * + * If the generic mpisr.c satisifies your requirements, then + * remove this routine from your target's shmsupp/mpisr.c file. + * Then simply install the generic Shm_isr in the Shm_setvec + * routine below. + */ +} + +/* + * This driver routine sets the SHM interrupt vector to point to the + * driver's SHM interrupt service routine. + */ + +void Shm_setvec( void ) +{ + /* XXX: FIX ME!!! */ +} -- cgit v1.2.3